PROCESS CP716V Small Signal Transistors PNP - High Voltage Transistor Chip PROCESS DETAILS Process EPITAXIAL PLANAR Die Size 20 x 20 MILS Die Thickness 7.1 MILS Base Bonding Pad Area 4.0 x 4.0 MILS Emitter Bonding Pad Area 4.7 x 4.7 MILS Top Side Metalization Al - 30,000Å Back Side Metalization Au - 18,000Å GEOMETRY GROSS DIE PER 4 INCH WAFER 29,659 PRINCIPAL DEVICE TYPES CMUT5401 CMPT5401 CXT5401 BACKSIDE COLLECTOR 145 Adams Avenue Hauppauge, NY 11788 USA Tel: (631) 435-1110 Fax: (631) 435-1824 www.centralsemi.com R0 (9- May 2005) PROCESS CP716V Typical Electrical Characteristics 145 Adams Avenue Hauppauge, NY 11788 USA Tel: (631) 435-1110 Fax: (631) 435-1824 www.centralsemi.com R0 (9- May 2005)