FAIRCHILD AN-9050

www.fairchildsemi.com
AN-9050
FDMF6704 Power Loss Calculation
YoungSub Jeong
Introduction
The FDMF6704 DrMOS MCM (Multi Chip Module)
product has HS and LS FETs and a gate driver all contained
within a single module. The design has been optimized for
Synchronous Buck applications. The switching and
conduction loss of each HS FET, LS FET and gate driver
are critical for system and application design. Generally it is
hard to get measurement of each internal loss because of its
MCM structure. Instead of measuring each power loss
elements, expression of module power loss have been used
to show MCM product power related performance. Module
power loss is defined to be all power losses dissipated by
DrMOS module itself. It includes all HS FET, LS FET and
gate driver power losses. Using this approach, a system
designer can easily estimate total power loss of the system,
and do easy and convenient predictions of design related
application performance. This application note explains
basic theory of module power loss, and how to use the
module power loss calculation tool. It is easy and
convenient to use the power loss calculator when the system
designer does a particular application design.
MCCC Application Engineering
FDMF6704 are optimized for a 5 V power rail in computing
applications. Both pins are normally connected to each
other in an application. The VSWH pin is the switch node
of Synchronous Buck converter. It is connected to the
internal HS FET source and LS FET drain. As a point of
view of a module product, VIN, VCIN and VDRV are
inputs and VSWH is output. The module power loss and
efficiency are defined by formulas as below.
z
Module Power Loss
= Module input power – Module output power
= (Pin + Pcin&Pdrv) – Psw [W]
z
Module Efficiency
= Module output power / Module input power
= Psw / (Pin + Pcin&Pdrv) * 100 [%]
Power Loss of DrMOS
Figure 1 shows a typical Synchronous Buck application
circuit using an FDMF6704 DrMOS product. The
application schematic is based on a Fairchild Semiconductor
FDMF6704 evaluation board which is used for datasheet
characterization testing. The circuit includes all components
in a Sync Buck converter except for the PWM controller.
The PWM control function is accomplished by external
voltage compensation loop using a pulse generator and a PC
automation program. All passive components and layout,
such as input caps, output caps, output inductor and boot
cap, are optimized for DrMOS products.
Power loss sense point pins of FDMF6704 are VIN, VCIN,
VDRV and VSWH. VIN is an input pin for main DC/DC
power converting. It is connected to the internal HS FET
drain. The current into VIN is related to HS FET switching
and conduction losses. Its voltage level is typically 12 V in
computing application. The VCIN pin is connected to the
VCC of internal gate drive logic. The VDRV pin is used for
HS and LS FET gate driving voltage. VCIN & VDRV of
© 2007 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 7/14/09
Figure 1. Typical Application Circuit of FDMF6704
The primary power loss elements in a Sync Buck converter
are the switching devices and the output inductor. Silicon
conduction and switching loss represent the largest element
of the power loss in a typical Sync Buck converter.
Normally inductor power loss is added to silicon loss to
determine the system total performance. Key points of good
inductor design include saturation current (adequate to
handle peak transients), low DCR, core type, low noise and
thermal characteristics. With a properly chosen inductor,
module power loss is essentially independent of inductor
power loss. Since we want to focus on silicon loss tradeoffs,
we will use module power loss as our figure of merit to
compare MCM designs.
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APP NOTE NUMBER
APPLICATION NOTE
Table 1 and Table 2 show an example of power loss
definition, measurement and calculation. A Fairchild
FDMF6704 evaluation board was used for the testing. Note
that module power loss without inductor power loss makes
SW node efficiency higher than output node efficiency.
Inductor power loss is 0.64 W and it makes output
efficiency 1.3 % lower than SW node efficiency. If the
inductor value is not optimized, the whole system
performance as well as DrMOS will be affected and
decreased. All input/output voltage and current are
measured with precise DMM and current shunt resistors for
accurate data capture.
Power Loss Measurement
Figure 2 shows the power loss diagram of a Fairchild
DrMOS evaluation board. The input powers are PIN, PCIN
and PDRV. Output power of the module is PSW. POUT is
total board output power after power loss of the inductor.
POUT is connected to Load.
Pcin&
Pdrv
PLmodule
DrMOS
FDMF
6704
Pin
PLinductor
[email protected]
Psw
[email protected]
Output
Inductor
Pout
Load
Power Loss Graph in Datasheet
The evaluation board total efficiency, SW node efficiency
and module power loss are measured and calculated to
represent DrMOS product performance in the datasheet.
The FDMF6704 datasheet has several graphs which indicate
module power loss, output current, normalized module
power loss and each design parameter variations. Figure 3
shows an example of a graph in the datasheet for module
power loss vs. output current.
Figure 2. Ploss Diagram of FDMF6704 Eval Board
When designing a Sync Buck application, critical design
parameters are input/output voltage, output current,
switching frequency and inductor value. Typically input and
output voltages are decided by the system application.
Switching frequency and output inductor are then optimized
to get the best trade-off among dynamic performance, EMI,
thermal, BOM, cost, etc.
Using module power loss as a figure of merit, it is easy to
judge which DrMOS design point is better or not since the
module power loss does not include the inductor power
loss. In other words, even using different inductors, module
power loss can specify the real and accurate power loss of
module itself and it is only slightly affected by inductor
power loss, if the inductor value is correct and the
application design is optimized.
PIN
VIN x IIN [W]
PCIN&PDRV
VCIN x ICIN [W] (including PDRV)
PSW
VSW x IOUT [W]
POUT
VOUT x IOUT [W]
PLmodule
PIN + PCIN&PDRV – PSW [W]
PLinductor
PSW – POUT [W]
[email protected]
PSW/(PIN+PCIN&PDRV)*100 [%]
[email protected]
POUT/(PIN+PCIN&PDRV)*100
[%]
Figure 3. Module Power Loss vs. Iout
Figure 3 represents a performance of FDMF6704 with
particular parameter values, such as VIN=12 V, VOUT=1.3
V, LOUT=440 nH, Fsw=350 kHz and output current from 0
to 35 A. This graph shows a performance under specific
condition. In order to use the datasheet graphs easily in
various system designs, normalized power loss graphs for
each key parameter are included in the datasheet. In the
Figure 4, power loss of the module is plotted with a
normalized value according to the output voltage change.
The reference value of module power loss for normalization
is chosen as 1.3 Vout because this voltage is typical in a
computing application, such as multi-phase VRD for Vcore.
When the output voltage is 2 V, normalized module power
loss will be around 1.13 times higher compared to 1.3 Vout.
Table 1. Power, Power Loss and Efficiency
Total
Pin
[W]
46.49
PLmod
Psw
PLind
Pout
[W]
6.771
[W]
39.72
[W]
0.64
[W]
39.08
Effi
@SW
[%]
85.44
Effi
@Out
[%]
84.06
Table 2. Power Loss Example at 30A Load
© 2007 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 7/14/09
www.fairchildsemi.com
2
APP NOTE NUMBER
APPLICATION NOTE
Calculation Example of Power Loss
All power loss graphs in the FDMF6704 datasheet are
generated from measured evaluation board test data. System
designer can calculate module power loss with normalized
power loss graphs, and estimate performance of the module
and application. Examples below show how to calculate
module power loss with normalized power loss graphs in
datasheet.
z
Example 1
1. Define design parameters
Vin=12 V
Figure 4. Normalized Module Ploss vs. Vout
Vcin & Vdrv=5 V
Vout=1.5 V
Iout=30 A
FDMF6704 Evaluation Board
Fsw=600 kHz
The FDMF6704 evaluation board is used for FDMF6704
electrical characterization test. The board specifications and
structure are shown in Table 3.
Inductor=440 nH
2. Calculate each steps
Dimension
15 x 15 cm
No. of layers
4 layers
Layer sequence
TOP-GND-PWR-BOT
Total thickness
1.6 mm
- Find normalized value of module power loss with
Figure 4 when Vout is 1.5 V Æ 1.04
TOP and BOT
1.5 oz (1 oz base + 0.5 oz plating)
- Multiply 6.8 W by 1.04 Æ 7.072 W
GND and PWR
1 oz
- Find normalized value of module power loss with
Figure 5 when Fsw is 600 kHz Æ 1.12
- Find reference design parameter values and
module power loss with Figure 3 Æ 6.8 W with 12
Vin, 5 Vcin, 1.3 Vout, 30 A, 350 kHz and 440 nH
Table 3. Evaluation Board Spec. and Structure
- Multiply 7.072 W by 1.12. Æ 7.921 W
- The calculated module power loss is 7.921 W.
Table 4 shows reference test condition of evaluation board.
VIN
12 V
VCIN & VDRV
5V
VOUT
1.3 V
PWM HI/LO
5 V/0 V
FSW
350 kHz
IOUT
0~35 A, 5 A step
Soaking time
5 minutes
LOUT
440 nH/0.32 mOhms/35 A
Snubber
Not used
Air flow
Not used
Heat sink
Not used
Ambient Temp.
25 C
Figure 5. Normalized Module Ploss vs. Fsw
In this example 1, two design parameters, such as Vout and
Fsw, are changed from reference values. The calculated
module power loss shows under 0.5 % error compared to
the real lab test data. Table 5 shows the module power loss
Table 4. Evaluation Board Reference Test Condition
© 2007 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 7/14/09
www.fairchildsemi.com
3
APP NOTE NUMBER
APPLICATION NOTE
error between calculated result with datasheet graphs and
real lab data from test.
Calculated
Real
Module Ploss
Module Ploss
7.921 W
7.96 W
Ploss Error
(1-7.921/7.96)*100
=0.495 %
Table 5. Power Loss Error of Example 1
z
Example 2
1. Define design parameters
Vin=10 V
Figure 6. Normalized Module Ploss vs. Vin
Vcin & Vdrv=5.5 V
Vout=2 V
Iout=25 A
Fsw=600 kHz
Inductor=320 nH
2. Calculate each steps
- Find reference design parameter values and
module power loss with Figure 3 Æ 4.6 W with 12
Vin, 5 Vcin, 1.3 Vout, 25 A, 350 kHz and 440 nH
- Ploss at 10 Vin. Note Figure 6:
4.6 W * 1.016 = 4.674 W
- Ploss at 10 Vin and 5.5 Vcin. Note Figure 7
4.674 W * 0.957 = 4.473 W
- Ploss at 10 Vin, 5.5 Vcin and 2 Vout. Note Figure
4:
Figure 7. Normalized Module Ploss vs. Vcin&Vdrv
4.473 W * 1.13 = 5.054 W
- Ploss at 10 Vin, 5.5 Vcin, 2 Vout and 600 kHz.
Note Figure 5:
5.054 W * 1.12 = 5.661 W
- Ploss at 10 Vin, 5.5 Vcin, 2 Vout, 600 kHz and
320 nH. Note Figure 8:
5.661 W * 1.007 = 5.7 W
- The calculated module power loss is 5.7 W. The
error between calculated and real data is around
3.8 %. See Table 6 below for error calculation.
Calculated
Real
Module Ploss
Module Ploss
5.7 W
5.489 W
Ploss Error
(1-5.7/5.489)*100
Figure 8. Normalized Module Ploss vs. Lout
=-3.844 %
Table 6. Power Loss Error of Example 2
© 2007 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 7/14/09
www.fairchildsemi.com
4
APP NOTE NUMBER
APPLICATION NOTE
Figure 11 shows a chart which depicts the calculated
efficiency and power loss at module. The user is able to use
this chart on another document by copying and pasting.
FDMF6704 Ploss Calculation Tool
In order to get quick and accurate performance estimation,
the automatic power loss calculation tool was developed
using concepts mentioned in the previous paragraph. The
calculator excel file can be used for estimating FDMF6704
performance regarding power loss and efficiency. Figure 9
shows the table for parameter input. The yellow cells are
user input parameters and the blue cells are calculated
parameters by internal logic of excel file. Once the user
inputs parameter value into the yellow cells, the sheet
automatically calculates power loss, efficiency and module
temperature, and also generates performance related charts.
Note that each user input parameter has a minimum input
step. For example, the “VIN” parameter has input range
from 5 V to 16 V with 0.5 V step. The “Recommended
OUTL” parameter shows a calculated inductor value
according to other parameter input. The user can enter this
“Recommended OUTL” value into the yellow “OUTL
Value” cell. The “Δ IL Ratio Value” depends on application
design related to output voltage ripple. The user inputs this
value from 20 % to 30 % of Iout for normal Sync Buck
application.
Calculated SW Node Efficiency and Ploss
100
14
95
12
[email protected] [%]
10
85
8
80
6
75
PD_module [W]
90
4
70
[email protected] [%]
65
2
PD_MOD [W]
0
60
0
5
10
15
20
Iout [A]
25
30
35
40
Figure 11. Calculated Efficiency and Power Loss Chart
Figure 12 is another example of a chart for module
temperature. This chart can be also copied or pasted for end
user documentation.
Calculated Module Case Top Temp. and Ploss
140
14
120
12
100
10
80
8
60
6
40
4
Figure 10 is a table which is generated by input parameter
values. All design parameters, input/output powers,
efficiencies and module case top temperature are generated
automatically. The red values mean a warning for overspecification of FDMF6704 maximum current and module
temperature. For example, current of 35 A would make
10.93 W module power loss and 145 C module case top
temperature. The user should consider specification of
FDMF6704 and application when using this design tool.
2
PD_MOD [W]
0
0
0
5
10
15
20
Iout [A]
25
30
35
40
Figure 12. Calculated Module Temp. and Ploss Chart
The data used for this tool is based on a real lab test data,
and the models of each parameter are extracted with multi
element polynomial equations. So its accuracy is good
enough to check brief power loss related to performance of
FDMF6704. Typical power loss calculation error of this
tool at max load is under 5 % compared to real data. Note
that some application at various customers would show
different performance, if their application circuit,
components, board layout and structure are significantly
different from Fairchild evaluation board environment. The
internal parameters, equations and calculating logic are
Fairchild confidential since they are directly related to the
HS FET, LS FET and gate driver electrical characteristics.
The locked version of FDMF6704 power loss calculator
Figure 10. Calculated Power Loss and Efficiency
© 2007 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 7/14/09
MOD_TEMP [C]
20
PD_module [W]
Module Temp. [C
Figure 9. Input Parameters of Ploss Calculation Tool
www.fairchildsemi.com
5
APP NOTE NUMBER
APPLICATION NOTE
tool will be provided to customers so that its internal
parameters should not be opened to outside. If the user
would like to use an unlocked version, please contact to
Fairchild staff.
Summary
Fairchild DrMOS FDMF6704 is a multi-chip module
product for Sync Buck applications. To specify its
performance, the concept of module power loss
measurement and calculation is developed. Normalized
power loss graphs are added in the datasheet to let the
system designer use them for designing various
applications. The graphs are based on the real lab test data
and have a good accuracy. To support easy and convenient
application design, the FDMF6704 automatic power loss
calculation tool has been developed. The tool accuracy is a
good to match to real data so that the designer is able to use
this tool to know how much FDMF6704 application
consumes power loss and how the performance it shows,
before system design and test.
Related Documents
FDMF6704 Datasheet:
FDMF6704A Datasheet:
FDMF6704V Datasheet:
FDMF6704/A Power Loss Calculator REV0:
FDMF6704V Power Loss Calculator REV0:
© 2007 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 7/14/09
www.fairchildsemi.com
6
APP NOTE NUMBER
APPLICATION NOTE
DISCLAIMER
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HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE
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PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1.
Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body, or
(b) support or sustain life, or (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in significant injury to the user.
© 2007 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 7/14/09
2.
A critical component is any component of a life support
device or system whose failure to perform can be reasonably
expected to cause the failure of the life support device or
system, or to affect its safety or effectiveness.
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