CY7C1041BN 256 K × 16 Static RAM Features Functional Description ■ Temperature ranges ❐ Commercial: 0 °C to 70 °C ❐ Industrial: –40 °C to 85 °C ❐ Automotive-A: –40 °C to 85 °C ■ High speed ❐ tAA = 15 ns ■ Low active power ❐ 1540 mW (max.) ■ Low CMOS standby power (L version) ❐ 2.75 mW (max.) ■ 2.0 V data retention (400 μW at 2.0 V retention) ■ Automatic power-down when deselected ■ TTL-compatible inputs and outputs ■ Easy memory expansion with CE and OE features ■ Available in Pb-free and non Pb-free 44-pin TSOP II and molded 44-pin (400-Mil) SOJ packages The CY7C1041BN is a high-performance CMOS static RAM organized as 262,144 words by 16 bits. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A17). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A17). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of read and write modes. The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1041BN is available in a standard 44-pin 400-mil-wide body width SOJ and 44-pin TSOP II package with center power and ground (revolutionary) pinout. Selection Guide Description -15 Maximum access time Maximum operating current 15 20 ns 190 170 mA Industrial 210 190 – – 190 – mA Commercial 3 3 0.5 0.5 Industrial 6 6 Automotive-A – 6 Commercial L Cypress Semiconductor Corporation Document #: 001-06496 Rev. *E • Unit Commercial Automotive-A Maximum CMOS standby current -20 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised May 12, 2011 [+] Feedback CY7C1041BN A0 A1 A2 A3 A4 A5 A6 A7 A8 Row Decoder Input Buffer 256 K x 16 Array Sense Amps Logic Block Diagram I/O0–I/O7 I/O8–I/O15 A9 A10 A 11 A 12 A 13 A14 A15 A16 A17 Column Decoder BHE WE CE OE BLE Document #: 001-06496 Rev. *E Page 2 of 13 [+] Feedback CY7C1041BN Contents Pin Configuration ............................................................. 4 Maximum Ratings ............................................................. 5 Operating Range ............................................................... 5 Electrical Characteristics Over the Operating Range .. 5 Capacitance ...................................................................... 6 AC Test Loads and Waveforms ....................................... 6 Switching Characteristics[4] Over the Operating Range 6 Data Retention Characteristics Over the Operating Range (L version only) ................... 7 Data Retention Waveform ................................................ 7 Switching Waveforms ...................................................... 8 Read Cycle No. 1 ........................................................ 8 Read Cycle No. 2 (OE Controlled) .............................. 8 Write Cycle No. 1 (CE Controlled) ............................... 9 Write Cycle No. 2 (BLE or BHE Controlled) ................ 9 Write Cycle No. 3 (WE Controlled, OE LOW) ........... 10 Document #: 001-06496 Rev. *E Truth Table ...................................................................... 10 Ordering Information ...................................................... 11 Ordering Code Definition ........................................... 11 Package Diagrams .......................................................... 12 Acronyms ........................................................................ 12 Document Conventions ................................................. 12 Units of Measure ....................................................... 12 Sales, Solutions, and Legal Information ...................... 13 Worldwide Sales and Design Support ....................... 13 Products .................................................................... 13 PSoC Solutions ......................................................... 13 Page 3 of 13 [+] Feedback CY7C1041BN Pin Configuration SOJ TSOP II Top View A0 A1 A2 A3 A4 CE I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A5 A6 A7 A8 A9 Document #: 001-06496 Rev. *E 1 44 2 3 43 42 4 41 40 39 38 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A17 A16 A15 OE BHE BLE I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 NC A14 A13 A12 A11 A10 Page 4 of 13 [+] Feedback CY7C1041BN Maximum Ratings (Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested.) Operating Range Storage temperature ................................ –65 °C to +150 °C Range Ambient temperature with power applied ........................................... –55 °C to +125 °C Commercial Ambient Temperature[2] VCC 0 °C to +70 °C 5 V ± 0.5 Supply voltage on VCC to relative GND .....–0.5 V to +7.0 V Industrial –40 °C to +85 °C DC voltage applied to outputs in High Z State[1] .................................. –0.5 V to VCC + 0.5 V Automotive-A –40 °C to +85 °C [1] DC input voltage[1] ............................... –0.5 V to VCC + 0.5 V Current into outputs (LOW) ......................................... 20 mA Electrical Characteristics Over the Operating Range Parameter Description –15 Test Conditions –20 Max Min Max 2.4 – 2.4 – V – 0.4 – 0.4 V V VOH Output HIGH voltage VCC = Min, IOH = –4.0 mA VOL Output LOW voltage VCC = Min, IOL = 8.0 mA VIH Input HIGH voltage – 2.2 VCC + 0.5 2.2 VCC + 0.5 – voltage[1] Unit Min VIL Input LOW –0.5 0.8 –0.5 0.8 V IIX Input load current GND < VI < VCC –1 +1 –1 +1 µA IOZ Output leakage current GND < VOUT < VCC, Output Disabled –1 +1 –1 +1 µA ICC VCC operating supply current VCC = Max, f = fMAX = 1/tRC Comm’l – 190 – 170 mA Ind’l – 210 – 190 mA Auto-A – – – 190 mA ISB1 Automatic CE Power-down current—TTL inputs Max VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fMAX – 40 – 40 mA ISB2 Automatic CE power-down current —CMOS inputs Max VCC, CE > VCC – 0.3 V, Comm’l VIN > VCC – 0.3 V, Comm’l L or VIN < 0.3 V, f = 0 Ind’l – 3 – 3 mA – 0.5 – 0.5 mA – 6 – 6 mA – 6 mA Auto-A – Notes 1. VIL (min.) = –2.0 V for pulse durations of less than 20 ns. 2. TA is the case temperature. Document #: 001-06496 Rev. *E Page 5 of 13 [+] Feedback CY7C1041BN Capacitance Parameter[3] Description CIN Input capacitance COUT I/O capacitance Test Conditions Max Unit 8 pF 8 pF TA = 25 °C, f = 1 MHz, VCC = 5.0 V AC Test Loads and Waveforms R1 481 Ω 5V All Input Pulses R1 481Ω 5V Output 3.0 V 90% Output R2 255 Ω 30 pF Including JIG and Scope R2 255 Ω 5 pF Including JIG and Scope (a) 90% 10% 10% GND ≤ 3 ns ≤ 3 ns (b) Equivalent to: Output Thé venin Equivalent 167 Ω 1.73 V Switching Characteristics[4] Over the Operating Range Parameter Description –15 Min –20 Max Min Max Unit Read Cycle tpower VCC(typical) to the First Access[5] 1 – 1 – μs tRC Read Cycle Time 15 – 20 – ns tAA Address to Data Valid – 15 20 ns tOHA Data Hold from Address Change 3 – 3 – ns tACE CE LOW to Data Valid – 15 – 20 ns tDOE OE LOW to Data Valid – 7 – 8 ns tLZOE OE LOW to Low Z 0 – ns 8 ns – ns 8 ns tHZOE OE HIGH to High 0 – Z[6, 7] – 7 [7] tLZCE CE LOW to Low Z 3 – tHZCE CE HIGH to High Z[6, 7] – 7 3 tPU CE LOW to Power-Up 0 – 0 – ns tPD CE HIGH to Power-Down – 15 – 20 ns tDBE Byte Enable to Data Valid – 7 – 8 ns tLZBE Byte Enable to Low Z 0 – 0 – ns tHZBE Byte Disable to High Z – 7 – 8 ns Notes 3. Tested initially and after any design or process changes that may affect these parameters. 4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 5. This part has a voltage regulator which steps down the voltage from 5 V to 3.3 V internally. tpower time has to be provided initially before a read/write operation is started. 6. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. Document #: 001-06496 Rev. *E Page 6 of 13 [+] Feedback CY7C1041BN Switching Characteristics[4] Over the Operating Range (continued) Parameter –15 Description –20 Min Max Min Max Unit Write Cycle[11, 12] tWC Write Cycle Time 15 – 20 – ns tSCE CE LOW to Write End 12 – 13 – ns tAW Address Set-Up to Write End 12 – 13 – ns tHA Address Hold from Write End 0 – 0 – ns tSA Address Set-Up to Write Start 0 – 0 – ns tPWE WE Pulse Width 12 – 13 – ns tSD Data Set-Up to Write End 8 – 9 – ns tHD Data Hold from Write End 0 – 0 – ns Z[10] tLZWE WE HIGH to Low 3 – 3 – ns tHZWE WE LOW to High Z[9, 10] – 7 – 8 ns tBW Byte Enable to End of Write 12 – 13 – ns Min Max Unit Data Retention Characteristics Over the Operating Range (L version only) Parameter Conditions[14] Description VDR VCC for Data Retention – ICCDR Data Retention Current tCDR[8] Chip Deselect to Data Retention Time VCC = VDR = 2.0 V, CE > VCC – 0.3 V, VIN > VCC – 0.3 V or VIN < 0.3 V tR [13] Operation Recovery Time 2.0 – V – 200 μA 0 – ns tRC – ns Data Retention Waveform Data Retention Mode VCC 3.0 V tCDR VDR > 2 V 3.0 V tR CE Notes 8. Tested initially and after any design or process changes that may affect these parameters. 9. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 10. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 11. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 12. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. 13. tr < 3 ns for the –15 speed. tr < 5 ns for the -20 and slower speeds. 14. No input may exceed VCC + 0.5 V. Document #: 001-06496 Rev. *E Page 7 of 13 [+] Feedback CY7C1041BN Switching Waveforms Read Cycle No. 1[15, 16] tRC Address tAA tOHA Data Out Previous Data Valid Data Valid Read Cycle No. 2 (OE Controlled)[16, 17] Address tRC CE tACE OE tHZOE tDOE BHE, BLE tLZOE tHZCE tDBE tLZBE Data Out High Impedance High Impedance Data Valid tLZCE VCC Supply Current tHZBE tPD tPU 50% ICC 50% ISB Notes 15. Device is continuously selected. OE, CE, BHE, and/or BHE = VIL. 16. WE is HIGH for read cycle. 17. Address valid prior to or coincident with CE transition LOW. Document #: 001-06496 Rev. *E Page 8 of 13 [+] Feedback CY7C1041BN Switching Waveforms (continued) Write Cycle No. 1 (CE Controlled)[18, 19] tWC Address tSA CE tSCE tAW tHA tPWE WE tBW BHE, BLE tSD tHD Data I/O Write Cycle No. 2 (BLE or BHE Controlled) tWC Address BHE, BLE tSA tBW tAW tHA tPWE WE tSCE CE tSD tHD Data I/O Notes 18. Data I/O is high impedance if OE or BHE and/or BLE= VIH. 19. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. Document #: 001-06496 Rev. *E Page 9 of 13 [+] Feedback CY7C1041BN Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, OE LOW) tWC Address tSCE CE tAW tHA tSA tPWE WE tBW BHE, BLE tHZWE tSD tHD Data I/O tLZWE Truth Table CE OE WE BLE BHE H X X X X High Z High Z Power down Standby (ISB) L L H L L Data out Data out Read All bits Active (ICC) L L H L H Data out High Z Read Lower bits only Active (ICC) L L H H L High Z Data out Read Upper bits only Active (ICC) L X L L L Data in Data in Write All bits Active (ICC) L X L L H Data in High Z Write Lower bits only Active (ICC) L X L H L High Z Data in Write Upper bits only Active (ICC) L H H X X High Z High Z Selected, Outputs Disabled Active (ICC) Document #: 001-06496 Rev. *E I/O0–I/O7 I/O8–I/O15 Mode Power Page 10 of 13 [+] Feedback CY7C1041BN Ordering Information Cypress offers other versions of this type of product in many different configurations and features. The following table contains only the list of parts that are currently available. For a complete listing of all options, visit the Cypress website at http://www.cypress.com and refer to the product summary page at http://www.cypress.com/products or contact your local sales representative. Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives and distributors. To find the office closest to you, visit us at http://www.cypress.com/go/datasheet/offices. Speed (ns) Ordering Code 15 CY7C1041BNL-15ZXC 20 CY7C1041BN-20ZSXA Package Name 51-85087 Package Type 44-pin TSOP Type II (Pb-free) 44-pin TSOP Type II Operating Range Commercial Automotive-A Ordering Code Definitions CY 7 C 1 04 1 BN L - XX ZX / ZSX X Temperature range: C = Commercial; A = Automotive-A ZX / ZSX = 44-pin TSOP II (Pb-free) Speed: xx = 15 ns / 20 ns Low power 180 nm technology Data width x 16-bits 4-Mbit density Fast Asynchronous SRAM family Technology code: C = CMOS SRAM Company Code: CY = Cypress Document #: 001-06496 Rev. *E Page 11 of 13 [+] Feedback CY7C1041BN Package Diagrams 44-Pin TSOP II (51-85087) 51-85087 *C Acronyms Acronym 51-85087-*A Document Conventions Description Units of Measure BHE Byte high enable BLE Byte low enable ns nano seconds CE Chip enable V Volts CMOS Complementary metal oxide semiconductor µA micro Amperes I/O Input/output mA milli Amperes OE Output enable SRAM Static random access memory mV milli Volts TSOP Thin small outline package WE Write enable Document #: 001-06496 Rev. *E Symbol Unit of Measure mW milli Watts MHz Mega Hertz pF pico Farad °C degree Celcius W Watts Page 12 of 13 [+] Feedback CY7C1041BN Document History Page Document Title: CY7C1041BN 256 K × 16 Static RAM Document Number: 001-06496 Revision ECN Orig. of Change Submission Date ** 424111 NXR See ECN New Data Sheets *A 498575 NXR See ECN Added Automotive-A operating range updated Ordering Information Table *B 2897061 AJU 03/22/10 Removed obsolete parts from ordering information table Updated package diagrams *C 2906679 NXR 04/07/10 Removed inactive part CY7C1041BNL-20VXCT from the ordering information table. *D 3086674 PRAS 11/15/10 Removed inactive parts (CY7C1041BN-15ZXI, CY7C1041BN-15VXI). Added Ordering Code Definition. *E 3232637 PRAS 04/20/2011 Description of Change Fixed unit for Input Load current and Output Leakage current under Electrical Characteristics table from mA to µA. Updated template. Added Units table. Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive Clocks & Buffers cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2006-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 001-06496 Rev. *E Revised May 12, 2011 Page 13 of 13 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback