HD66764 176-channel Common Driver for Color Displays Rev.1.0 September, 2001 Description The HD66764 is a common-driver LSI for systems with color-liquid-crystal dot-matrix graphic displays. It incorporates 176 LCD drive circuits and power-supply circuits. An external capacitor is also needed for the liquid crystal display. This LSI, when used with the HD66763 384-channel segment driver with on-chip RAM, is suitable for color displays of cellular phones to a maximum of 128-by-176 dots. Features • LCD drive circuits 176 outputs • Internal power-supply circuit Step-up circuit: twice to 12 times, positive-polarity inversion Bias setting: 1/2 to 1/13, programmable Contrast adjustment: 128-level programmable volume Dividing resistors: built-in (controls the bias) Setting: serial transfer from the HD66763 segment driver • Low power consumption • Power-supply voltage Vcc = 1.8 to 3.6 V • LCD drive voltage VLCD-VEE = 10 to 44 V (VM standard: ± 5 to ± 2 2 V) • Package TCP and chip HD66764 Type Number Type Number External Appearance HD66764TB0 TCP HCD66764BP Die with Au bump 2 HD66764 HD66764 PAD arrangement No.1 DUMMY62 DUMMY63 DUMMY100 DUMMY101 No.341 No302 No.301 DUMMY61 COM1 COM2 DYMMY1 DUMMY2 DUMMY3 No.2 DUMMY4 No.300 DUMMY5 RESET - Chip size : 10.2mm x 3.3mm - Chip thickness : 550um (typ.) - PAD coordinates : PAD center - Coordinate origin : chip center - Au bump size (PAD number is shown in the bracket) : (1) 80um x 80um DUMMY1(1) to DUMMY13(77) DUMMY54(118), DUMMY61(301) (2) 45um x 80um COM1(300) to COM16(285) COM161(134)to COM176(119) DUMMY14(78) to DUMMY53(117) DUMMY62(302) to DUMMY101(341) (3)35um x 80um COM17(284) to COM88(213) DUMMY55(207) to DUMMY60(212) COM89(206) to COM160(135) - Au bump height : 15um (typ.) CDA CCL COM15 COM16 COM17 COM18 CCS DISPTMG M FLM CL1 DCCLK VSH VSH Vcc Vcc Vcc GND GND GMD VM VM VM VCH VCH VCH VLREF VREG2 VREGH VEE HD66764 VEE COM87 COM88 DUMMY60 DUMMY59 VEE VCL VCL VCL DUMMY6 Y CE- DUMMY56 DUMMY55 COM89 COM90 CE+ DUMMY7 DUMMY8 VLCD X VLCD VLCD VLOUT2 VLOUT2 C23C23+ C22C22+ C21C21+ VCI2 VCI2 VCI2 VLOUT1 VLOUT1 C12C12+ C11C11+ VCI1 Type code VCI1 VCIOUT VCIOUT HD66764 VCIOUT VREG1 VREGL TEST3 TEST2 RESET COM159 COM160 COM161 COM162 DUMMY9 No.76 DUMMY10 No.119 DUMMY11 DUMMY12 COM175 COM176 DUMMY13 DUMMY54 DUMMY53 DUMMY52 No. 78 DUMMY15 DUMMY14 No. 77 No.118 No.117 3 HD66764 HD66764 PAD Coordinate No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 4 pad name DUMMY1 DUMMY2 DUMMY3 DUMMY4 DUMMY5 RESET CDA CCL CCS DISPTMG M FLM CL1 DCCLK VSH VSH VCC VCC VCC GND GND GND VM VM VM VCH VCH VCH VLREF VREG2 VREGH VEE VEE VEE VCL VCL VCL DUMMY6 CECE+ DUMMY7 DUMMY8 VLCD VLCD VLCD VLOUT2 VLOUT2 C23C23+ C22C22+ C21C21+ VCI2 VCI2 VCI2 VLOUT1 VLOUT1 C12C12+ X -4932 -4699 -4598 -4498 -4398 -4194 -4049 -3904 -3759 -3615 -3470 -3325 -3180 -3035 -2824 -2724 -2624 -2524 -2424 -2224 -2124 -2024 -1823 -1723 -1623 -1423 -1323 -1223 -1023 -922 -822 -622 -522 -422 -222 -122 -22 179 279 379 479 579 779 879 979 1180 1280 1380 1480 1580 1680 1780 1880 2081 2181 2281 2381 2481 2581 2681 Y -1476 -1476 -1476 -1476 -1476 -1476 -1476 -1476 -1476 -1476 -1476 -1476 -1476 -1476 -1476 -1476 -1476 -1476 -1476 -1476 -1476 -1476 -1476 -1476 -1476 -1476 -1476 -1476 -1476 -1476 -1476 -1476 -1476 -1476 -1476 -1476 -1476 -1476 -1476 -1476 -1476 -1476 -1476 -1476 -1476 -1476 -1476 -1476 -1476 -1476 -1476 -1476 -1476 -1476 -1476 -1476 -1476 -1476 -1476 -1476 No 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 (Unit : um) pad name C11C11+ VCI1 VCI1 VCIOUT VCIOUT VCIOUT VREG1 VREGL TEST3 TEST2 RESET DUMMY9 DUMMY10 DUMMY11 DUMMY12 DUMMY13 DUMMY14 DUMMY15 DUMMY16 DUMMY17 DUMMY18 DUMMY19 DUMMY20 DUMMY21 DUMMY22 DUMMY23 DUMMY24 DUMMY25 DUMMY26 DUMMY27 DUMMY28 DUMMY29 DUMMY30 DUMMY31 DUMMY32 DUMMY33 DUMMY34 DUMMY35 DUMMY36 DUMMY37 DUMMY38 DUMMY39 DUMMY40 DUMMY41 DUMMY42 DUMMY43 DUMMY44 DUMMY45 DUMMY46 DUMMY47 DUMMY48 DUMMY49 DUMMY50 DUMMY51 DUMMY52 DUMMY53 DUMMY54 COM176 COM175 X 2781 2881 2982 3082 3282 3382 3482 3682 3782 3882 3983 4194 4398 4498 4598 4699 4932 4932 4932 4932 4932 4932 4932 4932 4932 4932 4932 4932 4932 4932 4932 4932 4932 4932 4932 4932 4932 4932 4932 4932 4932 4932 4932 4932 4932 4932 4932 4932 4932 4932 4932 4932 4932 4932 4932 4932 4932 4932 4728 4668 Y -1476 -1476 -1476 -1476 -1476 -1476 -1476 -1476 -1476 -1476 -1476 -1476 -1476 -1476 -1476 -1476 -1476 -1159 -1099 -1039 -979 -919 -859 -798 -738 -678 -618 -558 -498 -438 -378 -318 -257 -197 -137 -77 -17 43 103 163 224 284 344 404 464 524 584 644 705 765 825 885 945 1005 1065 1125 1185 1474 1474 1474 No 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 pad name COM174 COM173 COM172 COM171 COM170 COM169 COM168 COM167 COM166 COM165 COM164 COM163 COM162 COM161 COM160 COM159 COM158 COM157 COM156 COM155 COM154 COM153 COM152 COM151 COM150 COM149 COM148 COM147 COM146 COM145 COM144 COM143 COM142 COM141 COM140 COM139 COM138 COM137 COM136 COM135 COM134 COM133 COM132 COM131 COM130 COM129 COM128 COM127 COM126 COM125 COM124 COM123 COM122 COM121 COM120 COM119 COM118 COM117 COM116 COM115 X 4608 4547 4487 4427 4367 4307 4247 4187 4127 4067 4006 3946 3886 3826 3766 3716 3666 3616 3565 3515 3465 3415 3365 3315 3265 3215 3164 3114 3064 3014 2964 2914 2864 2814 2763 2713 2663 2613 2563 2513 2463 2413 2362 2312 2262 2212 2162 2112 2062 2012 1962 1911 1861 1811 1761 1711 1661 1611 1561 1510 Y 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 HD66764 HD66764 PAD Coordinate (Continue) No 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 pad name COM114 COM113 COM112 COM111 COM110 COM109 COM108 COM107 COM106 COM105 COM104 COM103 COM102 COM101 COM100 COM99 COM98 COM97 COM96 COM95 COM94 COM93 COM92 COM91 COM90 COM89 DUMMY55 DUMMY56 DUMMY57 DUMMY58 DUMMY59 DUMMY60 COM88 COM87 COM86 COM85 COM84 COM83 COM82 COM81 COM80 COM79 COM78 COM77 COM76 COM75 COM74 COM73 COM72 COM71 COM70 COM69 COM68 COM67 COM66 COM65 COM64 COM63 COM62 COM61 X 1460 1410 1360 1310 1260 1210 1160 1109 1059 1009 959 909 859 809 759 708 658 608 558 508 458 408 358 307 257 207 125 75 25 -25 -75 -125 -205 -255 -305 -355 -405 -455 -506 -556 -606 -656 -706 -756 -806 -856 -907 -957 -1007 -1057 -1107 -1157 -1207 -1257 -1308 -1358 -1408 -1458 -1508 -1558 Y 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 No 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 pad name COM60 COM59 COM58 COM57 COM56 COM55 COM54 COM53 COM52 COM51 COM50 COM49 COM48 COM47 COM46 COM45 COM44 COM43 COM42 COM41 COM40 COM39 COM38 COM37 COM36 COM35 COM34 COM33 COM32 COM31 COM30 COM29 COM28 COM27 COM26 COM25 COM24 COM23 COM22 COM21 COM20 COM19 COM18 COM17 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 (Unit : um) X -1608 -1658 -1709 -1759 -1809 -1859 -1909 -1959 -2009 -2059 -2110 -2160 -2210 -2260 -2310 -2360 -2410 -2460 -2510 -2561 -2611 -2661 -2711 -2761 -2811 -2861 -2911 -2962 -3012 -3062 -3112 -3162 -3212 -3262 -3312 -3363 -3413 -3463 -3513 -3563 -3613 -3663 -3713 -3764 -3824 -3884 -3944 -4004 -4064 -4124 -4184 -4245 -4305 -4365 -4425 -4485 -4545 -4605 -4665 -4725 Y 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 No 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 pad name DUMMY61 DUMMY62 DUMMY63 DUMMY64 DUMMY65 DUMMY66 DUMMY67 DUMMY68 DUMMY69 DUMMY70 DUMMY71 DUMMY72 DUMMY73 DUMMY74 DUMMY75 DUMMY76 DUMMY77 DUMMY78 DUMMY79 DUMMY80 DUMMY81 DUMMY82 DUMMY83 DUMMY84 DUMMY85 DUMMY86 DUMMY87 DUMMY88 DUMMY89 DUMMY90 DUMMY91 DUMMY92 DUMMY93 DUMMY94 DUMMY95 DUMMY96 DUMMY97 DUMMY98 DUMMY99 DUMMY100 DUMMY101 X -4932 -4932 -4932 -4932 -4932 -4932 -4932 -4932 -4932 -4932 -4932 -4932 -4932 -4932 -4932 -4932 -4932 -4932 -4932 -4932 -4932 -4932 -4932 -4932 -4932 -4932 -4932 -4932 -4932 -4932 -4932 -4932 -4932 -4932 -4932 -4932 -4932 -4932 -4932 -4932 -4932 Y 1474 1185 1125 1065 1005 945 885 825 765 705 644 584 524 464 404 344 284 224 163 103 43 -17 -77 -137 -197 -257 -318 -378 -438 -498 -558 -618 -678 -738 -798 -859 -919 -979 -1039 -1099 -1159 5 HD66764 Pin Functions Table 1 Pin Functions Signal Name Quantity Input/ Output Connected to Function Vcc 1 - Power supply GND 1 - Power supply VCC-GND: Logic-circuit power supply. Supply the same voltage as for the HD66763. VLCD 1 - Power supply or VLOUT2 LCD-drive-circuit power supply, positive side. VEE 1 - Power supply or VCL LCD-drive-circuit power supply, negative side. VciOUT 1 - Vci1 and capacitor for stabilization or open Outputs a regulated voltage derived from Vcc. Connect a capacitor for stabilization. When this pin is not used, leave it open. Vci1 1 - VciOUT or power supply Voltage-input pin for step-up circuit 1. When the Vci adjuster is used, input the power supply from VciOUT. When not used, input the external power supply. Vci2 1 - VLOUT1 or power supply Voltage-input pin in step-up circuit 2. When the internal step-up circuit is not used, leave this pin open. VCH 4 Capacitor for stabilization and VSH of HD66763 or external power supply When the internal power supply circuit is used, the LCD-drive-level power supply is output here. VCH, VM, and VCL are used for the common driver, and VSH for the segment driver. Connect a capacitor for stabilization of the display quality. - VSH VM VCL When the internal power-supply circuit is not used, connect the output of the external powersupply circuit. However, VSH need not be supplied. VLOUT1 1 - Step-up capacitance/ Vci2 pin A voltage that doubles or triples the voltage between Vci1 and GND is output here. The step-up factor can be set in an internal register. VLOUT2 1 - Step-up capacitance/ VLCD pin A voltage that is boosted from the voltage between Vci1/Vci2 and GND is output here. The step-up factor can be set in an internal register. C11+, C11- to C23+, C23- 10 - Step-up capacitance or open Connect a step-up capacitor according to the step-up factor. When the internal step-up circuit is not used, leave this pin open. CE+, CE- 2 - Step-up capacitance or open Connect a step-up capacitor for generating the VCL level from the VCH and VM levels. When the internal step-up circuit is not used, leave this pin open. 6 HD66764 Table 1 Pin Functions (cont) Signal Name Quantity Input/ Output VREGL 1 VREG1 Connected to Function - External reference voltage Reference voltage input. Connect an external reference voltage. Input current is not supplied from this pin. Therefore, External voltage can be generated by regulator which uses divided resistor. 1 - VREGH A voltage that doubles, triples, quadruples, or quintuples the voltage on VREGL is output here. VREGH 1 - VREG1 Connects the output of VREG1. VREG2 1 - VLREF or open A voltage that doubles, triples, quadruples, or quintuples the voltage on VREGH is output here. VLREF 1 - VREG2 or external power supply Input for the LCD drive voltage. When the internal amplification circuit is used, the output of VREG2 is connected here. When the circuit is not used, supply external power. RESET1*/ RESET2* 2 Input External reset circuit Reset pin. When a low level is input here, the LSI is reinitialized. Be sure to apply a signal to this pin during the system’s power-on reset. RESET1* and RESET2* are equivalent. So apply a signal to either pin as required and leave the other pin open. CL1 1 Input CL1 of HD66763 Clock input pin. The output of the LCD changes on the falling edge of this signal. FLM 1 Input FLM of HD66763 Frame-synchronization with the segment driver. M 1 Input M of HD66763 Inputs the current-alternating signal from the LCD output. When output is selected, the following levels are output: Low: VCL, high: VCH When output is not selected, VM is output. DISPTIMG 1 Input DISPTMG of HD66763 A display timing signal. DISPTMG = 1: display, DISPTMG = 0: nondisplay DCCLK 1 Input DCCLK of HD66763 A clock for the step-up circuit that is supplied from HD66763. CCL 1 Input CCL of HD66763 Operates as a clock for the transfer of register settings. Latches data on the rising edge of the clock. CDA 1 Input CDA of HD66763 Operates as the data for the transfer of register settings. CCS* 1 Input CCS* of HD66763 A chip-select signal. Low: selected (data-transfer enabled), high: not selected (data-transfer disabled) 7 HD66764 Table 1 Pin Functions (cont) Signal Name Quantity Input/ Output Connected to Function COM1 to COM176 176 Output Liquid crystal Signals to drive the common lines. Output either of VCL, VCH, or VM levels. When selected, VCH or VCL is output. When not selected, VM is output. When the display is off, the GND level is output. TEST2, TEST3 2 Output Open Test pins. Leave these pins open. 8 HD66764 Internal Block Diagram COM1 to COM176 LCD drive circuit 176 Level shifter 176 Scan data generation circuit VSH VCH VM VCL VLREF VREG1 VREGH VREG2 VEE VLCD CE- CE+ VLOUT2 C21- to C23- Vci2 C21+ to C23+ VLOUT1 C11+ to C12+ C11- to C12- Vci1 DCCLK VREGL LCD drive-level generation circuit Step-up circuit VciOUT CCS* CCL CDA M CL1 DISPTMG FLM RESET* Serial interface /register Figure 1 Block Diagram 1. Step-up circuit Boosts the Vci1 voltage by from two to 12 times. The required voltage is generated by combining double or triple step-up and double, triple, or quadruple step-up. The factor is controlled by register settings. A negative-polarity voltage is also generated. For details, refer to the section on the LCD Voltage Generation Circuit. 2. LCD-drive-level generation circuit Generates the VCH, VSH, VM, or VCL levels required to drive the LCDs. The VSH level is supplied to the HD66763. 3. Interface circuit Transfers the data to the internal control register. 4. Scan data generation circuit Produces the output signals for the common lines at logic levels, as selected and in the selected direction, in synchronization with the FLM signal. 9 HD66764 5. Level shifter Shifts the level from Vcc-GND power supply for operation of the logic circuits to VLCD-VEE for the LCD drive circuit. 6. LCD drive circuit Outputs one of VCH, VM, or VCL according to the combination of data and the M signal from the scan data generation circuit. 10 HD66764 Instructions Outline The HD66764 has seven internal registers. The data is written to these registers by using a common serial data interface. This interface can be directly connected with the HD66763 segment driver for the automatic transfer of instructions. When an instruction is written to the HD66763 via the bus from the CPU, it is output from the serial interface of the HD66763, and the HD66764 receives the instruction to make a setting in one of its internal registers. In the bit configuration for the transfer of instructions, the upper three bits are index numbers that indicate the target register of the transfer, and the lower 13 bits are the data. Detailed Description Power Control 1 D15 0 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 BS2 BS1 BS0 BT3 BT2 BT1 BT0 DC2 DC1 DC0 AP1 AP0 SLP Index code Figure 2 Power Control 1 Instruction BS2-0: Set the LCD drive bias within the range from 1/2 to 1/13. Set the bias according to the LCD drive duty cycle and LCD drive voltage. BT3-0: Control the step-up factor of the step-up circuit. Adjust the step-up factor according to the LCD drive duty and power-supply voltage to be used. Set the output of VLOUT1 to 5.5 V or lower. DC2-0: Set the step-up cycle of the step-up circuit. When the cycle is accelerated, the driving ability of the step-up circuit becomes high, but its current consumption is increased, too. Adjust the cycle with consideration of the display quality and the current consumption. AP1-0: Adjust the amount of fixed current from the fixed current source in the operational amplifier circuit for the LCD drive-level power. When the amount of fixed current becomes large, the LCD driving ability and the quality of the display become high, but the current consumption is increased. Adjust the fixed current with consideration of the display quality and the current consumption. During times when there is no display, such as in the sleep or standby modes, AP1-0 can be set to (0, 0) and the current consumption is reduced by shutting the operational amplifier down. SLP: Sets the sleep mode. When SLP = 1, bits AP1/0 and DISP in the first-screen driving-control register are all fixed to 0. This stops the operation of the power-supply circuit and turns off the display at the same time. The state of SLP bit does not change the values of these bits. 11 HD66764 Table 2 BS Bits and LCD Drive Bias Value BS2 BS1 BS0 LCD Drive Bias Value 0 0 0 1/13 bias 0 0 1 1/12 bias 0 1 0 1/11 bias 0 1 1 1/10 bias 1 0 0 1/9 bias 1 0 1 1/8 bias 1 1 0 1/4 bias 1 1 1 1/2 bias Table 3 BT Bits and VLOUT1 and VLOUT2 Outputs BT3 BT2 BT1 BT0 VLOUT1 Output VLOUT2 Output 0 0 0 0 2 x Vci1 2 x Vci2 0 0 0 1 3 x Vci1 2 x Vci2 0 0 1 0 2 x Vci1 3 x Vci2 0 0 1 1 3 x Vci1 3 x Vci2 0 1 0 0 2 x Vci1 4 x Vci2 0 1 0 1 3 x Vci1 4 x Vci2 0 1 1 0 2 x Vci1 Step-up stopped 0 1 1 1 3 x Vci1 Step-up stopped 1 0 0 0 2 x Vci1 Vci1 + Vci2 1 0 0 1 3 x Vci1 Vci1 + Vci2 1 0 1 0 2 x Vci1 Vci1 + 2 x Vci2 1 0 1 1 3 x Vci1 Vci1 + 2 x Vci2 1 1 0 0 2 x Vci1 Vci1 + 3 x Vci2 1 1 0 1 3 x Vci1 Vci1 + 3 x Vci2 1 1 1 0 2 x Vci1 Vci2 1 1 1 1 3 x Vci1 Vci2 12 HD66764 Table 4 DC Bits and Step-up Cycle DC2 DC1 DC0 Step-up Cycle in Step-up Circuit 1 Step-up Cycle in Step-up Circuit 2/3 0 0 0 DCCLK DCCLK 0 0 1 DCCLK divided by two DCCLK 0 1 0 DCCLK DCCLK divided by two 0 1 1 DCCLK divided by two DCCLK divided by two 1 0 0 DCCLK DCCLK divided by three 1 0 1 DCCLK divided by two DCCLK divided by three 1 1 0 DCCLK DCCLK divided by four 1 1 1 DCCLK divided by two DCCLK divided by four Table 5 AP Bits and Amount of Current in Operational Amplifier AP1 AP0 Amount of Current in Operational Amplifier 0 0 Operation of the operational amplifier and step-up circuit are stopped. 0 1 Small 1 0 Medium 1 1 Large Power Control 2 D15 0 D14 0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 0 0 0 0 0 0 0 0 VC2 VC1 VC0 Index code Figure 3 Power Control 2 Instruction VC2-0: Adjust the VciOUT voltage to fraction of Vcc. The voltage of VLOUT1 can be controlled when VciOUT is connected to Vci1. When VC2 = 1, the Vci1 amplifier operation is stopped, and any voltage can be externally applied to the Vci1 pin. Table 6 VC Bits and Vci Adjustment Reduction Factor VC2 VC1 VC0 Adjusted Vci Magnification Factor 0 0 0 0.92 x Vcc 0 0 1 0.83 x Vcc 0 1 0 0.76 x Vcc 0 1 1 0.68 x Vcc 1 * * No amplification of Vci1 (external input to Vci1). 13 HD66764 Contrast Adjustment D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 0 VR3 VR2 VR1 VR0 0 CT6 CT5 CT4 CT3 CT2 CT1 CT0 Index code Figure 4 Contrast Adjustment Instruction CT6-0: Control the LCD drive voltage to adjust contrast to one of 128 steps. VR3-0: Amplifies the output voltage (VREG2) in the LCD-drive reference-voltage generator to from four to 25 times the voltage on VREGL. The value of VREG1 must not exceed 5.5 V. Table 7 CT Bits and Contrast Value to be Set to CT Bits CT6 CT5 CT4 CT3 CT2 CT1 CT0 Contrast 0 0 0 0 0 0 0 3.84R (minimum) 0 0 0 0 0 0 1 3.81R 0 0 0 0 0 1 0 3.78R 0 0 0 0 0 1 1 3.75R 0 0 0 0 1 0 0 3.72R : : : : : : : 1 1 1 1 1 1 0 0.06R (maximum) 1 1 1 1 1 1 1 0.03R (maximum) 14 : HD66764 Table 8 VR Bits and VREG and VLREF Voltages VR3 VR2 VR1 VR0 VREG1 Voltage VREG2 Voltage VLREF Voltage 0 0 0 0 VREGL x 2 VREGH x 2 VREGL x 4 0 0 0 1 VREGL x 3 VREGH x 2 VREGL x 6 0 0 1 0 VREGL x 4 VREGH x 2 VREGL x 8 0 0 1 1 VREGL x 5 VREGH x 2 VREGL x 10 0 1 0 0 VREGL x 2 VREGH x 3 VREGL x 6 0 1 0 1 VREGL x 3 VREGH x 3 VREGL x 9 0 1 1 0 VREGL x 4 VREGH x 3 VREGL x 12 0 1 1 1 VREGL x 5 VREGH x 3 VREGL x 15 1 0 0 0 VREGL x 2 VREGH x 4 VREGL x 8 1 0 0 1 VREGL x 3 VREGH x 4 VREGL x 12 1 0 1 0 VREGL x 4 VREGH x 4 VREGL x 16 1 0 1 1 VREGL x 5 VREGH x 4 VREGL x 20 1 1 0 0 VREGL x 2 VREGH x 5 VREGL x 10 1 1 0 1 VREGL x 3 VREGH x 5 VREGL x 15 1 1 1 0 VREGL x 4 VREGH x 5 VREGL x 20 1 1 1 1 VREGL x 5 VREGH x 5 VREGL x 25 15 HD66764 1st Screen Driving Position 2nd Screen Driving Position D15 D14 D13 D12 D11 D10 D9 D8 0 1 1 0 0 1 0 0 0 0 0 0 0 SE17 SE16 SE15 SE14 SE13 SE12 SE11 SE10 1 0 1 0 0 0 0 0 SS27 SS27 SS25 SS24 SS23 SS22 SS21 SS20 1 1 0 0 0 0 0 0 SE27 SE26 SE25 SE24 SE23 SE22 SE21 SE20 DISP CMS SPT D7 D6 D5 D4 D3 D2 D1 D0 SS17 SS16 SS15 SS14 SS13 SS12 SS11 SS10 Index code Figure 5 1st and 2nd Screen Driving Position Instruction DISP: Controls the display operation. When DISP = 0, the GND level is output from all common outputs. When the GND level is output, the segment output can turn the display off. When DISP = 1, the display operates. CMS: Selects the scan direction for output of the common driver. When CMS = 0, a direction is from COM1 to COM176, and, when CMS = 1, it is from COM176 to COM1. SPT: When SPT = 1, driving is in two-screen division mode. For details, refer to the section on the Screen-division Driving Function of the HD66763. SS17-10: Specify the start position of driving for the first screen, in units of raster rows. The common driver is provided to LCDs from the value set here plus one. SE17-10: Specify the end position of driving for the first screen, in units of raster rows. The common driver is provided to LCDs up to the value set here plus one. SS27-20: Specify the start position of driving for the second screen, in units of raster rows. The common driver is provided to LCDs from the value set here plus one. SE27-20: Specify the end position of driving for the second screen, in units of raster rows. The common driver is provided to LCDs up to the value set here plus one. 16 HD66764 Common Serial Transfer Register settings are transferred from the HD66763. The interface is made up of the common chip select (CCS*), transfer clock (CCL), and data input (CDA) lines. Data transfer starts when the falling edge of the CCS* line indicates that data is to be transferred. Transfer is ended when the rising edge of the CCS* line indicates that the transfer is over. Bits are transferred in 16-bit units, and the data is transferred in order from MSB to LSB. Transfer start Transfer end CCS* CCL CDA IX2 IX1 IX0 D12 D11 D10 D9 Index code D8 D7 D6 D5 D4 D3 D2 D1 D0 Instruction data Figure 6 Format for Data Transfer 17 HD66764 Interface with LCD Panel Setting the CMS bit can change the direction of the common signal. The LCD panel and HD66764 can be connected in several ways. When CMS = 0, scanning is in order from COM1 to COM176, and, CMS = 1, it is from COM176 to COM1. When the placement of the screen is adjusted, the display on the LCD grid be made to run from any horizontal or vertical position, in either direction. COM1 COM2 Scan direction HD66764 LCD COM176 COM175 Scan direction HD66764 LCD COM175 COM176 COM2 COM1 a) CMS = "0" b) CMS = "1" Figure 7 Interface between HD66764 and LCD Panel 18 HD66764 Table 9 Common Output to be Used Display Duty Cycle CMS = 0 CMS = 1 1/16 COM1 to COM16 COM176 to COM160 1/24 COM1 to COM24 COM176 to COM152 1/32 COM1 to COM32 COM176 to COM144 1/40 COM1 to COM40 COM176 to COM136 1/48 COM1 to COM48 COM176 to COM128 1/56 COM1 to COM56 COM176 to COM120 1/64 COM1 to COM64 COM176 to COM112 1/72 COM1 to COM72 COM176 to COM104 1/80 COM1 to COM80 COM176 to COM96 1/88 COM1 to COM88 COM176 to COM88 1/96 COM1 to COM96 COM176 to COM80 1/104 COM1 to COM104 COM176 to COM72 1/112 COM1 to COM112 COM176 to COM64 1/120 COM1 to COM120 COM176 to COM56 1/128 COM1 to COM128 COM176 to COM48 1/136 COM1 to COM136 COM176 to COM40 1/144 COM1 to COM144 COM176 to COM32 1/152 COM1 to COM152 COM176 to COM24 1/160 COM1 to COM160 COM176 to COM16 1/168 COM1 to COM168 COM176 to COM8 1/176 COM1 to COM176 COM176 to COM1 Note: The above values apply when SS17 to SS10 = H’00. 19 HD66764 Example of System Configuration Figure 8 shows an LCD panel with 128 (horizontal)-by-176 (vertical) dots, configured by using the HD66763 segment driver with built-in display memory. Only two chips are needed to drive the LCD display. 128 pixels 3 COM1 COM2 SEG1 SEG2 SEG383 SEG384 COM175 COM176 FLM, CL1, M, DISPTMG, CL1,FLM,M 5 DCCLK DISPTMG, DCCLK CCS*, CDA, CCL HD66763 VSH 16 4 DB0 to DB15 CS*, WR*, RD*, RS Figure 8 System Configuration 20 176 HD66764 LCD HD66764 Example of Connection with HD66763 Figure 9 shows an example of connection with the HD66763 segment driver. HD66764 HD66763 VREGL VREG1 VREGH VREG2 VLREF VLOUT2 Vref VLCD VEE VCH VCL VSH VM VSH VSL DISPTMG CL1 FLM M DCCLK CCS* CCL CDA DISPTMG CL1 FLM M DCCLK CCS* CCL CDA Figure 9 Example of Connection with HD66763 21 HD66764 LCD Voltage Generation Circuit Figure 10 shows a configuration of the HD66764 LCD drive voltage generation circuit. It consists of step-up circuit 1 that doubles or triples the voltage that is applied to Vci, step-up circuit 2 that multiplies the voltage from step-up circuit 1 by one to four times, and step-up circuit 3 that generates a VCL level by inverting the VCH level centered around the VM level. These circuits generate VLCD and VCL that are required to drive the LCDs. When the voltage input to VREGL is amplified in amplification circuit 1 or 2, the level (VCH, VSH, or VM) that drives the LCD is generated by resistance division according to VLREF. Since the input current for VREGL hardly flows, VREGL can be generated by high-resistance division to lower the power consumption. Connect VSH to HD66763. 22 HD66764 Vcc VREGL LCD driver VREGH Amplification circuit 2 0.1 F VCH VSH + Bias adjustment + VREG1 + Amplification circuit 1 Contrast adjustment VM VSH To segment driver VREG2 VLREF 0.1 F Vcc VciOUT Regulator VEE VCL Vci1 C11CE- C11+ C12- Polarity inversion circuit Step-up circuit 1 C12+ CE+ VLOUT1 VCI2 HD66764 C21C21+ Vcc C22C22+ Step-up circuit 2 GND C23C23+ VLOUT2 VLCD Note 1. Unmarked capacitors are 1 F (B-characteristics). 2. Schottky barrier diode needs to be put between VCL and GND. (VF = 0.4V/20mA, VR 30V) Figure 10 Configuration of Internal Power Circuit 23 HD66764 Notes: 1. Generate an output voltage (VLOUT1) from step-up circuit 1 within the range from 4.5 to 6.0 V. 2. Do not allow the output voltage (VLOUT2) from step-up circuit 2 to exceed 22 V. 3. Generate an output voltage (VREG1) from amplification circuit 1 within the range from 4.5 to 6.0 V. 4. Generate an output voltage (VREG2) from amplification circuit 2 that is lower than VLCD. 5. When a capacitor with polarity is used, be sure that an inverted voltage is not applied to it in any state of the system. 6. Vci1/Vci2 is used as both the reference voltage input and power supply in the step-up circuit. Keep sufficient LCD drive current. 7. The rated voltage of the capacitors are as follows. When actual voltage is less than 16V, 16V rated voltage capacitors can be used. 6.3V : VREG1, VciOUT, C11, C12, VLOUT1, C21, C22, C23, VSH, VM 25V(16V) : VREG2, VLOUT2, VCH, CE, VCL LCD Drive Voltage The required voltage can be calculated by applying the following expressions. Drive voltages are standard; generate a voltage to suit the panel to be used. VSH - VM, VM - VSL = VCH - VM, VM - VCL = 1 2 2 N 1 2 2N N Vth N-1 Vth: Threshold voltage of the LCD panel to be used. N: Display duty cycle. Vth N-1 LCD Drive Bias An optimal bias can be calculated by applying the following expression. The value that has been calculated is theoretically optimal. If a lower bias value than the optimal value is used to drive the LCD, contrast may be reduced depending on lighting conditions. However, the power consumption can be reduced by lowering the drive voltage. Adjust the value according to the system to be used. Bias value = 1 N 24 HD66764 VLREF Rc VCH Rb VSH Rb: Resistor for bias adjustment (R to 12R) Rc: Resistor for contrast adjustment (0.03R to 3.84R) R VM R Figure 11 Rb and Rc Resistors Table 10 BS Bits, LCD Drive Bias Value, and Rb Resistor Value BS2 BS1 BS0 LCD Drive Bias Value Rb Resistor Value 0 0 0 1/13 bias 12R 0 0 1 1/12 bias 11R 0 1 0 1/11 bias 10R 0 1 1 1/10 bias 9R 1 0 0 1/9 bias 8R 1 0 1 1/8 bias 7R 1 1 0 1/4 bias 3R 1 1 1 1/2 bias R 25 HD66764 Power-on/off Sequence To prevent pulse lighting of LCD screens at power-on/off, the power-on/off sequence is activated as shown below. However, since the sequence depends on LCD materials to be used, confirm the conditions by using your own system. Power-on Sequence Turn on the power voltages Wait for 1ms or longer (power-on time) Wait for 10 ms or longer (oscillation stabilization time) Power Control 1 setting (BS2-0, BT2-0, DC2-0, AP1-0) Power Control 2 setting (VC2-0) Contrast Control setting (VR3-0, CT6-0) Wait for 150 ms * or longer Turn on display : D1 = "1" Note : Power supply stabilization time. It depends on step-up ratio, capacitance for the step-up circuit. Figure 12 Power-on Sequence Power-off Sequence Turn off the display : D1 = "0" Turn off power supply circuit (AP1-0 = "00") Wait for 1 ms Power off Figure 13 26 Power-off Sequence HD66764 Setting flow for the power circuit of HD66764 Set Vci voltage (R0Ch) Transfer COM driver data (R0Ah) Set VR and CT bits (R04h) Transfer COM driver data (R0Ah) Set BS, BT, DC, AP bits. Step-up circuit must be three times (R03h) Transfer COM driver data (R0Ah) Wait 100ms *1 Set BS, BT, DC, AP bits. Step-up circuit must be four times (R03h) Transfer COM driver data (R0Ah) Wait 100ms *1 It is not nec essary when setpu p factor is three Wait until the power circuit becomes stable. It varies according to step-up factor, the value of step-up and stabilized condenser. Evaluate this period on yoursystem. These register numbers are that of HD66763 or HD66765. P o w er-o n res et 1m s Vcc R E S ET * 27 HD66764 Example of register setting on power supply Examples of register setting values on power supply are described below. Example 1 : 1/160 duty ratio, Vcc = 3.0V, VLCD = 18V BS2-0 = H'0 : bias adjustment 1/12 BT3-0 = H'4 : step-up circuit 1 2 times, step-up circuit 2 4 times DC2-0 = H'6 : step-up circuit 1 frequency DCCLK, step-up circuit 2 frequency DCCLK/4 AP1-0 = H'1 : low fixed current in the amplifier VC2-0 = H'0 : Vci1 = 0.92 x Vcc = 2.75V VR3-0 = H'A : VREG1 = 3 x VREGL, VREG2 = 5 x VREGH = 15 x VREGL = 18V VREGL = 1.2V CT6-0 : appropriate contrast setting values D1 = H'1 : Dispaly on CMS = H'0 : Scan direction from COM1 to COM160 SPT = H'0 : No screen-division SS17 = H'00 SE17 = H'9F : Display area from COM1 to COM160 Example 2 : 1/160 duty ratio, Vcc = 2.4V, Vci = 2.8V, VLCD = 18V BS2-0 = H'0 : bias adjustment 1/12 BT3-0 = H'4 : step-up circuit 1 2 times, step-up circuit 2 4 times DC2-0 = H'6 : step-up circuit 1 frequency DCCLK, step-up circuit 2 frequency DCCLK/4 AP1-0 = H'1 : low fixed current in the amplifier VC2-0 = H'4 : Vci regulator is off. Input external voltage to Vci VR3-0 = H'A : VREG1 = 3 x VREGL, VREG2 = 5 x VREGH = 15 x VREGL = 18V VREGL = 1.2V CT6-0 : appropriate contrast setting values D1= H'1 : Dispaly on CMS = H'0 : Scan direction from COM1 to COM160 SPT = H'0 : No screen-division SS17 = H'00 SE17 = H'9F : Display area from COM1 to COM160 Example 3 : Partial display, 1/24 duty ratio, Vcc = 2.4V, Vci = 2.8V, VLCD = 7V BS2-0 = H'0 : bias adjustment 1/4 BT3-0 = H'0 : step-up circuit 1 2 times, step-up circuit 2 1.5 times DC2-0 = H'6 : step-up circuit 1 frequency 2 x DCCLK, step-up circuit 2 frequency DCCLK/4 AP1-0 = H'1 : low fixed current in the amplifier VC2-0 = H'4 : Vci regulator is off. VR3-0 = H'2 : VREG1 = 3 x VREGL, VREG2 = 2 x VREGH = 6 x VREGL = 7.2V VREGL = 1.2V CT6-0 : appropriate contrast setting values D1= H'1 : Dispaly on CMS = H'0 : Scan direction from COM1 to COM24 SPT = H'0 : No screen-division SS17= H'00 SE17= H'17 : Display area from COM1 to COM24 28 HD66764 HD66764 power supply level correlation VLC D V LO U T2 ( +7 ～+23V ) VR EG 2( <VLO U T2) V LR EF CT6-0: C ontrast control VC H BT2-1 2 to 4 tim es V R3-2: 2 to 5 tim es B S2-0: B ias control V C2-0: 68 to 92% V LO U T1 (4.5 ～6.0V ) V R EG 1(<VLO U T1) Vcc V ci1 VR EG L(<VLO U T1) GND V ci2 B T0: 2 to 3 tim es VR EFH V R1-0: 2 to 5 tim es VS H VM V oltage poality inversion betw een V C H and V M VCL 29 HD66764 Reset Function The HD66764 is internally initialized by RESET input GND level. Instructions are not issued during the reset period. After power on, the reset must be held. Instruction Set Initialization: a. b. c. d. e. Power control 1 (BS2-0 = 000, BT3-0 = 0000, DC2–0 = 000, AP1–0 = 00, SLP = 0,) Power control 2 (VC2-0 = 000) Contrast adjustment (VR3-0 = 0000, CT6–0 = 0000000) 1st screen division (D1 = 0, CMS = 0, SPT = 0, SE17-10 = 11111111, SS17-10 = 00000000) 2nd screen division (SE27-20 = 11111111, SS27-20 = 00000000) Output Pin Initialization: LCD driver output pins (COM): Output GND level 30 HD66764 Absolute Maximum Ratings Item Symbol Ratings Unit Notes Logic circuit Vcc -0.3 to +7.0 V 1 LCD drive circuit VLCD-VEE -0.3 to +46 V Input voltage VT1 -0.3 to Vcc + 0.3 V Operating temperature topr -40 to +85 °C Storage temperature Tstg -55 to +110 °C Power supply voltage 1, 2 Notes: 1. Voltage from GND. 2. Applies to the CL1, FLM, M, CCS*, CDA, CCL, and VREGL pins. Note: If the LSI is used beyond the above maximum ratings, it may be permanently damaged. It should always be used within its specified operating range for normal operation to prevent malfunction or degraded reliability. 31 HD66764 Electrical Characteristics DC Characteristics (VCC = 1.8 to 3.6 V, VLCD–VEE = 10 to 44 V, GND = 0 V, Ta = -40 to +85 C)*1 Item Symbol Input high voltage VIH Input low voltage VIL Driver ON resistance RON VREG OUT voltage range Test Condition min. typ. max. Unit Notes 0.8× Vcc 0 - Vcc V 2 - 0.2× Vcc V 2 VLCD-VEE = 40 V, Iload ± 100 µA - 1.5 3.0 kΩ 3 VREG VREGH=VREG1 -3.0 0 3.0 % Input leakage current IIL Vin=0 to VCC -2.5 - 2.5 µA 2 Stanby voltage Istb Vcc=3.0V - 0.1 5 µA 5 Consumption voltage Iop 1/176 duty, frame frequency : 60 Hz, Vcc = 3 V, - 250 450 µA 6 4 Notes: 1. For bare die and wafer products, guaranteed at 85°C. 2. Applies to the CL1, FLM, M, DISPTMG, CCS*, CCL, and CDA input pins. 3. Resistor value between the COM and V (VCH, VM, or VCL) pins when a load current flows on one pin of COM1 to COM176. This is specified under the following conditions: VCH = +21.5 V, VCL = -18.5 V, VM = (VCH+VCL)/2, Iload = ±100 µA The COM1 to COM176 pins other than the pin to be measured should be disconnected. 4. Applies to range of VREG2 OUT expectation value in the following conditions. Amplification circuit 1 : 4 times , Amplification circuit 2 : 4 times 5.Specified the following conditions for Vcc,Vci 1 pins. (1) CL1 = fixed GND , AP1-0 = (00) (2) CL1 = fixed GND , SLP = 0 6.Specified the following conditions for consumption voltage. VC2 - 0=(000) (Vci OUT= 0.92×Vcc) , step-up eight times (step-up circuit 1 : 2 times, step-up circuit 2 : 4 times) CT6 - 0 =(100 0000), VR3 - 0=(1010), AP1 - 0=(01) Vci out=Vci1,VLOUT1=Vci2,VLOUT2=VLCD,VREG2=VLREF,VREG1=VREGH, VREGL=1.1V 32 HD66764 AC Characteristics (VCC = 1.8 to 3.6 V, VLCD-VEE = 10 to 44 V) LCD control signal Timing Item Symbol Pin min. typ. max. Unit CL1 high-level width tCWH CL1 4.0 - - µs CL1 low-level width tCWL CL1 4.0 - - µs CL1 cycle time tCYC CL1 10 - 200 µs CL1 rise time tr CL1 - - 100 ns CL1 fall time tf CL1 - - 100 ns FLM setup time tFS FLM, CL1 3.0 - - µs FLM hold time tFH FLM, CL1 3.0 - - µs Notes t CYC t CWH CL1 t CWL tr tf 0.8 Vcc 0.2Vcc 0.2 Vcc t FS t FH 0.8 Vcc FLM Figure 14 LCD control signal Timing 33 HD66764 Common Serial Timing Item Symbol Pin min. typ. max. Unit CCL high-level width tCLWH CCL 1.0 - - µs CCL low-level width tCLWL CCL 1.0 - - µs CCL cycle time tCYCC CCL 2.5 - 10 µs CCL rise time tr CCL - - 100 ns CCL fall time tf CCL - - 100 ns CDA setup time tCDS CDA, CCL 0.5 - - µs CDA hold time tCDH CDA, CCL 0.5 - - µs CCS* setup time tCSS CCS*, CCL 2.0 - - µs CCS* hold time tCSH CCS*, CCL 2.0 - - µs CCS* 0.2 Vcc tCSS t CSH t CYCC t CLWH t CLWL tr tf 0.2 Vcc CCL 0.8 Vcc t CDS t CDH 0.8 Vcc CDA 0.2 Vcc Figure 14 34 Common Serial Timing Notes HD66764 Reference Data 1) Step-up Circuit 1 -0.4 Drop Voltage(V) Measurement condition Step-up factor :Twice DCCLK :13.09kHz Step-up cycle : DCCLK Temperature :25℃ Vci1 :3.0V 0.0 -0.2 -0.6 -0.8 -1.0 -1.2 -1.4 -1.6 -1.8 -2.0 0 100 200 300 400 500 600 700 800 900 1000 1100 1200 Iload(uA) 2) Polarity inversion circuit -0.4 Drop Voltage (V) Measurement condition DCCLK :13.09kHz Step-up cycle : DCCLK/ 4 Temperature :25℃ VCH :16V VM : 0V 0.0 -0.2 -0.6 -0.8 -1.0 -1.2 -1.4 -1.6 -1.8 -2.0 0 20 40 60 80 100 120 140 Iload(uA) 35 HD66764 3) Step-up Circuit 2 0.0 -0.2 -0.4 Drop Voltage(V) a) Measurement condition Step-up factor :Twice DCCLK :13.09kHz Step-up cycle : DCCLK/4 Temperature :25℃ Vci2 :5.0V -0.6 -0.8 -1.0 -1.2 -1.4 -1.6 -1.8 -2.0 0 20 40 60 80 100 120 140 100 120 140 100 120 140 Iload(uA) 0.0 -0.2 -0.4 Drop Voltage(V) b) Measurement condition Step-up factor :3 times DCCLK :13.09kHz Step-up cycle : DCCLK/4 Temperature :25℃ Vci2 :5.0V -0.6 -0.8 -1.0 -1.2 -1.4 -1.6 -1.8 -2.0 0 20 40 60 80 Iload(uA) 0.0 -0.2 -0.4 Drop Voltage(V) b) Measurement condition Step-up factor :4 times DCCLK :13.09kHz Step-up cycle : DCCLK/4 Temperature :25℃ Vci2 :5.0V -0.6 -0.8 -1.0 -1.2 -1.4 -1.6 -1.8 -2.0 0 20 40 60 80 Iload(uA) 36 HD66764 1) Step-up Circuit 1 0.0 -0.2 -0.4 Drop Voltage(V) Measurement condition Step-up factor : Twice DCCLK : 13.09kHz Step-up cycle : DCCLK Temperature : 25℃ Vci1 : 3.0V Iload : 300μA -0.6 -0.8 -1.0 -1.2 -1.4 -1.6 -1.8 -2.0 -50 -30 -10 10 30 50 70 90 50 70 90 Ta(℃) 2) Polarity inversion circuit 0.0 -0.2 -0.4 Drop Voltage(V) Measurement condition DCCLK : 13.09kHz Step-up cycle : DCCLK/ 4 Temperature : 25℃ VCH : 16V VM : 0V Iload : 50μA -0.6 -0.8 -1.0 -1.2 -1.4 -1.6 -1.8 -2.0 -50 -30 -10 10 30 Ta( ℃) 37 HD66764 0.0 3) Step-up Circuit 2 -0.2 -0.4 Drop Voltage(V) a)Measurement condition Step-up factor : Twice DCCLK : 13.09kHz Step-up cycle : DCCLK/4 Temperature : 25℃ Vci2 : 5.0V Iload : 50μA -0.6 -0.8 -1.0 -1.2 -1.4 -1.6 -1.8 -2.0 -50 -30 -10 10 30 50 70 90 50 70 90 50 70 Ta( ℃) 0.0 -0.2 -0.4 Drop Voltage(V) b)Measurement condition Step-up factor : 3 times DCCLK : 13.09kHz Step-up cycle : DCCLK/4 Temperature : 25℃ Vci2 : 5.0V Iload : 50μA -0.6 -0.8 -1.0 -1.2 -1.4 -1.6 -1.8 -2.0 -50 -30 -10 10 30 Ta(℃) 0.0 -0.4 Drop Voltage(V) c)Measurement condition Step-up factor : 4 times DCCLK : 13.09kHz Step-up cycle : DCCLK/4 Temperature : 25℃ Vci2 : 5.0V Iload : 50μA -0.2 -0.6 -0.8 -1.0 -1.2 -1.4 -1.6 -1.8 -2.0 -50 -30 -10 10 30 Ta(℃) 38 90