GAL6002
High Performance E2CMOS FPLA
Generic Array Logic™
Features
Functional Block Diagram
ICLK
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— 15ns Maximum Propagation Delay
— 75MHz Maximum Frequency
— 6.5ns Maximum Clock to Output Delay
— TTL Compatible 16mA Outputs
— UltraMOS® Advanced CMOS Technology
INPUT
CLOCK
2
14
11
{
23
ILMC
IOLMC
AND
RESET
INPUTS
2-11
OUTPUT
ENABLE
• ACTIVE PULL-UPS ON ALL PINS
• LOW POWER CMOS
— 90mA Typical Icc
14
• E2 CELL TECHNOLOGY
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
D
23
OLMC
E
OR
0
D
7
BLMC
{ OUTPUTS
14 - 23
E
OCLK
• UNPRECEDENTED FUNCTIONAL DENSITY
— 78 x 64 x 36 FPLA Architecture
— 10 Output Logic Macrocells
— 8 Buried Logic Macrocells
— 20 Input and I/O Logic Macrocells
Macrocell Names
• HIGH-LEVEL DESIGN FLEXIBILITY
— Asynchronous or Synchronous Clocking
— Separate State Register and Input Clock Pins
— Functional Superset of Existing 24-pin PAL®
and FPLA Devices
BLMC
BURIED LOGIC MACROCELL
OLMC
OUTPUT LOGIC MACROCELL
ILMC
OUTPUT
CLOCK
INPUT LOGIC MACROCELL
IOLMC I/O LOGIC MACROCELL
PinNames
• APPLICATIONS INCLUDE:
— Sequencers
— State Machine Control
— Multiple PLD Device Integration
Description
I0 - I10
INPUT
I/O/Q
BIDIRECTIONAL
ICLK
INPUT CLOCK
VCC
POWER (+5V)
OCLK
OUTPUT CLOCK
GND
GROUND
Pin Configuration
Having an FPLA architecture, the GAL6002 provides superior
flexibility in state-machine design. The GAL6002 offers the highest
degree of functional integration, flexibility, and speed currently
available in a 24-pin, 300-mil package. E2CMOS technology offers
high speed (<100ms) erase times, providing the ability to reprogram
or reconfigure the device quickly and efficiently.
DIP
PLCC
4
I
I/O/Q
28
I/O/Q
NC
2
Vcc
I/ICLK
I
The GAL6002 has 10 programmable Output Logic Macrocells
(OLMC) and 8 programmable Buried Logic Macrocells (BLMC). In
addition, there are 10 Input Logic Macrocells (ILMC) and 10
I/O Logic Macrocells (IOLMC). Two clock inputs are provided for
independent control of the input and output macrocells.
I
I/ICLK
25
I
I
7
23
GAL6002
NC
I
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacturing. As a result, Lattice
Semiconductor delivers 100% field programmability and
functionality of all GAL products. In addition, 100 erase/write cycles
and data retention in excess of 20 years are specified.
9
Top View
21
I
11
I/O/Q
OCLK
I/O/Q
19
18
16
NC
14
I
I
12
Vcc
I/O/Q
GAL
6002
I/O/Q
I/O/Q
I
I/O/Q
I
I/O/Q
I
NC
I
I/O/Q
I
I/O/Q
I
I/O/Q
I/O/Q
GND
I
24
I/O/Q
I
26
5
1
I
I/O/Q
I/O/Q
6
I/O/Q
18
I/O/Q
I
I/O/Q
I
I/O/Q
GND
12
13
OCLK
Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
6002_02
1
July 1997
Specifications GAL6002
GAL6002 Commercial Device Ordering Information
Commercial Grade Specifications
Tpd (ns)
Fmax (MHz)
Icc (mA)
15
75
135
GAL6002B-15LP
24-Pin Plastic DIP
135
GAL6002B-15LJ
28-Lead PLCC
135
GAL6002B-20LP
24-Pin Plastic DIP
135
GAL6002B-20LJ
28-Lead PLCC
20
60
Ordering #
Package
Part Number Description
XXXXXXXX _ XX
X
X X
GAL6002B Device Name
Grade
Speed (ns)
L = Low Power
Power
Blank = Commercial
Package P = Plastic DIP
J = PLCC
2
Specifications GAL6002
Input Logic Macrocell (ILMC) and I/O Logic Macrocell (IOLMC)
The GAL6002 features two configurable input sections. The ILMC
section corresponds to the dedicated input pins (2-11) and the
IOLMC to the I/O pins (14-23). Each input section is individually
configurable as asynchronous, latched, or registered inputs. Pin
1 (ICLK) is used as an enable input for latched macrocells or as a
clock input for registered macrocells. Individually configurable
inputs provide system designers with unparalleled design flexibility.
With the GAL6002, external input registers and latches are not
necessary.
Both the ILMC and the IOLMC are individually configurable and the
ILMC can be configured independently of the IOLMC. The three
valid macrocell configurations and its associated fuse numbers are
shown in the diagrams on the following pages. Note that these
programmable cells are configured by the logic compiler software.
The user does not need to manually manipulate these architecture
bits.
Output Logic Macrocell (OLMC) and Buried Logic Macrocell (BLMC)
The outputs of the OR array feed two groups of macrocells. One
group of eight macrocells is buried; its outputs feed back directly
into the AND array rather than to device pins. These cells are called
the Buried Logic Macrocells (BLMC), and are useful for building
state machines. The second group of macrocells consists of 10
cells whose outputs, in addition to feeding back into the AND array,
are available at the device pins. Cells in this group are known as
Output Logic Macrocells (OLMC).
sum term is routed directly to the clock input. This permits
asynchronous programmable clocking, selected on a register-byregister basis.
Registers in both the Output and Buried Logic Macrocells feature
a common RESET product term. This active high product term
allows the registers to be asynchronously reset. All registers reset
to logic zero. With the inverting output buffers, the output pins will
reset to logic one.
The Output and Buried Logic Macrocells are configurable on a
macrocell by macrocell basis. Buried and Output Logic Macrocells
may be set to one of three configurations: combinational, D-type
register with sum term (asynchronous) clock, or D/E-type register.
Output macrocells always have I/O capability, with directional control
provided by the 10 output enable (OE) product terms. Additionally,
the polarity of each OLMC output is selected through the
programmable polarity control cell called XORD. Polarity selection
for BLMCs is selected through the true and complement forms of
their feedbacks to the AND array. Polarity of all E (Enable) sum
terms is selected through the XORE programmable cells.
There are two possible feedback paths from each OLMC. The first
path is directly from the OLMC (this feedback is before the output
buffer). When the OLMC is used as an output, the second feedback
path is through the IOLMC. With this dual feedback arrangement,
the OLMC can be permanently buried without losing the use of the
associated OLMC pin as an input, or dynamically buried with the
use of the output enable product term.
The D/E registers used in this device offer the designer the ultimate
in flexibility and utility. The D/E register architecture can emulate
RS, JK, and T registers with the same efficiency as a dedicated RS,
JK, or T registers.
When the output or buried logic macrocell is configured as a
D/E type register, the register is clocked from the common OCLK
and the register clock enable input is controlled by the associated
"E" sum term. This configuration is useful for building counters and
state-machines with count hold and state hold functions.
The three macrocell configurations are shown in the diagrams on
the following pages. These programmable cells are also configured
by the logic compiler software. The user does not need to manually
manipulate these architecture bits.
When the macrocell is configured as a D type register with a sum
term clock, the register is always enabled and the associated “E”
3
Specifications GAL6002
ILMC and IOLMC Configurations
ICLK
LATCH
E
Q
MUX
D
INVALID
REG.
INPUT
or I/O
Q
0
0
0
1
1
0
1
1
AND
ARRAY
D
LATCH(i) ISYN(i)
ILMC/IOLMC
Generic Logic Block Diagram
Input Macrocell JEDEC Fuse Numbers
I/O Macrocell JEDEC Fuse Numbers
INSYNC
INLATCH
ILMC
IOSYNC
IOLATCH
8218
8219
0
8238
8239
9
8220
8221
1
8240
8241
8
8222
8223
2
8242
8243
7
8224
8225
3
8244
8245
6
8226
8227
4
8246
8247
5
8228
8229
5
8248
8249
4
8230
8231
6
8250
8251
3
8232
8233
7
8252
8253
2
8234
8235
8
8254
8255
1
8236
8237
9
8256
8257
0
4
IOLMC
Specifications GAL6002
OLMC and BLMC Configurations
OE
PRODUCT
TERM
AND
ARRAY
RESET
IOLMC
MUX
OLMC ONLY
XORD(i)
1
R
I/O
D
D
MUX
Vcc
0
Q
0
E
OLMC ONLY
XORE(i)
OSYN(i)
1
E
MUX
CKS(i)
0
1
OCLK
OLMC/BLMC
Generic Logic Block Diagram
OLMC JEDEC Fuse Numbers
BLMC JEDEC Fuse Numbers
OLMC
CKS
OUTSYNC
XORE
XORD
BLMC
CKS
OUTSYNC
XORE
0
8178
8179
8180
8181
7
8175
8176
8177
1
8182
8183
8184
8185
6
8172
8173
8174
2
8186
8187
8188
8189
5
8169
8170
8171
3
8190
8191
8192
8193
4
8166
8167
8168
4
8194
8195
8196
8197
3
8163
8164
8165
5
8198
8199
8200
8201
2
8160
8161
8162
6
8202
8203
8204
8205
1
8157
8158
8159
7
8206
8207
8208
8209
0
8154
8155
8156
8
8210
8211
8212
8213
9
8214
8215
8216
8217
5
11(13)
9(11)
10(12)
8(10)
7(9)
6(7)
5(6)
4(5)
3(4)
2(3)
1(2)
ICLK
BLMC 7
BLMC 6
BLMC 5
BLMC 4
BLMC 3
BLMC 2
BLMC 1
BLMC 0
ILMC 9
ILMC 8
ILMC 7
ILMC 6
ILMC 5
ILMC 4
ILMC 3
ILMC 2
ILMC 1
ILMC 0
6
IOLMC 9
OLMC 9
OLMC 8
OLMC 7
OLMC 6
OLMC 5
OLMC 4
OLMC 3
OLMC 2
OLMC 1
OLMC 0
IOLMC 0
IOLMC 1
IOLMC 2
IOLMC 3
IOLMC 4
IOLMC 5
IOLMC 6
IOLMC 7
IOLMC 8
Specifications GAL6002
Logic Diagram
7
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
Q
1
Q
1
Q
1
Q
1
Q
1
Q
1
Q
1
Q
R
R
R
R
R
R
R
R
0
E
D
0
E
D
0
E
D
0
E
D
0
E
D
0
E
D
0
E
D
0
E
D
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
XORE
BLMC 0
XORE
BLMC 1
XORE
BLMC 2
XORE
BLMC 3
XORE
BLMC 4
XORE
BLMC 5
XORE
BLMC 6
XORE
BLMC 7
OCLK
RESET
OLMC 9
XORE
XORD
OLMC 0
XORE
XORD
OLMC 1
XORE
XORD
OLMC 2
XORE
XORD
OLMC 3
XORE
XORD
OLMC 4
XORE
XORD
OLMC 5
XORE
XORD
OLMC 6
XORE
XORD
OLMC 7
XORE
XORD
OLMC 8
XORE
XORD
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
E
D
0
E
D
0
E
D
0
E
D
0
E
D
0
E
D
0
E
D
0
E
D
0
E
D
0
E
D
R
R
R
R
R
R
R
R
R
R
1
Q
1
Q
1
Q
1
Q
1
Q
1
Q
1
Q
1
Q
1
Q
1
Q
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
13(16)
14(17)
15(18)
16(19)
17(20)
18(21)
19(23)
20(24)
21(25)
22(26)
23(27)
Specifications GAL6002
Logic Diagram (Continued)
Specifications GAL6002
Absolute Maximum Ratings(1)
Recommended Operating Conditions
Supply voltage VCC ...................................... –0.5 to +7V
Input voltage applied .......................... –2.5 to VCC +1.0V
Off-state output voltage applied ......... –2.5 to VCC +1.0V
Storage Temperature ................................ –65 to 150°C
Ambient Temperature with
Power Applied ........................................ –55 to 125°C
Commercial Devices:
Ambient Temperature (TA) ............................... 0 to 75°C
Supply voltage (VCC)
with Respect to Ground ..................... +4.75 to +5.25V
1.Stresses above those listed under the “Absolute Maximum
Ratings” may cause permanent damage to the device. These
are stress only ratings and functional operation of the device at
these or at any other conditions above those indicated in the
operational sections of this specification is not implied (while
programming, follow the programming specifications).
DC Electrical Characteristics
Over Recommended Operating Conditions (Unless Otherwise Specified)
SYMBOL
VIL
VIH
IIL1
IIH
VOL
VOH
IOL
IOH
IOS2
MIN.
TYP.3
MAX.
UNITS
Input Low Voltage
Vss – 0.5
—
0.8
V
Input High Voltage
2.0
—
Vcc+1
V
PARAMETER
CONDITION
Input or I/O Low Leakage Current
0V ≤ VIN ≤ VIL (MAX.)
—
—
-100
µA
Input or I/O High Leakage Current
3.5V ≤ VIN ≤ VCC
—
—
10
µA
Output Low Voltage
IOL = MAX. Vin = VIL or VIH
—
—
0.5
V
Output High Voltage
IOH = MAX. Vin = VIL or VIH
2.4
—
—
V
Low Level Output Current
—
—
16
mA
High Level Output Current
—
—
–3.2
mA
–30
—
–130
mA
—
90
135
mA
Output Short Circuit Current
COMMERCIAL
ICC
Operating Power
Supply Current
VCC = 5V
VOUT = 0.5V TA = 25°C
VIL = 0.5V VIH = 3.0V
L -15/-20
ftoggle = 15MHz Outputs Open
1) The leakage current is due to the internal pull-up resistor on all pins. See Input Buffer section for more information.
2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester
ground degradation. Characterized but not 100% tested.
3) Typical values are at Vcc = 5V and TA = 25 °C
Capacitance (TA = 25°C, f = 1.0 MHz)
SYMBOL
PARAMETER
MAXIMUM*
UNITS
TEST CONDITIONS
CI
Input Capacitance
8
pF
VCC = 5.0V, VI = 2.0V
CI/O
I/O Capacitance
8
pF
VCC = 5.0V, VI/O = 2.0V
*Characterized but not 100% tested.
8
Specifications GAL6002
AC Switching Characteristics
Over Recommended Operating Conditions
PARAM.
tpd1
tpd2
tpd3
tco1
tco2
tco3
tco4
tcf12
tcf22
tsu1
tsu2
tsu3
tsu4
tsu5
tsu6
th1
th2
th3
th4
fmax13
fmax23
fmax33
fmax43
fmax53
fmax63
twh1
twh2
twh3
TEST
COND1.
COM
COM
-15
-20
DESCRIPTION
UNITS
MIN. MAX. MIN. MAX.
A
Combinatorial Input to Combinatorial Output
—
15
—
20
ns
A
Feedback or I/O to Combinational Output
—
15
—
20
ns
A
Transparent Latch Input to Combinatorial Output
—
18
—
23
ns
A
Input Latch ICLK to Combinatorial Output Delay
—
20
—
25
ns
A
Input Reg. ICLK to Combinatorial Output Delay
—
20
—
25
ns
A
Output D/E Reg. OCLK to Output Delay
—
6.5
—
8
ns
A
Output D Reg. Sum Term CLK to Output Delay
—
18
—
20
ns
—
Output D/E Reg. OCLK to Buried Feedback Delay
—
3.6
—
7
ns
—
Output D Reg. STCLK to Buried Feedback Delay
— 10.1
—
13
ns
—
Setup Time, Input before Input Latch ICLK
1.5
—
2
—
ns
—
Setup Time, Input before Input Reg. ICLK
1.5
—
2
—
ns
—
Setup Time, Input or Fdbk before D/E Reg. OCLK
11.5 —
13
—
ns
—
Setup Time, Input or Fdbk before D Reg. Sum Term CLK
5
—
7
—
ns
—
Setup Time, Input Reg. ICLK before D/E Reg. OCLK
15
—
20
—
ns
—
Setup Time, Input Reg. ICLK before D Reg. Sum Term CLK
7
—
9
—
ns
—
Hold Time, Input after Input Latch ICLK
3
—
4
—
ns
—
Hold Time, Input after Input Reg. ICLK
3
—
4
—
ns
—
Hold Time, Input or Feedback after D/E Reg. OCLK
0
—
0
—
ns
—
Hold Time, Input or Feedback after D Reg. Sum Term CLK
4
—
6
—
ns
—
Max. Clock Frequency w/External Feedback, 1/(tsu3+tco3)
55.5 —
—
Max. Clock Frequency w/External Feedback, 1/(tsu4+tco4)
43.4 —
—
Max. Clock Frequency w/Internal Feedback, 1/(tsu3+tcf1)
66
—
Max. Clock Frequency w/Internal Feedback, 1/(tsu4+tcf2)
—
47.6 —
MHz
37
—
MHz
—
50
—
MHz
66
—
50
—
MHz
Max. Clock Frequency w/No Feedback, OCLK
75
—
60
—
MHz
—
Max. Clock Frequency w/No Feedback, STCLK
70
—
60
—
MHz
—
ICLK Pulse Duration, High
6
—
7
—
ns
—
OCLK Pulse Duration, High
6
—
7
—
ns
—
STCLK Pulse Duration, High
7
—
8
—
ns
1) Refer to Switching Test Conditions section.
2) Calculated from fmax with internal feedback. Refer to fmax Description section.
3) Refer to fmax Description section.
9
Specifications GAL6002
AC Switching Characteristics (Continued)
Over Recommended Operating Conditions
PARAMETER
TEST
COND1.
COM
COM
-15
-20
DESCRIPTION
MIN. MAX. MIN. MAX.
UNITS
twl1
twl2
twl3
tarw
ten
tdis
—
ICLK Pulse Duration, Low
6
—
7
—
ns
—
OCLK Pulse Duration, Low
6
—
7
—
ns
—
STCLK Pulse Duration, Low
7
—
8
—
ns
—
Reset Pulse Duration
12
—
15
—
ns
B
Input or I/O to Output Enabled
—
15
—
20
ns
C
Input or I/O to Output Disabled
—
15
—
20
ns
tar
tarr1
tarr2
A
Input or I/O to Asynchronous Reg. Reset
—
16
—
20
ns
—
Asynchronous Reset to OCLK Recovery Time
11
—
14
—
ns
—
Asynchronous Reset to Sum Term CLK Recovery Time
4
—
6
—
ns
1) Refer to Switching Test Conditions section.
10
Specifications GAL6002
Switching Waveforms
INPUT or
I/O FEEDBACK
INPUT or
I/O FEEDBACK
VALID INPUT
VALID INPUT
tsu2
tpd1,2
COMBINATORIAL
OUTPUT
th2
ICLK (REGISTER)
tco2
COMBINATORIAL
OUTPUT
Combinatorial Output
tsu5
INPUT or
I/O FEEDBACK
OCLK
VALID INPUT
tsu1
tsu6
th1
Sum Term CLK
ICLK (LATCH)
tco1
tpd3
Registered Input
COMBINATORIAL
OUTPUT
Latched Input
INPUT or
I/O FEEDBACK
INPUT or
I/O FEEDBACK
tsu3
VALID INPUT
tsu4
VALID INPUT
th4
th3
OCLK
tco3
Sum Term CLK
1/ fmax1
tco4
REGISTERED
OUTPUT
REGISTERED
OUTPUT
1/ fmax2
Registered Output (OCLK)
Registered Output (Sum Term CLK)
INPUT or
I/O FEEDBACK
tdis
INPUT or
I/O FEEDBACK
DRIVING AR
ten
tarw
REGISTERED
OUTPUT
OUTPUT
tar
Input or I/O to Output Enable/Disable
Sum Term CLK
twh1,2
tarr2
twl1,2
ICLK or
OCLK
OCLK
twh3
tarr1
twl3
Asynchronous Reset
Sum Term CLK
Clock Width
11
Specifications GAL6002
fmax Descriptions
CLK
CLK
LOGIC
ARRAY
REGISTER
LOGIC
ARRAY
REGISTER
tsu
tco
fmax with External Feedback 1/(tsu+tco)
t cf
t pd
Note: fmax with external feedback is calculated from measured
tsu and tco.
fmax with Internal Feedback 1/(tsu+tcf)
CLK
LOGIC
ARRAY
Note: tcf is a calculated value, derived by subtracting tsu from
the period of fmax w/internal feedback (tcf = 1/fmax - tsu). The
value of tcf is used primarily when calculating the delay from
clocking a register to a combinatorial output (through registered
feedback), as shown above. For example, the timing from clock
to a combinatorial output is equal to tcf + tpd.
REGISTER
fmax with No Feedback
Note: fmax with no feedback may be less than 1/(twh + twl). This
is to allow for a clock duty cycle of other than 50%.
Switching Test Conditions
Input Pulse Levels
GND to 3.0V
Input Rise and Fall Times
+5V
3ns 10% – 90%
Input Timing Reference Levels
1.5V
Output Timing Reference Levels
1.5V
Output Load
R1
See Figure
3-state levels are measured 0.5V from steady-state active
level.
FROM OUTPUT (O/Q)
UNDER TEST
R2
Output Load Conditions (see figure)
Test Condition
R1
R2
CL
300Ω
390Ω
50pF
Active High
∞
390Ω
50pF
Active Low
300Ω
390Ω
50pF
Active High
∞
390Ω
5pF
Active Low
300Ω
390Ω
5pF
A
B
C
TEST POINT
C L*
*C L INCLUDES TEST FIXTURE AND PROBE CAPACITANCE
12
Specifications GAL6002
Array Description
Register Preload
The GAL6002 contains two E2 reprogrammable arrays. The first is
an AND array and the second is an OR array. These arrays are described in detail below.
AND ARRAY
The AND array is organized as 78 inputs by 75 product term outputs.
The 10 ILMCs, 10 IOLMCs, 8 BLMC feedbacks, 10 OLMC feedbacks, and ICLK comprise the 39 inputs to this array (each available
in true and complement forms). 64 product terms serve as inputs
to the OR array. The RESET product term generates the RESET
signal described in the Output and Buried Logic Macrocells section. There are 10 output enable product terms which allow device
I/O pins to be bi-directional or tri-state.
OR ARRAY
The OR array is organized as 64 inputs by 36 sum term outputs.
64 product terms from the AND array serve as the inputs to the OR
array. Of the 36 sum term outputs, 18 are data (“D”) terms and 18
are enable/clock (“E”) terms. These terms feed into the 10 OLMCs
and 8 BLMCs, one “D” term and one “E” term to each.
The programmable OR array offers unparalleled versatility in product term usage. This programmability allows from 1 to 64 product
terms to be connected to a single sum term. A programmable OR
array is more flexible than a fixed, shared, or variable product term
architecture.
When testing state machine designs, all possible states and state
transitions must be verified, not just those required during normal
operations. This is because certain events may occur during system operation that cause the logic to be in an illegal state (powerup, line voltage glitches, brown-out, etc.). To test a design for proper
treatment of these conditions, a method must be provided to break
the feedback paths and force any desired state (i.e., illegal) into the
registers. Then the machine can be sequenced and the outputs
tested for correct next state generation.
All of the registers in the GAL6002 can be preloaded, including the
ILMC, IOLMC, OLMC, and BLMC registers. In addition, the contents of the state and output registers can be examined in a special
diagnostics mode. Programming hardware takes care of all preload
timing and voltage requirements.
Latch-Up Protection
GAL6002 devices are designed with an on-board charge pump to
negatively bias the substrate. The negative bias is of sufficient
magnitude to prevent input undershoots from causing the circuitry
to latch. Additionally, outputs are designed with n-channel pull-ups
instead of the traditional p-channel pull-ups to eliminate any possibility of SCR induced latching.
Input Buffers
Electronic Signature
GAL6002 devices are designed with TTL level compatible input
buffers. These buffers have a characteristically high impedance,
and present a much lighter load to the driving logic than bipolar TTL
devices.
An electronic signature is provided with every GAL6002 device. It
contains 72 bits of reprogrammable memory that can contain user
defined data. Some uses include user ID codes, revision numbers,
or inventory control. The signature data is always available to the
user independent of the state of the security cell.
GAL6002 input buffers have active pull-ups within their input structure. This pull-up will cause any un-terminated input or I/O to float
to a TTL high (logical 1). Lattice Semiconductor recommends that
all unused inputs and tri-stated I/O pins be connected to another
active input, Vcc, or GND. Doing this will tend to improve noise
immunity and reduce Icc for the device.
Security Cell
A security cell is provided with every GAL6002 device as a deterrent
to unauthorized copying of the array patterns. Once programmed,
this cell prevents further read access to the AND array. This cell
can be erased only during a bulk erase cycle, so the original configuration can never be examined once this cell is programmed.
The Electronic Signature is always available to the user, regardless of the state of this control cell.
Typical Input Pull-up Characteristic
I n p u t C u r r e n t (u A )
NOTE: The electronic signature is included in checksum calculations. Changing the electronic signature will alter the checksum.
0
-20
-40
-60
Device Programming
0
1.0
2.0
3.0
In p u t V o lt ag e ( V o lt s)
GAL devices are programmed using a Lattice Semiconductorapproved Logic Programmer, available from a number of manufacturers. Complete programming of the device takes only a few
seconds. Erasing of the device is transparent to the user, and is
done automatically as part of the programming cycle.
13
4.0
5.0
Specifications GAL6002
Power-Up Reset
Vcc
Vcc (min.)
t su
t wl
CLK
t pr
INTERNAL REGISTER
Q - OUTPUT
Internal Register
Reset to Logic "0"
FEEDBACK/EXTERNAL
OUTPUT REGISTER
Device Pin
Reset to Logic "1"
of system power-up, some conditions must be met to provide a
valid power-up reset of the GAL6002. First, the VCC rise must be
monotonic. Second, the clock input must be at static TTL level
as shown in the diagram during power up. The registers will reset
within a maximum of tpr time. As in normal system operation,
avoid clocking the device until all input and feedback path setup
times have been met. The clock must also meet the minimum
pulse width requirements.
Circuitry within the GAL6002 provides a reset signal to all registers
during power-up. All internal registers will have their Q outputs
set low after a specified time (tpr, 1µs MAX). As a result, the state
on the registered output pins (if they are enabled) will always be
high on power-up, regardless of the programmed polarity of the
output pins. This feature can greatly simplify state machine design
by providing a known state on power-up. The timing diagram for
power-up is shown below. Because of the asynchronous nature
Differential Product Term Switching (DPTS) Applications
The number of Differential Product Term Switching (DPTS ) for
a given design is calculated by subtracting the total number of
product terms that are switching from a Logical HI to a Logical LO
from those switching from a Logical LO to a Logical HI within a
5ns period. After subtracting take the absolute value.
The majority of designs fall below 15 DPTS, with the upper limit
being approximately 25 DPTS. Lattice Semiconductor guarantees
and tests the commercial grade GAL6002 for functionality at
DPTS ≤30.
DPTS = (P-Terms)LH - (P-Terms)HL
A software utility is available from Lattice Semiconductor
Applications Engineering that will perform this calculation on any
GAL6002 JEDEC file. This program, DPTS, and additional
information may be obtained from your local Lattice
Semiconductor representative or by contacting Lattice
Semiconductor Applications Engineering Dept. (Tel: 503-681-0118
or 1-888-ISP-PLDS; FAX: 681-3037).
DPTS restricts the number of product terms that can be switched
simultaneously - there is no limit on the number of product terms
that can be used.
14
Specifications GAL6002
Typical AC and DC Characteristic Diagrams
Normalized Tpd vs Vcc
1.2
1.2
1.1
PT L->H
1
0.9
0.8
RISE
1.1
Normalized Tsu
PT H->L
Normalized Tco
FALL
1
0.9
4.75
5.00
5.25
5.50
4.50
4.75
Supply Voltage (V)
Normalized Tpd vs Temp
5.00
5.25
Normalized Tco
PT H->L
1.2
PT L->H
1.1
1
0.9
0.8
-25
0
25
50
75
100
1.4
RISE
1.2
FALL
1.1
1
0.9
0.8
PT H->L
1.2
PT L->H
1.1
1
0.9
0.8
0.7
-25
0
25
50
75
100
125
-55
-25
0
-0.5
-1
RISE
-1.5
FALL
-2
-0.5
-1
RISE
-1.5
FALL
-2
4
5
6
7
8
9
10
1
Number of Outputs Switching
2
3
4
5
6
7
8
9
10
Number of Outputs Switching
Delta Tpd vs Output Loading
Delta Tco vs Output Loading
12
10
RISE
8
FALL
Delta Tco (ns)
12
6
4
2
10
RISE
8
FALL
6
4
2
0
0
-2
-2
0
50
100
150
200
250
0
300
50
100
150
200
250
Output Loading (pF)
Output Loading (pF)
15
0
25
50
75
100
Temperature (deg. C)
Delta Tco vs # of Outputs
Switching
Delta Tco (ns)
Delta Tpd (ns)
1.3
Temperature (deg. C)
3
5.50
Normalized Tsu vs Temp
0
2
5.25
Normalized Tco vs Temp
Delta Tpd vs # of Outputs
Switching
1
5.00
Supply Voltage (V)
-55
125
4.75
Supply Voltage (V)
Temperature (deg. C)
Delta Tpd (ns)
-55
0.9
4.50
0.7
0.7
PT L->H
1
5.50
1.3
1.3
PT H->L
1.1
0.8
0.8
4.50
Normalized Tsu
Normalized Tpd
1.2
Normalized Tpd
Normalized Tsu vs Vcc
Normalized Tco vs Vcc
300
125
Specifications GAL6002
Typical AC and DC Characteristic Diagrams
Voh vs Ioh
5
2
4
1.5
1
0.5
4.25
3
2
20.00
40.00
60.00
80.00
3.5
0.00
10.00
20.00
30.00
40.00
50.00
60.00
0.00
1.00
2.00
3.00
Iol (mA)
Ioh(mA)
Ioh(mA)
Normalized Icc vs Vcc
Normalized Icc vs Temp
Normalized Icc vs Freq.
1.2
1.10
1.00
0.90
0.80
1.1
1
0.9
0.8
0.7
4.75
5.00
5.25
5.50
Supply Voltage (V)
2.5
2
30
40
Iik (mA)
0
1
0
25
75
100
125
50
60
70
80
0.5
90
100
0
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00
Vin (V)
1.00
0.90
-2.00
-1.50
-1.00
Vik (V)
16
-0.50
0
25
50
75
Frequency (MHz)
Input Clamp (Vik)
Delta Icc vs Vin (1 input)
1.5
-25
Temperature (deg. C)
10
20
1.10
0.80
-55
3
4.00
1.20
Normalized Icc
Normalized Icc
1.20
4.50
4
3.75
0
0.00
Normalized Icc
4.5
1
0
Delta Icc (mA)
Voh vs Ioh
Voh (V)
2.5
Voh (V)
Vol (V)
Vol vs Iol
0.00
100