Micrel, Inc. ULTRA PRECISION 4×4 CML SWITCH WITH INTERNAL I/O TERMINATION SY58040U Precision Edge® SY58040U FEATURES ■ Provides crosspoint switching between any input pair to any output pair ■ Guaranteed AC performance over temperature and voltage: • DC to >5Gbps throughput • <350ps propagation delay • <60ps tr / tf times • <25ps skew (output-to-output) ■ Unique, patent-pending, channel-to-channel isolation design provides superior crosstalk performance ■ Ultra-low jitter design: • <1psRMS random jitter • <10psPP deterministic jitter • <10psPP total jitter (clock) • <0.7psRMS crosstalk-induced jitter ■ Unique, patent-pending, 50Ω input termination extended CMVR, and VT pin accepts DC- and ACcoupled differential inputs ■ 400mV CML output swing ■ 50Ω source terminated outputs minimize round-trip reflections ■ Power supply 2.5V ±5% or 3.3V ±10% ■ –40°C to +85°C temperature range ■ Available in 44-pin (7mm × 7mm) MLF® package ■ Pb-Free green package Precision Edge® DESCRIPTION The SY58040U is a low jitter, low skew, high-speed 4×4 crosspoint switch optimized for precision telecom and enterprise server/storage distribution applications. The SY58040U distributes clock frequencies from DC to 4GHz, and data rates to 5Gbps guaranteed over temperature and voltage. The SY58040U differential input includes Micrel’s unique, 3-pin input termination architecture that directly interfaces to any differential signal (AC- or DC-coupled) as small as 100mV (200mVpp) without any level shifting or termination resistor networks in the signal path. The outputs are 50Ω source-terminated CML with extremely fast rise/fall times guaranteed to be less than 60ps. The SY58040U features a patent-pending isolation design that significantly improves on channel-to-channel crosstalk performance. The SY58040U operates from a 2.5V ±5% or 3.3V ±10% supply and is guaranteed over the full industrial temperature range of –40°C to +85°C. The SY58040U is part of Micrel’s high-speed, Precision Edge® product line. Datasheets and support documentation can be found on Micrel’s web site at: www.micrel.com. APPLICATIONS ■ ■ ■ ■ Data communication systems All SONET/SDH data/clock applications All Fibre Channel applications All Gigabit Ethernet applications Precision Edge is a registered trademark of Micrel, Inc. MLF and MicroLeadFrame are registered trademarks of Amkor Technology, Inc. M9999-103009 [email protected] or (408) 955-1690 1 Rev.: E Amendment: /0 Issue Date: October 2009 SY58040U Micrel, Inc. Functional block diagram IN0 VT0 /IN0 VREF-AC0 50W 0 50W 1 Q0 2 /Q0 3 IN1 VT1 /IN1 VREF-AC1 0 50Ω 50Ω 1 Q1 2 /Q1 3 IN2 VT2 /IN2 VREF-AC2 0 50Ω 1 Q2 50Ω 2 /Q2 3 0 IN3 VT3 /IN3 VREF-AC3 50Ω 1 Q3 2 /Q3 3 50Ω SIN0 (CMOS/TTL) SIN1 (CMOS/TTL) SOUT0 (CMOS/TTL) Control Logic SOUT1 (CMOS/TTL) CONF (CMOS/TTL) LOAD (CMOS/TTL) TRUTH TABLES Output Select Address Table SOUT1 SOUT0 OUTPUT 0 0 Q0 0 1 Q1 Input Select Address Table SIN1 SIN0 INPUT 0 0 IN0 0 1 IN1 1 0 IN2 1 0 Q2 1 1 IN3 1 1 Q3 M9999-103009 [email protected] or (408) 955-1690 2 SY58040U Micrel, Inc. PACKAGE/ORDERING INFORMATION GND GND VREF-AC3 IN3 VT3 /IN3 SOUT0 SOUT1 GND GND VCC Ordering Information(1) VREF-AC2 /IN2 VT2 IN2 CONFIG VCC LOAD /IN1 VT1 IN1 VREF-AC1 44 43 42 41 40 39 38 37 36 35 34 1 33 2 32 3 31 4 30 5 29 6 28 7 27 8 26 9 25 10 24 11 23 GND GND VREF-AC0 /IN0 VT0 IN0 SIN0 SIN1 GND GND VCC 12 13 14 15 16 17 18 19 20 21 22 Package Operating Type Range Part Number /Q3 Q3 VCC /Q2 Q2 VCC /Q1 Q1 VCC /Q0 Q0 Package Marking Lead Finish Sn-Pb SY58040UMI MLF-44 Industrial SY58040U SY58040UMITR(2) MLF-44 Industrial SY58040U Sn-Pb SY58040UMY(3) MLF-44 Industrial SY58040U Pb-Free bar-line indicator Pb-Free Matte-Sn SY58040UMYTR(2, 3) MLF-44 Industrial SY58040U Pb-Free bar-line indicator Pb-Free Matte-Sn Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC electricals only. 2. Tape and Reel. 3. Pb-Free package recommended for new designs. 44-Pin MLF® (MLF-44) PIN DESCRIPTION Pin Number Pin Name Pin Function 17, 15, IN0, /IN0 Differential Inputs: These input pairs are the differential signal inputs to the device. Inputs accept 10, 8, IN1, /IN1 AC or DC-coupled signals as small as 100mV. Each pin of a pair internally terminates to a VT pin 4, 2, IN2, /IN2 through 50Ω. Note that these inputs will default to an indeterminate state if left open. Please refer to 41, 39 IN3, /IN3 the “Input Interface Applications” section for more details. 16, 9, VT0, VT1 Input Termination Center-Tap: Each side of the differential input pair terminates to a VT pin. The VT 3, 40 VT2, VT3 pins provide a center-tap to a termination network for maximum interface flexibility. See “Input Interface Applications” section for more details. 14, VRef_AC0 Reference Voltage: This output biases to VCC–1.2V. It is used when AC coupling the inputs. 11, VRef_AC1 Connect VRef-AC output pin to the VT input pin. Bypass each VRef-AC pin with a 0.01µF low ESR 1, VRef_AC2 capacitor to VCC. See “Input Interface Applications” section for more details. 42 VRef_AC3 18 SIN0 These single-ended TTL/CMOS-compatible inputs address the data inputs. Note that these inputs 19 SIN1 are internally connected to a 25kΩ pull-up resistor and will default to a logic HIGH state if left open. 38 SOUT0 These single-ended TTL/CMOS-compatible inputs address the data outputs. Note that these inputs 37 SOUT1 are internally connected to a 25kΩ pullup resistor and will default to a logic HIGH state if left open. 5 CONF, These single-ended TTL/CMOS compatible inputs control the transfer of the addresses to the 7 LOAD internal multiplexers. See “Address Tables” and “Timing Diagram” sections for more details. Note that these inputs are internally connected to a 25kΩ pull-up resistor and will default to a logic HIGH state if left open. Configuration Sequence 23, 24, Q0, /Q0, 26, 27, Q1, /Q1, 29, 30 Q2, /Q2, 32, 33 Q3, /Q3, 6, 22, 25, VCC 28, 31, 34 12, 13, 20, 21, GND, 35, 36, 43, 44 Exposed pad 1.Load: Loads configuration into buffer, while Configuration Buffer holds existing switch configuration. 2.Configuration: Loads new configuration into the Configuration Buffer and updates switch configuration. Buffer Mode The SY58040U defaults to buffer mode (IN-to-Q) if the load and configuration control signals are floating. Differential Outputs: These CML output pairs are the outputs of the device. Please refer to the truth table below for details. Unused output pairs may be left open. Each output is designed to drive 400mV into 100Ω across the pair, or 50Ω to VCC. Positive power supply. Bypass with 0.1µF//0.01µF low ESR capacitors and place as close to each VCC pin. Ground. GND and EPad must both be connected to most negative potential of chip ground. M9999-103009 [email protected] or (408) 955-1690 3 SY58040U Micrel, Inc. Absolute Maximum Ratings(1) Operating Ratings(2) Power Supply Voltage (VCC )........................–0.5V to +4.0V Input Voltage (VIN)............................................–0.5V to VCC CML Output Voltage (VOUT)...........VCC –0.5V to VCC +5.0V Termination Current(3) Source or sink current on VT pin......................... ±100mA Input Current(3) Source or sink current on IN, /IN........................... ±50mA VREF-AC Current(3) Source or sink current on IN, /IN............................. ±2mA Lead Temperature (soldering, 20 sec.)....................... 260°C Storage Temperature Range (TS )............. –65°C to +150°C Power Supply Voltage (VCC).................. +2.375V to +3.60V Ambient Temperature Range (TA)............... –40°C to +85°C Package Thermal Resistance(4) MLF® (θJA) Still-Air.............................................................. 23°C/W MLF® (ψJB) Junction-to-board.............................................. 12°C/W DC ELECTRICAL CHARACTERISTICS(5) TA= –40°C to +85°C, unless otherwise stated. Symbol Parameter VCC Power Supply Voltage Power Supply Current ICC Condition Min Typ Max Units VCC = 2.5V. 2.375 2.5 2.625 V 3.0 3.3 3.6 V 225 300 mA VCC = 3.3V. No load, max. VCC. Includes current from internal 50Ω pull-up on each output. RIN Input Resistance (IN-to-VT, /IN-to-VT) VIH Input HIGH Voltage (IN-to-/IN) VIL Input LOW Voltage (IN-to-/IN) VIN Input Voltage Swing (IN-to-/IN) VDIFF_IN Differential Input Voltage Swing |IN – /IN| VT_IN IN to VT (IN-to-/IN) RDIFF_IN VREF-AC 45 50 55 Ω 90 100 110 Ω VCC V 0 VIH–0.1 V See Figure 1a. 0.1 1.7 V See Figure 1b. 0.2 Differential Input Resistance (IN-to-/IN) Note 6 VCC–1.6 Output Reference Voltage 1.28 VCC–1.3 VCC–1.2 VCC–1.1 V V V Notes: 1. Permanent device damage may occur if ratings in the “Absolute Maximum Ratings” section are exceeded. This is a stress rating only and functional operation is not implied for conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. Due to the limited drive capability, use for input of the same package only. 4. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the device’s most negative potential on the PCB. θJA uses 4-layer in still-air number, unless otherwise stated. 5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. 6. VIH (min) not lower than 1.2V. M9999-103009 [email protected] or (408) 955-1690 4 SY58040U Micrel, Inc. CML OUTPUT DC Electrical Characteristics(7) VCC = 2.5V ±5% or 3.3V ±10%; TA= –40°C to +85°C; RL = 100Ω across each output pair, unless otherwise stated. Symbol Parameter Condition Min Typ Max Units VOH Output HIGH Voltage VCC–0.040VCC–0.010 Q, /Q VCC V VOUT Output Differential Swing Q, /Q See Figure 1a. 325 400 mV VDIFF_OUT Differential Output Voltage Swing Q, /Q See Figure 1b. 650 800 mV ROUT Output Source Impedance 45 50 55 Ω Min Typ Max Units VCC V 0.8 V 30 µA LVTTL/CMOS DC Electrical Characteristics(7) VCC = 2.5V ±5% or 3.3V ±10%; TA= –40°C to +85°C, unless otherwise stated. Symbol Parameter VIH Input HIGH Voltage IIH Input HIGH Current –125 Input LOW Current –300 VIL IIL Condition 2.0 Input LOW Voltage VIL = 0V. Note: 7. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. M9999-103009 [email protected] or (408) 955-1690 5 µA SY58040U Micrel, Inc. AC ELECTRICAL CHARACTERISTICS(8) VCC = 2.5V ±5% or 3.3V ±10%; TA= –40°C to +85°C, RL = 100Ω across each output pair, unless otherwise stated. Symbol Parameter fMAX Maximum Operating Frequency tpd Differential Propagation Delay tpw Condition NRZ data VOUT ≥ 200mV Min 150 Set-Up Time SIN-to-LOAD 225 Units Gbps GHz 350 ps 500 ps 1500 ∆tpd Tempco Differential Propagation Delay Temperature Coefficient tS 3 CONFIG-to-Q Pulse Width of LOAD/CONFIG signal Max 5 Clock IN-to-Q Typ 225 800 ps fs/°C ps SOUT-to-LOAD 800 ps LOAD-to-CONFIG 800 ps CONFIG-to-LOAD 950 ps Hold Time tH LOAD-to-SIN, LOAD-to-SOUT 800 ps tSKEW Output-to-Output Skew Note 9 25 Part-to-Part Skew tJITTER Data Clock Note 10 150 ps Random Jitter (RJ) Note 11 1 psRMS Deterministic Jitter (DJ) Note 12 10 psPP Cycle-to-Cycle Jitter Total Jitter (TJ) Crosstalk-induced Jitter tr, tf ps Output Rise/Fall Time Note 13 1 psRMS Note 14 10 psPP Note 15 0.7 psRMS At full output swing, 20% to 80%. 60 ps 20 40 Notes: 8. High-frequency AC-parameters are guaranteed by design and characterization. 9. Output-to-output skew is measured between two different outputs under identical input transitions. 10.Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the respective inputs 11.Random jitter is measured with a K28.7 character pattern, measured at <fMAX. 12.Deterministic jitter is measured at 2.5Gbps/3.2Gbps, with both K28.5 and 223–1 PRBS pattern. 13.Cycle-to-cycle jitter definition: the variation of periods between adjacent cycles, Tn – Tn-1 where T is the time between rising edges of the output signal. 14.Total jitter definition: with an ideal clock input of frequency <fMAX, no more than one output edge in 1012 output edges will deviate by more than the specified peak-to-peak jitter value. 15.Crosstalk induced jitter is defined as the added jitter that results from signals applied to two adjacent channels. It is measured at the output while applying two similar differential clock frequencies that are asynchronous with respect to each other at the inputs. M9999-103009 [email protected] or (408) 955-1690 6 SY58040U Micrel, Inc. TYPICAL OPERATING CHARACTERISTICS VCC = 3.3V, GND = 0, VIN = 100mV, TA = 25°C, unless otherwise stated. 400 380 360 340 320 0 2000 4000 FREQUENCY (MHz) M9999-103009 [email protected] or (408) 955-1690 6000 20 18 16 14 within-DeviceSkew vs. Temperature (ReferencedtoQ0) Q0 Q1 12 10 8 6 4 Q2 2 0 -40 -20 0 20 40 Q3 60 80 100 TEMPERATURE (°C) 7 270 PROPAGATION DELAY (ps) 420 WITHIN DEVICE SKEW (ps) OUTPUT AMPLITUDE (mV) 440 Output Amplitude vs.Frequency Propagation Delay vs. Temperature 265 260 255 250 245 F = 200MHz 240 235 -40 -20 0 20 40 60 80 100 TEMPERATURE (°C) SY58040U Micrel, Inc. FUNCTIONAL CHARACTERISTICS VCC = 3.3V, GND = 0, VIN = 100mV, TA = 25°C, unless otherwise stated. 622MHzOutput Output Swing (100mV/div.) Output Swing (100mV/div.) 200MHzOutput TIME (100ps/div.) TIME (200ps/div.) Output Swing (200mV/div.) 5GbpsOutput(Q–/Q) TIME (50ps/div.) M9999-103009 [email protected] or (408) 955-1690 8 SY58040U Micrel, Inc. Single-Ended and Differential SwingS VDIFF_IN, VDIFF_OUT 800mV (Typ.) VIN, VOUT 400mV (Typ.) Figure 1a. Single-Ended Voltage Swing Figure 1b. Differential Voltage Swing TIMING DIAGRAM Input Address SIN [1:0] Output Address SOUT [1:0] tS (SIN-LOAD) LOAD tS (SOUT-LOAD) tH (LOAD-SIN/SOUT) tS (CONFIG-LOAD) tPW tS (LOAD-CONFIG) CONFIG tPW /IN [3:0] IN [3:0] tpd tPD (CONFIG-Q) /Q [3:0] Invalid(1) Q [3:0] Valid(1) Note: 1.Invalid and Valid refers to onfiguation being changed. All outputs with unchanged configuration remain valid. M9999-103009 [email protected] or (408) 955-1690 9 SY58040U Micrel, Inc. Input AND OUTPUT STAGES VCC VCC 50Ω 50Ω /Q ZO = 50Ω 100Ω IN Q 50Ω VT 50Ω 100mA GND GND /IN Figure 2b. CML DC-Coupled (100Ω Termination) Figure 2a. Simplified Differential Input Stage VCC 50Ω 50Ω ZO = 50Ω /Q Q ZO = 50Ω DC bias per application 100mA GND Figure 2c. CML AC-Coupled (50Ω Termination) M9999-103009 [email protected] or (408) 955-1690 ZO = 50Ω 10 SY58040U Micrel, Inc. INPUT INTERFACE APPLICATIONS VCC VCC VCC IN IN LVPECL VCC GND 0.01µF V T Rpd VREF-AC CML /IN SY58040U NC IN LVPECL /IN Rpd VCC GND Figure 3a. LVPECL Interface (DC-Coupled) SY58040U VT GND VREF-AC GND For VCC = 3.3V, Rpd = 50Ω. For VCC = 2.5V, Rpd = 19Ω. /IN SY58040U Rpd 0.01µF For 3.3V, Rpd = 100Ω. For 2.5V, Rpd = 50Ω. NC VT NC VREF-AC Option: May connect VT to VCC. Figure 3b. LVPECL Interface (AC-Coupled) Figure 3c. CML Interface (DC-Coupled) VCC VCC IN CML /IN GND IN SY58040U VCC LVDS /IN VT VREF-AC 0.01µF Figure 3d. CML Interface (AC-Coupled) SY58040U GND NC VT NC VREF-AC Figure 3e. LVDS Interface RELATED MICREL PRODUCTS and support documentation Part Number Function Data Sheet Link SY58040U Ultra Precision 4×4 CML Crosspoint Switch with Internal Input/Output Termination http://www.micrel.com/product-info/products/sy58040u.shtml MLF® Application Note www.amkor.com/products/notes_paper/MLF_AppNote.pdf HBW Solutions New Products and Applications www.micrel.com/product-info/products/solutions.shtml M9999-103009 [email protected] or (408) 955-1690 11 SY58040U Micrel, Inc. 44-pin MicroLeadFrame® (mlf-44) Package EP- Exposed Pad Die CompSide Island Heat Dissipation Heat Dissipation Heavy Copper Plane Heavy Copper Plane VEE VEE PCB Thermal Consideration for 44-Pin MLF® Package (Always solder, or equivalent, the exposed pad to the PCB) Package Notes: 1. Package meets Level 2 qualification. 2. All parts are dry-packaged before shipment. 3. Exposed pads must be soldered to a ground for proper thermal management. MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA tel + 1 (408) 944-0800 fax + 1 (408) 474-1000 web http://www.micrel.com The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2005 Micrel, Incorporated. M9999-103009 [email protected] or (408) 955-1690 12