ONSEMI MC74VHC4066DTR2G

MC74VHC4066
Quad Analog Switch/
Multiplexer/Demultiplexer
High−Performance Silicon−Gate CMOS
The MC74VHC4066 utilizes silicon−gate CMOS technology to
achieve fast propagation delays, low ON resistances, and low
O F F −c h a n n e l
leakage
current.
This
bilateral
switch/multiplexer/demultiplexer controls analog and digital voltages
that may vary across the full power−supply range (from VCC to GND).
The VHC4066 is identical in pinout to the metal−gate CMOS
MC14066 and the high−speed CMOS HC4066A. Each device has four
independent switches. The device has been designed so that the ON
resistances (RON) are much more linear over input voltage than RON
of metal−gate CMOS analog switches.
The ON/OFF control inputs are compatible with standard CMOS
outputs; with pullup resistors, they are compatible with LSTTL
outputs. For analog switches with voltage−level translators, see the
VHC4316.
Features
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MARKING
DIAGRAMS
14
SOIC−14
D SUFFIX
CASE 751A
1
1
14
VHC
4066
ALYWG
G
TSSOP−14
DT SUFFIX
CASE 948G
1
Fast Switching and Propagation Speeds
High ON/OFF Output Voltage Ratio
Low Crosstalk Between Switches
Diode Protection on All Inputs/Outputs
Wide Power−Supply Voltage Range (VCC − GND) = 2.0 to 12.0 Volts
Analog Input Voltage Range (VCC − GND) = 2.0 to 12.0 Volts
Improved Linearity and Lower ON Resistance over Input Voltage
than the MC14016 or MC14066
Low Noise
Chip Complexity: 44 FETs or 11 Equivalent Gates
These Devices are Pb−Free and are RoHS Compliant
VHC4066G
AWLYWW
1
14
SOEIAJ−14
M SUFFIX
CASE 965
1
VHC4066
ALYWG
1
A
= Assembly Location
WL, L
= Wafer Lot
Y
= Year
WW, W = Work Week
G or G
= Pb−Free Package
(Note: Microdot may be in either location)
FUNCTION TABLE
PIN ASSIGNMENT
XA
1
14
YA
2
13
YB
3
12
XB
B ON/OFF
CONTROL
C ON/OFF
CONTROL
GND
4
11
VCC
A ON/OFF
CONTROL
D ON/OFF
CONTROL
XD
5
10
YD
6
9
YC
7
8
XC
On/Off Control
Input
State of
Analog Switch
L
H
Off
On
ORDERING INFORMATION
Device
Package
Shipping†
MC74VHC4066DR2G
SOIC−14
2500 / T&R
MC74VHC4066DTR2G TSSOP−14
MC74VHC4066MG
SOEIAJ−14
2500 / T&R
50 / Rail
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2011
May, 2011 − Rev. 6
1
Publication Order Number:
MC74VHC4066/D
MC74VHC4066
XA
A ON/OFF CONTROL
XB
B ON/OFF CONTROL
XC
C ON/OFF CONTROL
XD
D ON/OFF CONTROL
1
2
YA
13
4
3
YB
ANALOG
OUTPUTS/INPUTS
5
8
9
YC
6
11
10
YD
ANALOG INPUTS/OUTPUTS = XA, XB, XC, XD
PIN 14 = VCC
PIN 7 = GND
12
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Figure 1. Logic Diagram
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
– 0.5 to + 14.0
V
Analog Input Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
Digital Input Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
± 25
mA
500
450
mW
– 65 to + 150
_C
VCC
Positive DC Supply Voltage (Referenced to GND)
VIS
Vin
I
DC Current Into or Out of Any Pin
PD
Power Dissipation in Still Air,
Tstg
Storage Temperature
SOIC Package†
TSSOP Package†
TL
Lead Temperature, 1 mm from Case for 10 Seconds
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: − 6.1 mW/_C from 65_ to 125_C
_C
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RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
2.0
12.0
V
Analog Input Voltage (Referenced to GND)
GND
VCC
V
Digital Input Voltage (Referenced to GND)
GND
VCC
V
Static or Dynamic Voltage Across Switch
—
1.2
V
– 55
+ 125
_C
VCC
Positive DC Supply Voltage (Referenced to GND)
VIS
Vin
VIO*
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time, ON/OFF Control
ns
Inputs (Figure 14)
VCC = 2.0 V
0
1000
VCC = 3.0 V
0
600
VCC = 4.5 V
0
500
VCC = 9.0 V
0
400
0
250
VCC = 12.0 V
*For voltage drops across the switch greater than 1.2 V (switch on), excessive VCC current may
be drawn; i.e., the current out of the switch may contain both VCC and switch input
components. The reliability of the device will be unaffected unless the Maximum Ratings are
exceeded.
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2
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V CC ).
Unused outputs must be left open.
I/O pins must be connected to a
properly terminated line or bus.
MC74VHC4066
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DC ELECTRICAL CHARACTERISTIC Digital Section (Voltages Referenced to GND)
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
– 55 to
25_C
v 85_C
v
125_C
Unit
VIH
Minimum High−Level Voltage
ON/OFF Control Inputs
Ron = Per Spec
2.0
3.0
4.5
9.0
12.0
1.5
2.1
3.15
6.3
8.4
1.5
2.1
3.15
6.3
8.4
1.5
2.1
3.15
6.3
8.4
V
VIL
Maximum Low−Level Voltage
ON/OFF Control Inputs
Ron = Per Spec
2.0
3.0
4.5
9.0
12.0
0.5
0.9
1.35
2.7
3.6
0.5
0.9
1.35
2.7
3.6
0.5
0.9
1.35
2.7
3.6
V
Iin
Maximum Input Leakage
Current
ON/OFF Control Inputs
Vin = VCC or GND
12.0
± 0.1
± 1.0
± 1.0
μA
ICC
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
VIO = 0 V
6.0
12.0
2
4
20
40
40
160
μA
DC ELECTRICAL CHARACTERISTICS Analog Section (Voltages Referenced to GND)
Guaranteed Limit
VCC
V
– 55 to
25_C
v 85_C
v
125_C
Vin = VIH
VIS = VCC to GND
IS v 2.0 mA
(Figures 2 through 7)
2.0†
3.0†
4.5
9.0
12.0
—
—
120
70
70
—
—
160
85
85
—
—
200
100
100
Vin = VIH
VIS = VCC or GND (Endpoints)
IS v 2.0 mA
(Figures 2 through 7)
2.0
3.0
4.5
9.0
12.0
—
—
70
50
30
—
—
85
60
60
—
—
100
80
80
Maximum Difference in “ON”
Resistance Between Any Two
Channels in the Same Package
Vin = VIH
VIS = 1/2 (VCC − GND)
IS v 2.0 mA
2.0
4.5
9.0
12.0
—
20
15
15
—
25
20
20
—
30
25
25
Ω
Ioff
Maximum Off−Channel
Leakage
Current, Any One Channel
Vin = VIL
VIO = VCC or GND
Switch Off (Figure NO TAG)
12.0
0.1
0.5
1.0
μA
Ion
Maximum On−Channel
Leakage
Current, Any One Channel
Vin = VIH
VIS = VCC or GND
(Figure NO TAG)
12.0
0.1
0.5
1.0
μA
Symbol
Ron
ΔRon
Parameter
Maximum “ON” Resistance
Test Conditions
Unit
Ω
†At supply voltage (VCC) approaching 3 V the analog switch−on resistance becomes extremely non−linear. Therefore, for low−voltage
operation, it is recommended that these devices only be used to control digital signals.
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3
MC74VHC4066
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AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, ON/OFF Control Inputs: tr = tf = 6 ns)
Guaranteed Limit
Symbol
Parameter
VCC
V
– 55 to
25_C
v 85_C
v
125_C
Unit
tPLH,
tPHL
Maximum Propagation Delay, Analog Input to Analog Output
(Figures 18 and 13)
2.0
3.0
4.5
9.0
12.0
40
30
5
5
5
50
40
7
7
7
60
50
8
8
8
ns
tPLZ,
tPHZ
Maximum Propagation Delay, ON/OFF Control to Analog Output
(Figures 14 and 15)
2.0
3.0
4.5
9.0
12.0
80
60
20
20
20
90
70
25
25
25
110
80
35
35
35
ns
tPZL,
tPZH
Maximum Propagation Delay, ON/OFF Control to Analog Output
(Figures 14 and 15)
2.0
3.0
4.5
9.0
12.0
80
45
20
20
20
90
50
25
25
25
100
60
30
30
30
ns
ON/OFF Control Input
—
10
10
10
pF
Control Input = GND
Analog I/O
Feedthrough
—
—
35
1.0
35
1.0
35
1.0
C
Maximum Capacitance
Typical @ 25°C, VCC = 5.0 V
CPD
15
Power Dissipation Capacitance (Per Switch) (Figure 17)*
* Used to determine the no−load dynamic power consumption: P D = CPD VCC
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4
2f
+ ICC VCC .
pF
MC74VHC4066
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ADDITIONAL APPLICATION CHARACTERISTICS (Voltages Referenced to GND Unless Noted)
VCC
V
Limit*
25_C
74HC
Symbol
Parameter
Test Conditions
BW
Maximum On−Channel Bandwidth or
Minimum Frequency Response
(Figure NO TAG)
fin = 1 MHz Sine Wave
Adjust fin Voltage to Obtain 0 dBm at VOS
Increase fin Frequency Until dB Meter Reads
– 3 dB
RL = 50 Ω, CL = 10 pF
4.5
9.0
12.0
150
160
160
MHz
Off−Channel Feedthrough Isolation
(Figure NO TAG)
fin Sine Wave
Adjust fin Voltage to Obtain 0 dBm at VIS
fin = 10 kHz, RL = 600 Ω, CL = 50 pF
4.5
9.0
12.0
− 50
− 50
− 50
dB
fin = 1.0 MHz, RL = 50 Ω, CL = 10 pF
4.5
9.0
12.0
− 40
− 40
− 40
Vin v 1 MHz Square Wave (tr = tf = 6 ns)
Adjust RL at Setup so that IS = 0 A
RL = 600 Ω, CL = 50 pF
4.5
9.0
12.0
60
130
200
RL = 10 kΩ, CL = 10 pF
4.5
9.0
12.0
30
65
100
fin Sine Wave
Adjust fin Voltage to Obtain 0 dBm at VIS
fin = 10 kHz, RL = 600 Ω, CL = 50 pF
4.5
9.0
12.0
– 70
– 70
– 70
fin = 1.0 MHz, RL = 50 Ω, CL = 10 pF
4.5
9.0
12.0
– 80
– 80
– 80
—
—
—
Crosstalk Between Any Two
Switches
(Figure 16)
Total Harmonic Distortion
(Figure 20)
fin = 1 kHz, RL = 10 kΩ, CL = 50 pF
THD = THDMeasured − THDSource
VIS = 4.0 VPP sine wave
VIS = 8.0 VPP sine wave
VIS = 11.0 VPP sine wave
*Guaranteed limits not tested. Determined by design and verified by qualification.
4.5
9.0
12.0
0.10
0.06
0.04
350
300
250
200
150
+25 _C
+125_C
−55_C
100
50
0
0.00
0.20
0.40
0.60
0.80
1.00
1.20
1.40
1.60
Vis, INPUT VOLTAGE (VOLTS), REFERENCED TO GROUND
Figure 2. Typical On Resistance, VCC = 2.0 V
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5
mVPP
dB
%
400
RON @ 2 V
THD
Feedthrough Noise, Control to
Switch
(Figure NO TAG)
Unit
1.80
2.00
MC74VHC4066
200
180
RON @ 4.5 V
160
140
+25 _C
+125_C
−55_C
120
100
80
60
40
20
0
0.00
0.50
1.00
1.50
2.00
2.50
3.00
3.50
4.00
4.50
Vis, INPUT VOLTAGE (VOLTS), REFERENCED TO GROUND
Figure 3. Typical On Resistance, VCC = 4.5 V
90
80
RON @ 6 V
70
60
50
40
30
+25 _C
+125_C
−55_C
20
10
0
0.00
0.50
1.00
1.50
2.00
2.50
3.00
3.50
4.00
4.50
Vis, INPUT VOLTAGE (VOLTS), REFERENCED TO GROUND
Figure 4. Typical On Resistance, VCC = 6.0 V
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6
5.00
5.50
6.00
MC74VHC4066
90
+25 _C
+125_C
−55_C
80
RON @ 9V
70
60
50
40
30
20
10
0
0.00
1.00
2.00
3.00
4.00
5.00
6.00
7.00
8.00
9.00
Vis, INPUT VOLTAGE (VOLTS), REFERENCED TO GROUND
Figure 5. Typical On Resistance, VCC = 9.0 V
60
RON @ 12 V
50
40
30
20
+25 _C
+125_C
−55_C
10
0
0.00
1.00
2.00
3.00
4.00
5.00
6.00
7.00
8.00
9.00
10.00
Vis, INPUT VOLTAGE (VOLTS), REFERENCED TO GROUND
Figure 6. Typical On Resistance, VCC = 12 V
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7
11.00
12.00
MC74VHC4066
PLOTTER
VCC
PROGRAMMABLE
POWER
SUPPLY
-
VCC
MINI COMPUTER
DC ANALYZER
+
14
GND
A
VCC
VCC
OFF
DEVICE
UNDER TEST
ANALOG IN
COMMON OUT
SELECTED
CONTROL
INPUT
7
VIL
GND
Figure 7. On Resistance Test Set−Up
Figure 8. Maximum Off Channel Leakage Current,
Any One Channel, Test Set−Up
VCC
VCC
VCC
14
14
A
VOS
fin
N/C
ON
ON
0.1μF
SELECTED
CONTROL
INPUT
7
dB
METER
CL*
GND
VIH
7
SELECTED
CONTROL
INPUT
VCC
*Includes all probe and jig capacitance.
Figure 9. Maximum On Channel Leakage Current,
Test Set−Up
VCC
VIS
Figure 10. Maximum On−Channel Bandwidth
Test Set−Up
VCC
VCC/2
VOS
14
14
fin
OFF
0.1μF
CL*
RL
VCC/2
RL
RL
dB
METER
OFF/ON
IS
VOS
CL*
SELECTED
CONTROL
INPUT
7
VCC
GND
Vin ≤ 1 MHz
tr = tf = 6 ns
7
SELECTED
CONTROL
INPUT
CONTROL
*Includes all probe and jig capacitance.
*Includes all probe and jig capacitance.
Figure 11. Off−Channel Feedthrough Isolation,
Test Set−Up
Figure 12. Feedthrough Noise, ON/OFF Control to
Analog Out, Test Set−Up
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8
MC74VHC4066
VCC
14
VCC
ANALOG IN
ANALOG OUT
ON
50%
ANALOG IN
CL*
GND
tPLH
TEST
POINT
tPHL
50%
ANALOG OUT
7
SELECTED
CONTROL
INPUT
VCC
*Includes all probe and jig capacitance.
Figure 18. Propagation Delays, Analog In to
Analog Out
Figure 13. Propagation Delay Test Set−Up
1
POSITIONWHEN
TESTING tPHZ AND tPZH
tr
CONTROL
tf
VCC
90%
50%
10%
1 kΩ
14
HIGH
IMPEDANCE
10%
tPZH
VCC
VCC
1
tPLZ
50%
ANALOG
OUT
2
GND
tPZL
2
POSITIONWHEN
TESTING tPLZ AND tPZL
1
CL*
VOL
SELECTED
CONTROL
INPUT
tPHZ
90%
50%
TEST
POINT
ON/OFF
2
VOH
7
HIGH
IMPEDANCE
*Includes all probe and jig capacitance.
Figure 14. Propagation Delay, ON/OFF Control
to Analog Out
Figure 15. Propagation Delay Test Set−Up
VIS
VCC
VCC
14
RL
fin
VOS
A
ON
0.1 μF
14
N/C
OFF
VCC OR GND
RL
RL
SELECTED
CONTROL
INPUT
CL*
VCC/2
RL
OFF/ON
CL*
VCC/2
7
7
VCC/2
SELECTED
CONTROL
INPUT
ON/OFF CONTROL
*Includes all probe and jig capacitance.
Figure 16. Crosstalk Between Any Two Switches,
Test Set−Up
Figure 17. Power Dissipation Capacitance
Test Set−Up
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9
N/C
MC74VHC4066
0
-10
VCC
VOS
fin
ON
RL
CL*
TO
DISTORTION
METER
-30
7
-40
-50
DEVICE
-60
VCC/2
SELECTED
CONTROL
INPUT
FUNDAMENTAL FREQUENCY
-20
0.1 μF
dBm
VIS
SOURCE
-70
VCC
-80
-90
*Includes all probe and jig capacitance.
1.0
Figure 20. Total Harmonic Distortion, Test Set−Up
Figure 19. Plot, Harmonic Distortion
APPLICATION INFORMATION
the example below, the difference between VCC and GND is
twelve volts. Therefore, using the configuration in Figure 21,
a maximum analog signal of twelve volts peak−to−peak can
be controlled.
When voltage transients above VCC and/or below GND
are anticipated on the analog channels, external diodes
(Dx) are recommended as shown in Figure 22. These
diodes should be small signal, fast turn−on types able to
absorb the maximum anticipated current surges during
clipping. An alternate method would be to replace the Dx
diodes with Mosorbs (high current surge protectors).
Mosorbs are fast turn−on devices ideally suited for precise
DC protection with no inherent wear out mechanism.
3.0
2.0
FREQUENCY (kHz)
The ON/OFF Control pins should be at VCC or GND logic
levels, VCC being recognized as logic high and GND being
recognized as a logic low. Unused analog inputs/outputs
may be left floating (not connected). However, it is
advisable to tie unused analog inputs and outputs to VCC or
GND through a low value resistor. This minimizes crosstalk
and feedthrough noise that may be picked−up by the
unused I/O pins.
The maximum analog voltage swings are determined by
the supply voltages V CC and GND. The positive peak
analog voltage should not exceed V CC . Similarly, the
negative peak analog voltage should not go below GND. In
VCC = 12 V
+ 12 V
14
ANALOG I/O
ON
ANALOG O/I
VCC
VCC
Dx
+ 12 V
16
ON
0V
0V
Dx
SELECTED
CONTROL
INPUT
7
Dx
VCC
OTHER CONTROL
INPUTS
(VCC OR GND)
Dx
SELECTED
CONTROL
INPUT
7
Figure 21. 12 V Application
OTHER CONTROL
INPUTS
(VCC OR GND)
Figure 22. Transient Suppressor Application
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10
MC74VHC4066
+5 V
+5 V
14
ANALOG
SIGNALS
R*
R* R* R*
VHC4066
LSTTL/
NMOS
6
VHCT
BUFFER
LSTTL/
NMOS
5
15
ANALOG
SIGNALS
VHC4066
5
6
CONTROL
INPUTS
14
14
ANALOG
SIGNALS
ANALOG
SIGNALS
CONTROL
INPUTS
14
15
7
7
R* = 2 TO 10 kΩ
a. Using Pull-Up Resistors
b. Using HCT Buffer
Figure 23. LSTTL/NMOS to HCMOS Interface
VDD = 5 V
13
1
VCC = 5 TO 12 V
16
14
ANALOG
SIGNALS
3
ANALOG
SIGNALS
VHC4066
5
2
5
9
4
6
11
6
14
CONTROL
INPUTS
10
15
7
7
14
MC14504
8
Figure 24. TTL/NMOS−to−CMOS Level Converter Analog Signal
Peak−to−Peak Greater than 5 V
(Also see VHC4316)
CHANNEL 4
1 OF 4
SWITCHES
CHANNEL 3
1 OF 4
SWITCHES
CHANNEL 2
1 OF 4
SWITCHES
COMMON I/O
INPUT
CHANNEL 1
1 OF 4
SWITCHES
1
1 OF 4
SWITCHES
+
OUTPUT
LF356 OR
EQUIVALENT
0.01 μF
2
3 4
CONTROL INPUTS
Figure 25. 4−Input Multiplexer
Figure 26. Sample/Hold Amplifier
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11
MC74VHC4066
PACKAGE DIMENSIONS
SOIC−14
CASE 751A−03
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
−A−
14
8
−B−
P 7 PL
0.25 (0.010)
M
7
1
G
−T−
D 14 PL
0.25 (0.010)
T B
S
A
DIM
A
B
C
D
F
G
J
K
M
P
R
J
M
K
M
F
R X 45 _
C
SEATING
PLANE
B
M
S
SOLDERING FOOTPRINT*
7X
7.04
14X
1.52
1
14X
0.58
1.27
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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12
MILLIMETERS
MIN
MAX
8.55
8.75
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.337 0.344
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
0.008 0.009
0.004 0.009
0_
7_
0.228 0.244
0.010 0.019
MC74VHC4066
PACKAGE DIMENSIONS
TSSOP−14
DT SUFFIX
CASE 948G−01
ISSUE B
14X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
S
S
N
2X
14
L/2
0.25 (0.010)
8
M
B
−U−
L
PIN 1
IDENT.
N
F
7
1
0.15 (0.006) T U
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
DETAIL E
K
A
−V−
K1
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
J J1
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
SECTION N−N
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
D
H
G
DETAIL E
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
14X
0.36
14X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
13
MILLIMETERS
INCHES
MIN
MAX
MIN MAX
4.90
5.10 0.193 0.200
4.30
4.50 0.169 0.177
−−−
1.20
−−− 0.047
0.05
0.15 0.002 0.006
0.50
0.75 0.020 0.030
0.65 BSC
0.026 BSC
0.50
0.60 0.020 0.024
0.09
0.20 0.004 0.008
0.09
0.16 0.004 0.006
0.19
0.30 0.007 0.012
0.19
0.25 0.007 0.010
6.40 BSC
0.252 BSC
0_
8_
0_
8_
MC74VHC4066
PACKAGE DIMENSIONS
SOEIAJ−14
CASE 965−01
ISSUE B
14
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
LE
8
Q1
E HE
L
7
1
M_
DETAIL P
Z
D
VIEW P
A
e
A1
b
0.13 (0.005)
c
M
0.10 (0.004)
DIM
A
A1
b
c
D
E
e
HE
L
LE
M
Q1
Z
MILLIMETERS
MIN
MAX
--2.05
0.05
0.20
0.35
0.50
0.10
0.20
9.90
10.50
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10 _
0_
0.70
0.90
--1.42
INCHES
MIN
MAX
--0.081
0.002
0.008
0.014
0.020
0.004
0.008
0.390
0.413
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10 _
0_
0.028
0.035
--0.056
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
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PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
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14
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For additional information, please contact your local
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MC74VHC4066/D