FAIRCHILD 74F125SCX

Revised September 2000
74F125
Quad Buffer (3-STATE)
Features
■ High impedance base inputs for reduced loading
Ordering Code:
Order Number
Package Number
Package Description
74F125SC
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
74F125SJ
M14D
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F125PC
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
IEEE/IEC
Unit Loading/Fan Out
Pin Names
U.L.
Input IIH/IIL
HIGH/LOW
Output IOH/IOL
1.0/0.033
20 µA/−20 µA
Description
An, Bn
Inputs
On
Outputs
600/106.6 (80) −12 mA/64 mA (48 mA)
Function Table
Inputs
Output
An
Bn
L
L
L
L
H
H
H
X
Z
O
H = HIGH Voltage Level
L = LOW Voltage Level
Z = High Impedance
X = Immaterial
© 2000 Fairchild Semiconductor Corporation
DS009475
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74F125 Quad Buffer (3-STATE)
April 1988
74F125
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
Storage Temperature
−65°C to +150°C
Ambient Temperature under Bias
−55°C to +125°C
Free Air Ambient Temperature
Junction Temperature under Bias
−55°C to +150°C
Supply Voltage
0°C to +70°C
+4.5V to +5.5V
−0.5V to +7.0V
VCC Pin Potential to Ground Pin
Input Voltage (Note 2)
−0.5V to +7.0V
Input Current (Note 2)
−30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with VCC = 0V)
Standard Output
−0.5V to VCC
3-STATE Output
−0.5V to +5.5V
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Current Applied to Output
in LOW State (Max)
twice the rated IOL (mA)
DC Electrical Characteristics
Symbol
Parameter
Min
Typ
Max
Input HIGH Voltage
VIL
Input LOW Voltage
0.8
V
VCD
Input Clamp Diode Voltage
−1.2
V
VOH
VOL
2.0
Units
VIH
Output HIGH
10% VCC
2.4
Voltage
10% VCC
2.0
5% VCC
2.7
5% VCC
2.0
Output LOW
VCC
Conditions
V
Recognized as a HIGH Signal
Recognized as a LOW Signal
IIN = −18 mA
Min
IOH = −3 mA
IOH = −12 mA
V
Min
0.55
V
Min
IOL = 64 mA
20
µA
Max
VIN = 2.7V
IOH = −3 mA
IOH = −15 mA
10% VCC
Voltage
IIH
Input HIGH Current
IBVI
Input HIGH Current
100
µA
0.0V
VIN = 7.0V
−20.0
µA
Max
VIN = 0.5V
Output Leakage Current
50
µA
Max
VOUT = 2.7V
Output Leakage Current
−50
µA
Max
VOUT = 0.5V
−225
mA
Max
VOUT = 0V
Output HIGH Leakage Current
250
µA
Max
VOUT = VCC
IZZ
Buss Drainage Test
500
µA
0.0V
VOUT = 5.25V
ICCH
Power Supply Current
18.5
24.0
mA
Max
VO = HIGH
ICCL
Power Supply Current
31.7
40.0
mA
Max
VO = LOW
ICCZ
Power Supply Current
27.6
35.0
mA
Max
VO = HIGH Z
Breakdown Test
IIL
Input LOW Current
IOZH
IOZL
IOS
Output Short-Circuit Current
ICEX
−100
AC Electrical Characteristics
Symbol
tPLH
Parameter
Propagation Delay
tPHL
tPZH
Output Enable Time
tPZL
tPHZ
Output Disable Time
tPLZ
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TA = +25°C
TA = 0°C to +70°C
VCC = +5.0V
VCC = +5.0V
CL = 50 pF
CL = 50 pF
Min
Typ
Max
Min
Max
2.0
4.0
6.0
2.0
6.5
3.0
4.6
7.5
3.0
8.0
3.5
4.7
7.5
3.0
8.5
3.5
5.3
8.0
3.5
9.0
1.5
3.9
5.5
1.5
6.0
1.5
4.0
6.0
1.5
6.5
2
Units
ns
ns
ns
74F125
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
Package Number M14A
3
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74F125
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D
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4
74F125 Quad Buffer (3-STATE)
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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