SANYO LC863524

Ordering number : ENN*6844
CMOS IC
LC863532A/28A/24A/20A/16A
8-Bit Single-Chip Microcontroller
Preliminary
Overview
The LC863532/28/24/20/16A are 8-bit single chip microcontrollers with the following on-chip functional blocks:
- CPU : Operable at a minimum bus cycle time of 0.424µs
- On-chip ROM capacity
Program ROM : 32K/28K/24K/20K/16K bytes
CGROM : 16K bytes
- On-chip RAM capacity : 512 bytes
- OSD RAM : 352 × 9 bits
- Closed-Caption TV controller and the on-screen display controller
- Four channels × 6-bit AD Converter
- Three channels × 7-bit PWM
- Two channels × 16-bit timer/counter, 14-bit base timer
- IIC-bus compliant serial interface circuit (Multi-master type)
- ROM correction function
- 12-source 8-vectored interrupt system
- Integrated system clock generator and display clock generator
Only one X’tal oscillator (32.768kHz) for PLL reference is used for both generators
TV control and the Closed Caption function
All of the above functions are fabricated on a single chip.
Note : This product includes the IIC bus interface circuit. If you intend to use the IIC bus interface, please
notify us of this in advance of our receiving your program ROM code order.
Purchase of SANYO IIC components conveys a license under the Philips IIC Patents Rights to use these
components in an IIC system, provided that the system conforms to the IIC Standard Specification as
defined by Philips.
Trademarks
IIC is a trademark of Philips Corporation.
Ver.1.00
00000
D2700 RM (IM) Shindo No.6844-1/19
LC863532A/28A/24A/20A/16A
Features
(1) Read-Only Memory (ROM) :
32768 × 8 bits / 28672 × 8 bits / 24576 × 8 bits
20486 × 8 bits / 16384 × 8 bits for program
16128 × 8 bits for CGROM
(2) Random Access Memory (RAM) :
384 × 8 bits (working area)
128 × 8 bits (working or ROM correction function)
352 × 9 bits (for CRT display)
(3) OSD functions
- Screen display
: 36 characters × 16 lines (by software)
- RAM
: 352 words (9 bits per word)
Display area
: 36 words × 8 lines
Control area
: 8 words × 8 lines
- Characters
Up to 252 kinds of 16 × 32 dot character fonts
(4 characters including 1 test character are not programmable)
Each font can be divided into two parts and used as two fonts (Ex. 16 × 16 dot character font × 2)
At least 111 characters need to be divide between a 16×18 dot and 8 × 9 dot character font to display the caption
fonts.
- Various character attributes
Character colors
: 16 colors (analog mode: lvp-p output) / 8 colors (digital/mode)
Character background colors
: 16 colors (analog mode: lvp-p output) / 8 colors (digital/mode)
Fringe / shadow colors
: 16 colors (analog mode: lvp-p output) / 8 colors (digital/mode)
Full screen colors
: 16 colors (analog mode: lvp-p output) / 8 colors (digital/mode)
Rounding
Underline
Italic character (slanting)
- Attribute can be changed without spacing
- Vertical display start line number can be set for each row independently (Rows can be overlapped)
- Horizontal display start position can be set for each row independently
- Horizontal pitch (bit 9 - 16)*1 and vertical pitch (bit-32) can be set for each row independently
- Different display modes can be set for each row independently
Caption • Text mode / OSD mode 1 / OSD mode 2 (Quarter size) / Simplifed graphic mode
- Ten character sizes *1
Horez. × Vert. = (1 × 1), (1 × 2), (2 × 2), (2 × 4), (0.5 × 0.5)
(1.5 × 1), (1.5 × 2), (3 × 2), (3 × 4), (0.75 × 0.5)
- Shuttering and scrolling on each row
- Simplified Graphic Display
*1 Note : range depends on display mode : refer to the manual for details.
(4) Bus Cycle Time / Instruction-Cycle Time
Bus cycle time Instruction cycle time Clock divider
1/2
0.424µs
0.848µs
7.5µs
91.55µs
183.1µs
15.0µs
183.1µs
366.2µs
1/2
1/1
1/2
System clock oscillation
Internal VCO
(Ref : X’tal 32.768kHz)
Internal RC
Crystal
Crystal
Oscillation Frequency
14.156MHz
Voltage
4.5V to 5.5V
800kHz
32.768kHz
32.768kHz
4.5V to 5.5V
4.5V to 5.5V
4.5V to 5.5V
(5) Ports
- Input / Output Ports
: 4 ports (24 terminals)
Data direction programmable in nibble units
: 1 port (8 terminals)
(If the N-ch open drain output is selected by option, the corresponding port data can be read in output mode.)
Data direction programmable for each bit individually
: 3 ports (16 terminals)
No.6844-2/19
LC863532A/28A/24A/20A/16A
(6) AD converter
- 4 channels × 6-bit AD converters
(7) Serial interfaces
- IIC-bus compliant serial interface (Multi-master type)
Consists of a single built-in circuit with two I/O channels.
internally.
The two data lines and two clock lines can be connected
(8) PWM output
- 3 channels × 7-bit PWM
(9) Timer
- Timer 0 : 16-bit timer/counter
With 2-bit prescaler + 8-bit programmable prescaler
Mode 0 : Two 8-bit timers with a programmable prescaler
Mode 1 : 8-bit timer with a programmable prescaler + 8-bit counter
Mode 2 : 16-bit timer with a programmable prescaler
Mode 3 : 16-bit counter
The resolution of timer is 1 tCYC.
- Timer 1 : 16-bit timer/PWM
Mode 0 : Two 8-bit timers
Mode 1 : 8-bit timer + 8-bit PWM
Mode 2 : 16-bit timer
Mode 3 : a variable-bit PWM (9 to 16 bits)
In mode 0/1, the resolution of timer/PWM is 1 tCYC
In mode 2/3, the resolution of timer/PWM is selectable by program; tCYC or 1/2 tCYC
- Base timer
Generate every 500ms overflow for a clock application (using 32.768kHz crystal oscillation for the base timer clock)
Generate every 976µs, 3.9ms, 15.6ms, 62.5ms overflow (using 32.768kHz crystal oscillation for the base timer
clock)
Clock for the base timer is selectable from 32.768kHz crystal oscillation, system clock or programmable prescaler
output of Timer 0
(10) Remote control receiver circuit (connected to the P73/INT3/T0IN terminal)
- Noise rejection function
- Polarity switching
(11) Watchdog timer
External RC circuit is required
Interrupt or system reset is activated when the timer overflows
(12) ROM correction function
Max 128 bytes / 2 addresses
No.6844-3/19
LC863532A/28A/24A/20A/16A
(13) Interrupts
- 12 sources 8 vectored interrupts
1. External Interrupt INT0
2. External Interrupt INT1
3. External Interrupt INT2, Timer/counter T0L (Lower 8 bits)
4. External Interrupt INT3, base timer
5. Timer/counter T0H (Upper 8 bits)
6. Timer T1H, Timer T1L
7. Vertical synchronous signal interrupt ( VS ), horizontal line ( HS )
8. IIC
- Interrupt priority control
Three interrupt priorities are supported (low, high and highest) and multi-level nesting is possible. Low or high
priority can be assigned to the interrupts from 3 to 8 listed above. For the external interrupt INT0 and INT1, low or
highest priority can be set.
(14) Sub-routine stack level
- A maximum of 128 levels (stack is built in the internal RAM)
(15) Multiplication/division instruction
- 16 bits × 8 bits (7 instruction cycle times)
- 16 bits / 8 bits (7 instruction cycle times)
(16) 3 oscillation circuits
- Built-in RC oscillation circuit used for the system clock
- Built-in VCO circuit used for the system clock and OSD
- X’tal oscillation circuit used for base timer, system clock and PLL reference
(17) Standby function
- HALT mode
The HALT mode is used to reduce the power dissipation. In this operation mode, the program execution is
stopped. This mode can be released by the interrupt request or the system reset.
- HOLD mode
The HOLD mode is used to stop the oscillations; RC (internal), VCO, and X’tal oscillations. This mode can be
released by the following conditions.
• Pull the reset terminal ( RES ) to low level.
• Feed the selected level to either P70/INT0 or P71/INT1.
(18) Package
- MFP36S
- DIP36S
(19) Development tools
- Flash EEPROM:
- Evaluation chip:
- Emulator:
LC86F3548A
LC863096
EVA86000 (main) + ECB863400 (evaluation chip board)
+ POD36-CABLE (cable)
+ POD36-DIP (for DIP36S)
or POD36-MFP (for MFP36S)
No.6844-4/19
LC863532A/28A/24A/20A/16A
System Block Diagram
Interrupt Control
IR
X’tal
RC
VCO
ROM
Clock
Generator
Standby Control
PLA
PC
PLL
IIC
ROM Correct Control
ACC
XRAM
B Register
Timer 0
Bus Interface
C Register
Timer 1
Port 1
ALU
Base Timer
Port 3
ADC
Port 7
PSW
INT0-3
Noise Rejection Filter
RAR
PWM
RAM
CGROM
OSD
Control
Circuit
Stack Pointer
VRAM
Port 0
Watch Dog Timer
No.6844-5/19
LC863532A/28A/24A/20A/16A
Pin Assignment
P10/SDA0
1
36
P03
P11/SCLK0
2
35
P02
P12/SDA1
3
34
P01
P13/SCLK1
4
33
P00
VSS
5
32
P17
XT1
6
31
P16/PWM3
XT2
7
30
P15/PWM2
VDD
8
29
P14/PWM1
P04/AN4
9
28
P73/INT3/T0IN
P05/AN5
10
27
P72/INT2/T0IN
P06/AN6
11
26
P71/INT1
P07/AN7
12
25
P70/INT0
RES
13
24
P32
FILT
14
23
P31
P33
15
22
BL
P30
16
21
B
VS
17
20
G
HS
18
19
R
Package Dimension
(unit : mm)
3204
SANYO : MFP-36S
Package Dimension
(unit : mm)
3170
SANYO : DIP-36S
No.6844-6/19
LC863532A/28A/24A/20A/16A
Pin Description
Pin Description Table
Terminal
VSS
XT1
XT2
VDD
I/O
Function Description
I
O
I
Negative power supply
Input terminal for crystal oscillator
Output terminal for crystal oscillator
Positive power supply
Reset terminal
VS
O
I
Filter terminal for PLL
Vertical synchronization signal input terminal
HS
R
G
B
BL
I
Horizontal synchronization signal input terminal
O
O
O
O
Red (R) output terminal of RGB image output
Green (G) output terminal of RGB image output
Blue (B) output terminal of RGB image output
Fast blanking control signal
Switch TV image signal and caption/OSD image signal
•8-bit input/output port,
Input/output can be specified in nibble unit
(If the N-ch open drain output is selected by option, the
corresponding port data can be read in output mode.)
•Other functions
AD converter input port (P04 to P07: 4 channels)
•8-bit input/output port
Input/output can be specified for each bit
(programmable pull-up resister provided)
•Other functions
P10 IIC0 data I/O
P11 IIC0 clock output
P12 IIC1 data I/O
P13 IIC1 clock output
P14 PWM1 output
P15 PWM2 output
P16 PWM3 output
P17 Timer 1 (PWM) output
RES
FILT
Port 0
P00 to P07
I/O
Port 1
P10 to P17
I/O
Port 3
P30 to P33
I/O
Option
Pull-up resistor
provided/not provided
Output Format
CMOS/Nch-OD
Output Format
CMOS/Nch-OD
•4-bit input/output port
Input/output can be specified for each bit
(CMOS output/input with programmable pull-up resister)
No.6844-7/19
LC863532A/28A/24A/20A/16A
Terminal
Port 7
P70
P71 to P73
I/O
I/O
Function Description
•4-bit input/output port
Input or output can be specified for each bit
P70: I/O with programmable pull-up resister
P71 to P73: CMOS output/input with programmable pull-up
resister
•Other function
P70 INT0 input/HOLD release input/
Nch-Tr. output for wachdog timer
P71 INT1 input/HOLD release input
P72 INT2 input/Timer 0 event input
P73 INT3 input (noise rejection filter connected)/
Timer 0 event input
Interrupt receiver format, vector addresses
rising falling rising/ H level L level vector
falling
INT0
enable enable disable enable enable
03H
INT1
enable enable disable enable enable
0BH
INT2
enable enable enable disable disable
13H
INT3
enable enable enable disable disable 1BH
Option
Note: A capacitor of at least 10µF must be inserted between VDD and VSS when using this IC.
• Output form and existance of pull-up resistor for all ports can be specified for each bit.
• Programmable pull-up resistor is always connected regardless of port option, CMOS or N-ch open drain output in port 1.
• Port status in reset
Terminal
I/O
Port 0
Port 1
I
I
Pull-up resistor status at selecting CMOS output option
Pull-up resistor OFF, ON after reset release
Programmable pull-up resistor OFF
No.6844-8/19
LC863532A/28A/24A/20A/16A
1. Absolute Maximum Ratings at VSS=0V and Ta=25°C
Parameter
Symbol
Pins
Conditions
min.
-0.3
-0.3
Ratings
typ.
max.
+7.0
Supply voltage
Input voltage
VDDMAX
VI(1)
Output voltage
VO(1)
Input/output
voltage
High
Peak
level
output
output
current
current
Total
output
current
VIO
• RES , HS , VS ,
CVIN
R, G, B, BL,
FILT
•Ports 0, 1, 3, 7
IOPH(1)
•Ports 0, 1, 3, 7
IOPH(2)
R, G, B, BL
∑IOAH(1)
Ports 0, 1
∑IOAH(2)
Ports 3, 7
∑IOAH(3)
R, G, B, BL
IOPL(1)
IOPL(2)
IOPL(3)
∑IOAL(1)
Ports 0, 1, 3
Port 7
R, G, B, BL
Ports 0, 1
∑IOAL(2)
Ports 3, 7
∑IOAL(3)
R, G, B, BL
Maximum power
dissipation
Pdmax
MFP36S
DIP36S
Operating
temperature
range
Storage
temperature
range
Topg
-10
340
500
+70
Tstg
-55
+125
Low
level
output
current
Peak
output
current
Total
output
current
VDD
VDD[V]
•CMOS output
•For each pin.
•CMOS output
•For each pin.
The total of all
pins.
The total of all
pins.
The total of all
pins.
For each pin.
For each pin.
For each pin.
The total of all
pins.
The total of all
pins.
The total of all
pins.
Ta=-10 to +70°C
unit
V
VDD+0.3
-0.3
VDD+0.3
-0.3
VDD+0.3
mA
-4
-5
-20
-10
-12
20
15
5
40
20
12
mW
°C
No.6844-9/19
LC863532A/28A/24A/20A/16A
2. Recommended Operating Range at Ta=-10°C to +70°C, VSS=0V
Parameter
Symbol
Pins
VDD
Operating
supply voltage
range
VDD(1)
Hold voltage
VHD
VDD
High level
input voltage
VIH(1)
Port 0
VIH(2)
•Ports 1,3 (Schumitt)
•Port 7 (Schumitt)
port input/interrupt
• HS , VS , RES
(Schumitt)
Port 70
Watchdog timer input
Port 0
•Ports 1,3 (Schumitt)
•Port 7 (Schumitt)
port input/interrupt
• HS , VS , RES
(Schumitt)
Port 70
Watchdog timer input
VDD(2)
VIH(3)
Low level
input voltage
VIL(1)
VIL(2)
VIL(3)
Operation
cycle time
tCYC(1)
tCYC(2)
tCYC(3)
Oscillation
frequency
range
FmRC
Conditions
VDD[V]
min.
4.5
Ratings
typ.
max.
5.5
0.844µs ≤ tCYC
≤ 0.852µs
4µs ≤ tCYC ≤
400µs
RAMs and the
registers data are
kept in HOLD
mode.
Output disable
4.5 to 5.5 0.6VDD
VDD
Output disable
4.5 to 5.5 0.75VDD
VDD
Output disable
4.5 to 5.5 VDD-0.5
VDD
Output disable
Output disable
4.5 to 5.5
4.5 to 5.5
VSS
VSS
0.25VDD
Output disable
4.5 to 5.5
VSS
0.6VDD
•All functions
operating
•AD converter
operating
•OSD is not
operating
•OSD, AD
converter is not
operating
Internal RC
oscillation
4.5 to 5.5
0.844
4.5 to 5.5
0.844
30
4.5 to 5.5
0.844
400
4.5 to 5.5
0.4
4.5
5.5
2.0
5.5
unit
V
0.2VDD
0.848
0.8
0.852
3.0
µs
MHz
No.6844-10/19
LC863532A/28A/24A/20A/16A
3. Electrical Characteristics at Ta=-10°C to +70°C, VSS=0V
Parameter
High level
input current
Low level
input current
Symbol
IIH(1)
Ports 0, 1, 3, 7
IIH(2)
• RES
IIL(1)
• HS , VS
Ports 0, 1, 3, 7
IIL(2)
High level
output voltage
VOH(1)
VOH(2)
Low level
output voltage
Pull-up MOS
Tr. resistance
Bus terminal
short circuit
resistance
(SCL0-SCL1,
SDA0-SDA1)
Hysteresis
voltage
Pin
capacitance
Pins
VOL(1)
VOL(2)
VOL(3)
VOL(4)
Rpu
• RES
• HS , VS
•CMOS output of
ports 0,1,3,71-73
R, G, B, BL
Ports 0,1,3,71-73
Ports 0,3,71-73
•R, G, B, BL
•Port 1
Port 70
•Ports 0, 1, 3, 7
RBS
•P10-P12
•P11-P13
VHIS
•Ports 1, 3, 7
• RES
CP
• HS , VS
All pins
Conditions
•Output disable
•Pull-up MOS Tr.
OFF
•VIN=VDD
(including the offleak current of the
output Tr.)
•VIN=VDD
VDD[V]
4.5 to 5.5
min.
Ratings
typ.
4.5 to 5.5
unit
µA
1
•Output disable
•Pull-up MOS
Tr. OFF
•VIN=VSS
(including the offleak current of the
output Tr.)
VIN=VSS
4.5 to 5.5
-1
4.5 to 5.5
-1
IOH=-1.0mA
4.5 to 5.5
VDD-1
IOH=-0.1mA
R.G.B: digital mode
IOL=10mA
IOL=1.6mA
IOL=3.0mA
R.G.B: digital mode
IOL=1mA
VOH=0.9VDD
4.5 to 5.5 VDD-0.5
V
4.5 to 5.5
4.5 to 5.5
4.5 to 5.5
4.5 to 5.5
4.5 to 5.5
max.
1
1.5
0.4
0.4
13
38
4.5 to 5.5
0.4
80
kΩ
130
Ω
Output disable
4.5 to 5.5
0.1VDD
V
•f=1MHz
•Every other
terminals are
connected to VSS.
•Ta=25°C
4.5 to 5.5
10
pF
No.6844-11/19
LC863532A/28A/24A/20A/16A
4. IIC Input/Output Conditions at Ta=-10°C to +70°C, VSS=0V
Parameter
Symbol
SCL Frequency
BUS free time between stop - start
HOLD time of start, restart condition
L time of SCL
H time of SCL
Set-up time of restart condition
HOLD time of SDA
Set-up time of SDA
Rising time of SDA, SCL
Falling time of SDA, SCL
Set-up time of stop condition
(Note)
fSCL
tBUF
tHD;STA
tLOW
tHIGH
tSU;STA
tHD;DAT
tSU;DAT
tR
tF
tSU;STO
Standard
min.
max.
0
100
4.7
4.0
4.7
4.0
4.7
0
250
1000
300
4.0
-
High speed
min.
max.
0
400
1.3
0.6
1.3
0.6
0.6
0
0.9
100
20+0.1Cb
300
20+0.1Cb
300
0.6
-
unit
kHz
µs
µs
µs
µs
µs
µs
ns
ns
ns
µs
Refer to figure 7
Cb : Total capacitance of all BUS (unit : pF)
5. Pulse Input Conditions at Ta=-10°C to +70°C, VSS=0V
Parameter
Symbol
Pins
High/low level
pulse width
tPIH(1)
tPIL(1)
tPIH(2)
tPIL(2)
•INT0, INT1
•INT2/T0IN
INT3/T0IN
(1 tCYC is
selected for noise
rejection clock.)
INT3/T0IN
(16 tCYC is
selected for noise
rejection clock.)
INT3/T0IN
(64 tCYC is
selected for noise
rejection clock.)
•Interrupt acceptable
•Timer0-countable
•Interrupt acceptable
•Timer0-countable
tPIH(3)
tPIL(3)
tPIH(4)
tPIL(4)
VDD[V]
4.5 to 5.5
min.
1
4.5 to 5.5
2
•Interrupt acceptable
•Timer0-countable
4.5 to 5.5
32
•Interrupt acceptable
•Timer0-countable
4.5 to 5.5
128
RES
Reset acceptable
4.5 to 5.5
200
tPIH(6)
tPIL(6)
HS , VS
4.5 to 5.5
8
tTHL
tTLH
HS
•Display position
controllable (Note)
•The active edge of
HS and VS must
be apart at least
1 tCYC.
•Refer to figure 6.
Refer to figure 6.
tPIL(5)
Rising/falling
time
Conditions
4.5 to 5.5
Ratings
typ.
max.
unit
tCYC
µs
500
ns
No.6844-12/19
LC863532A/28A/24A/20A/16A
6. AD Converter Characteristics at Ta=-10°C to + 70°C, VSS=0V
Parameter
Symbol
Pins
Resolution
Absolute
precision
Conversion
time
N
ET
tCAD
Vref selection to
conversion finish
Analog input
voltage range
Analog port
input current
VAIN
AN4 - AN7
(Note)
Conditions
VDD[V]
4.5 to 5.5
min.
Ratings
typ.
6
±1
(Note)
IAINH
IAINL
max.
1 bit conversion time
= 2 × Tcyc
VAIN=VDD
VAIN=VSS
bit
LSB
µs
1.69
VSS
unit
VDD
V
1
µA
-1
Absolute precision does not include quantizing error (1/2LSB).
7. Analog Mode RGB Characteristics at Ta=-10°C to +70°C, VSS=0V
Parameter
Symbol
Pins
Analog output
voltage
R.G.B
Analog output mode
Time setting
R.G.B
Conditions
Low level output
Intensity output
Hi lebel output
70%
10pf load
VDD[V]
5.0
min.
0.45
0.90
1.35
Ratings
typ.
0.5
1.0
1.5
max.
0.55
1.10
1.65
50
unit
V
ns
No.6844-13/19
LC863532A/28A/24A/20A/16A
8. Sample Current Dissipation Characteristics at Ta=-10°C to +70°C, VSS=0V
The sample current dissipation characteristics is the measurement result of Sanyo provided evaluation board when the
recommended circuit parameters shown in the sample oscillation circuit characteristics are used externally. The currents
through the output transistors and the pull-up MOS transistors are ignored.
Parameter
Current dissipation
during basic
operation
(Note 3)
Current dissipation
in HALT mode
(Note 3)
Symbol
Pins
IDDOP(1)
VDD
IDDOP(2)
VDD
IDDOP(3)
VDD
IDDHALT(1) VDD
IDDHALT(2) VDD
IDDHALT(3) VDD
Current dissipation
in HOLD mode
(Note 3)
IDDHOLD
VDD
Conditions
•FmX’tal=32.768kHz
X’tal oscillation
•System clock :
VCO
•VCO for OSD
operating
•OSD is Digital mode
•Internal RC
oscillation stops
•FmX’tal=32.768kHz
X’tal oscillation
•System clock :
VCO
•VCO for OSD
operating
•OSD is Analog mode
•Internal RC
oscillation stops
•FmX’tal=32.768kHz
X’tal oscillation
•System clock :
X’tal
•VCO for system
VCO for OSD,
internal RC
oscillation stop
•Data slicer, AD
converters stop
•HALT mode
•FmX’tal=32.768kHz
X’tal oscillation
•System clock :
VCO
•VCO for OSD stops
•Internal RC
oscillation stops
•HALT mode
•FmX’tal=32.768kHz
X’tal oscillation
•VCO for system
stops
•VCO for OSD stops
•System clock :
Internal RC
•HALT mode
•FmX’tal=32.768kHz
X’tal oscillation
•VCO for system
stops
•VCO for OSD stops
•System clock : X’tal
•HOLD mode
•All oscillation stops.
Ratings
typ.
14
max.
25
4.5 to 5.5
23
37
4.5 to 5.5
100
300
µA
4.5 to 5.5
5
10
mA
4.5 to 5.5
360
1000
µA
4.5 to 5.5
40
200
4.5 to 5.5
0.05
20
VDD[V]
4.5 to 5.5
min.
unit
mA
µA
(Note 3) The currents through the output transistors and the pull-up MOS transistors are ignored.
No.6844-14/19
LC863532A/28A/24A/20A/16A
Recommended Oscillation Circuit and Sample Characteristics
The sample oscillation circuit characteristics in the table below is based on the following conditions:
• Recommended circuit parameters are verified by an oscillator manufacturer using a Sanyo provided oscillation evaluation
board.
• Sample characteristics are the result of the evaluation with the recommended circuit parameters connected externally.
Recommended oscillation circuit and sample characteristics (Ta = -10 to +70°C)
Notes
Frequency
Manufacturer
Oscillator
32.768kHz
Seiko Epson
C-002RX
Operating
supply voltage
range
Recommended circuit
parameters
C1
18pF
C2
18pF
Rf
open
Rd
390kΩ
4.5 to 5.5V
Oscillation
stabilizing
time
typ.
max
1.00S 1.50S
Notes
The oscillation stabilizing time period is the time until the VCO oscillation for the internal system becomes stable
after the following conditions. (Refer to Figure 2.)
1. The VDD becomes higher than the minimum operating voltage after the power is supplied.
2. The HOLD mode is released.
The sample oscillation circuit characteristics may differ applications.
manufacturer with the following notes in your mind.
For further assistance, please contact with oscillator
•
Since the oscillation frequency precision is affected by wiring capacity of the application board, etc., adjust the
oscillation frequency on the production board.
• The above oscillation frequency and the operating supply voltage range are based on the operating temperature of -10°C
to +70°C. For the use with the temperature outside of the range herein, or in the applications requiring high reliability
such as car products, please consult with oscillator manufacturer.
• When using the oscillator which is not shown in the sample oscillation circuit characteristics, please consult with Sanyo
sales personnel.
Since the oscillation circuit characteristics are affected by the noise or wiring capacity because the circuit is designed with low
gain in order to reduce the power dissipation, refer to the following notices.
• The distance between the clock I/O terminal (XT1 terminal XT2 terminal) and external parts should be as short as
possible.
• The capacitors’ VSS should be allocated close to the microcontroller’s GND terminal and be away from other GND.
• The signal lines with rapid state changes or with large current should be allocated away from the oscillation circuit.
XT1
XT2
Rf
Rd
C1
C2
X’tal
Figure 1
Recommended oscillation circuit.
No.6844-15/19
LC863532A/28A/24A/20A/16A
VDD
VDD limit
0V
Power supply
Reset time
RES
Internal RC
Resonator
Oscillation
XT1,XT2
tmsVCO
VCO for system
Operation mode
stable
Unfixed
Reset
Instruction execution mode
<Reset time and oscillation stabilizing time>
HOLD release signal
Valid
Internal RC
Resonator
Oscillation
XT1,XT2
tmsVCO
VCO for system
Operation mode
stable
HOLD
Instruction execution mode
<HOLD release signal and oscillation stabilizing time>
Figure 2
Oscillation stabilizing time
No.6844-16/19
LC863532A/28A/24A/20A/16A
tPIL (1)-(5)
Figure 3
tPIH (1)-(4)
Pulse input timing condition – 1
tPIL(6)
HS
0.75VDD
0.25VDD
tTLH
VS
tPIL(6)
more than ±1tCYC
Figure 4
Pulse input timing condition - 2
LC863532A
10kΩ
HS
HS
C536
Figure 5
Recommended Interface circuit
No.6844-17/19
LC863532A/28A/24A/20A/16A
100Ω
FILT
+
2.2µF
-
1MΩ
Figure 6
(Note)
P
33000pF
FILT recommended circuit
Place FILT parts on board as close to the microcontroller as possible.
S
Sr
P
SDA
tBUF
tHD;STA
tR
tF
tHD;STA
tsp
SCL
tLOW
tHIGH
tHD;DAT
S : start condition
P : stop condition
Sr : restart condition
tSU;DAT
tSU;STA
tsp : Spike suppression
Figure 7
I≈1mA
↓
I
tSU;STO
Standard mode : not exist
High speed mode : less than 50ns
IIC timing
↓
I
↓
PAD
R≈500Ω
Figure 8
R.G.B. analog output equivalent circuit
No.6844-18/19
LC863532A/28A/24A/20A/16A
memo :
PS No.6844-19/19