SANYO LV1115

Ordering number : EN8263A
Bi-CMOS IC
LV1115/M
Surround Processor ICs for
Electronic Volume Control
Overview
The LV1115/M are a sound processor ICs developed for use in TV sets.
They incorporate surround processing function (AViSS), pseudo stereo function, auto gain control, and the major
functional blocks of an electronic volume control IC.
Features
• Input gain control (-9dB, -6dB, 0dB, 4dB, 6dB: 5 positions)
• AViSS (ON/OFF/6-stage level control)
• Tone control (BASS: ±20dB, TREBLE: ±18dB [in 2dB steps])
• Master volume control (0dB to -14dB: 1dB steps/-14dB to -80dB: 2dB steps/-∞ = -82dB)
• Balance control
• Through mode/MUTE mode
• Pseudo stereo function (ON/OFF/MONO control)
• Auto gain control function
• I2C bus control
Specifications
Maximum Ratings at Ta = 25°C
Parameter
Symbol
Conditions
Maximum supply voltage
VCC max
Allowable power dissipation 1
Pd max1
Ta ≤ 70°C *, DIP
Allowable power dissipation 2
Pd max2
Ta ≤ 70°C *, MFP
Ratings
Unit
10.5
V
700
mW
450
mW
Operating temperature
Topr
-25 to +70
°C
Storage temperature
Tstg
-40 to +125
°C
Note *: Mounted on a specified board: 114.3mm×76.1mm×1.6mm, glass epoxy board
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
customer who is considering such use and/or outside the scope of our intended standard applications, please
consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our
customer shall be solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer' s products or
equipment.
11608 TI IM B8-8522, 8618 / 92706 / 31005 YY PC No.8263-1/15
LV1115/1115M
Operating Condtions at Ta = 25°C
Parameter
Recommended supply voltage
Symbol
Conditions
Ratings
Unit
VCC
9.0
V
Operating supply voltage 1
VCC opg1
DIP
8.0 to 10.0
V
Operating supply voltage 2
VCC opg2
MFP
8.0 to 9.0
V
Control data
“H” level voltage
VIH
2.0 to 3.3
V
“L” level voltage
VIL
0.0 to 1.0
V
μs
Pulse width
tφw
1.0
Hold time
thold
1.0
μs
Operating frequency
fopg
100
kHz
Electrical Characteristics at Ta = 25°C, VCC = 9.0V, fin = 1kHz, VIN = 300mVrms = 0dB, RL = 10kΩ
(Output=L/R-VROUT, VCA circuit though)
Parameter
Quiescent current
Symbol
Conditions
Ratings
min
ICCO
typ
Unit
max
50
mA
Total through (Total through mode, Volume control: 0dB)
Voltage gain
VGT
Maximum output voltage
VOT
Total harmonic distortion
THDT
DIN AUDIO
0.01
0.1
%
Output noise voltage
VNOT
DIN AUDIO
-94
-85
dBV
Cross talk
CTT
DIN AUDIO
THD=1%
-1.5
-0.5
2.00
2.45
80
+0.5
dB
Vrms
90
dB
Matrix through (Matrix mode, Volume control: 0dB)
Voltage gain
VGF
Maximum output voltage
VOM
THD=1%
-1.6
-0.6
1.50
1.85
Total harmonic distortion
THDM
DIN AUDIO
0.05
0.1
%
Output noise voltage
VNOM
DIN AUDIO
-92
-85
dBV
Cross talk
CTM
DIN AUDIO
Maximum output voltage
VOS
THD=1%
Total harmonic distortion
THDS
DIN AUDIO
0.05
0.5
%
Output noise voltage
VNOS
DIN AUDIO
-92
-85
dBV
80
+0.6
dB
Vrms
90
dB
MONO mode (MONO mode, Volume control: 0dB)
1.50
1.85
Vrms
Surround (Surround mode-A, Volume control: 0dB)
Maximum output voltage
VOS
THD=1%
Total harmonic distortion
THDS
DIN AUDIO
1.50
0.26
1.85
0.5
Vrms
%
Output noise voltage
VNOS
DIN AUDIO
-90
-80
dBV
Pseudo stereo (Pseudo mode, Volume control: 0dB)
Maximum output voltage
VOS
THD=1%
Total harmonic distortion
THDS
DIN AUDIO
1.50
0.06
1.85
0.5
Vrms
%
Output noise voltage
VNOS
DIN AUDIO
-92
-85
dBV
±17
±20
±23
dB
1.0
2.0
3.0
dB
±15
±18
±21
dB
1.0
2.0
3.0
dB
Bass band EQR (Matrix through mode, Volume control: 0dB)
Control range
GeqB
Step resolution
EstepB
Max. Boost/Cut
Treble band EQR (Matrix through mode, Volume control: 0dB)
Control range
GeqT
Step resolution
EstepT
Max. Boost/Cut
Note: The output wave form becomes big depending on the surround or tone control setting. Please make sure the
output waveform is not distorted. If the waveform is distorted, reduce the gain setting of surround, tone control, or
input signal level.
No.8263-2/15
LV1115/1115M
Package Dimensions
unit : mm (typ)
3067B
13
1
12
0.95
0.51min
3.3
(3.25)
0.9
3.9 max
0.25
6.4
24
7.62
21.0
(0.71)
0.48
1.78
SANYO : DIP24S(300mil)
Package Dimensions
unit : mm (typ)
3112B
12.5
0.63
7.6
13
5.4
24
1
12
1.0
0.15
0.35
1.7max
0.1
(1.5)
(0.75)
SANYO : MFP24S(300mil)
No.8263-3/15
tSU:STA
GND
DET OUT
tHD:STA
1
24
Lch-IN
tHIGH
tR
tLOW
tHD:DAT
tSU:DAT
Rch-IN
2
23
AVL
AVL
+
-
+
-
3
DC
R-DC1
ST-2
ST-1
LPFC
P Stereo
4
Stereo
5
6
R-TC1
Bypass
ANALOG
7
8
9
DC
TOTAL
Bypass
R-BC R-DC2
TONE CONT
R-BC
Bypass
SURROUND
Matrix
(AViSS)
DC
16
TOTAL
SURROUND
Matrix
17
L-BC L-DC2
TONE CONT
18
L-BC
SURROUND
19
L-TC1
Bypass
20
HPFC
P Stereo
21
Pseud
DC
22
L-DC1
L-VROUT
MUTE
MUTE
+
-
L-VROUT
10
15
+
-
VREF
DET
11
VCC
13
DATA
DATA
CONTROL
14
12
CONTROL
CLK
LV1115/1115M
Block Diagram
I2C BUS Control Signal
tF
SCL
tSU:STO
tBUF
SDA
Figure 1. I2C BUS Control Signal timing chart
No.8263-4/15
LV1115/1115M
I2C BUS register
1) The explanation of I2C Bus
I2C Bus (Inter IC Bus) is the bus system which the PHILIPS company developed.
It does controls such as the start, the stop by two control signals of SDA (Serial Data) and SCL (Serial Clock).
The output of each signal is open drain and forms out of wired OR.
S: Start condition
P: Stop condition
ACK: Acknowledge
Data is transmitted in the MSB first.
1 unit is composed of 8 bits and ACK is put back from the slave to confirm.
Slave IC reads data with rising edge of SCL.
Master IC changes data by falling edge in SCL.
2) The control register
Table1 Slave Address
MSB
LSB
1
1
1
0
1
1
1
0
Note; LV1115/M are reception exclusive use. It depends and it uses LSB by the "0" fixation.
Table2 I2C Bus transmission
Sub Address
Function
Data
BINARY
HEX
D7
D6
Input Gain/AVL (On-Off) control
0000 0001
01
0
0
D5
D4
D3
D2
D1
Volume control
0000 0010
02
Channel
AVL detection level/Surround/MODE control
0000 0011
03
Tone control [Bass]
0000 0100
04
0
0
0
Bass
Tone control [TREBLE]
0000 0101
05
0
0
0
TREBLE
AVL CONTROL
0000 0110
06
0
0
0
Gain
D0
AVL MODE
Volume
AVL DET LEVEL
Surround
0
0
MODE
AVL SLOPE
Table3 AVL MODE
Sub Address
A7
D7
D6
D5
D4
D3
D2
D1
Mute
0
0
*
*
*
0
0
0
AVL ON
0
0
*
*
*
0
0
1
0
AVL OFF
0
A6
0
A5
0
A4
0
A3
Data
0
A2
0
A1
0
A0
1
D0
0
0
*
*
*
0
1
Mute
0
0
*
*
*
0
1
1
Mute
0
0
*
*
*
1
0
0
No.8263-5/15
LV1115/1115M
Table4 Gain control
Sub Address
A7
A6
D7
D6
D5
D4
D3
D2
D1
D0
-9dB
0
0
0
1
1
*
*
*
-6dB
0
0
0
1
0
*
*
*
0
0dB
A5
0
A4
Data
0
A3
0
A2
0
A1
0
A0
0
1
0
0
0
0
0
*
*
*
+4dB
0
0
1
1
0
*
*
*
+6dB
0
0
1
1
1
*
*
*
D7
D6
D5
D4
D3
D2
D1
D0
Bypass (Total)
*
*
*
*
*
*
0
0
Matrix
*
*
*
*
*
*
0
1
*
*
*
*
*
*
1
0
*
*
*
*
*
*
1
1
D0
Table5 Mode control
Sub Address
A7
A6
0
Mono
A5
0
A4
0
Data
A3
0
A2
0
A1
0
A0
1
1
Pseudo Stereo
Table6 Surround control
Sub Address
A7
D7
D6
D5
D4
D3
D2
D1
OFF
*
*
*
0
0
0
*
*
MODE-C
*
*
*
0
1
1
*
*
MODE-B
*
*
*
0
1
0
*
*
*
*
*
*
*
*
*
MODE-A
A6
0
A5
0
A4
Data
0
A3
0
A2
0
A1
0
A0
1
1
0
0
1
MODE-F
1
1
1
MODE-E
1
1
0
1
0
1
MODE-D
*
*
*
Note: At the time of forced mono mode, there is not Surround effect.
Note: Output gain = Step1 < Step7
Note: The output wave form becomes big depending on the surround or tone control setting. Please make sure the
output waveform is not distorted. If the waveform is distorted, reduce the gain setting of surround, tone control, or
input signal level.
Table7 AVL DETECTION LEVEL
Sub Address
A7
A6
A5
A4
A3
Data
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
OFF
0
0
0
*
*
*
*
*
100mV
0
0
1
*
*
*
*
*
200mV
0
1
0
*
*
*
*
*
0
1
1
*
*
*
*
*
1
0
0
*
*
*
*
*
500mV
1
0
1
*
*
*
*
*
600mV
1
1
0
*
*
*
*
*
700mV
1
1
1
*
*
*
*
*
D7
D6
D5
D4
D3
D2
D1
D0
LEVEL1
0
0
0
0
0
0
0
0
LEVEL2
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
LEVEL5
0
0
0
0
0
1
0
0
LEVEL6
0
0
0
0
0
1
0
1
300mV
400mV
0
0
0
0
0
0
1
1
Table8 AVL SLOPE
Sub Address
A7
LEVEL3
LEVEL4
0
A6
0
A5
0
A4
0
A3
0
Data
A2
1
A1
1
A0
0
No.8263-6/15
LV1115/1115M
Table9 Tone control [Bass control]
Sub Address
A7
D7
D6
D5
D4
D3
D2
D1
D0
+20dB
0
0
0
0
1
0
1
0
+18dB
0
0
0
0
1
0
0
1
+16dB
0
0
0
0
1
0
0
0
+14dB
0
0
0
0
0
1
1
1
+12dB
0
0
0
0
0
1
1
0
+10dB
0
0
0
0
0
1
0
1
+8dB
0
0
0
0
0
1
0
0
+6dB
0
0
0
0
0
0
1
1
+4dB
0
0
0
0
0
0
1
0
+2dB
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
-2dB
0
0
0
1
0
0
0
1
-4dB
0
0
0
1
0
0
1
0
-6dB
0
0
0
1
0
0
1
1
-8dB
0
0
0
1
0
1
0
0
-10dB
0
0
0
1
0
1
0
1
-12dB
0
0
0
1
0
1
1
0
-14dB
0
0
0
1
0
1
1
1
-16dB
0
0
0
1
1
0
0
0
-18dB
0
0
0
1
1
0
0
1
-20dB
0
0
0
1
1
0
1
0
0dB
0
A6
0
A5
0
A4
0
A3
Data
0
A2
1
A1
0
A0
0
Note: The output wave form becomes big depending on the surround or tone control setting. Please make sure the
output waveform is not distorted. If the waveform is distorted, reduce the gain setting of surround, tone control, or
input signal level.
Table10 Tone control [TREBLE control]
Sub Address
A7
D7
D6
D5
D4
D3
D2
D1
D0
+18dB
0
0
0
0
1
0
0
1
+16dB
0
0
0
0
1
0
0
0
+14dB
0
0
0
0
0
1
1
1
+12dB
0
0
0
0
0
1
1
0
+10dB
0
0
0
0
0
1
0
1
+8dB
0
0
0
0
0
1
0
0
+6dB
0
0
0
0
0
0
1
1
+4dB
0
0
0
0
0
0
1
0
+2dB
0
0
0
0
0
0
0
1
0dB
0
A6
0
A5
0
A4
0
A3
Data
0
A2
1
A1
0
A0
1
0
0
0
0
0
0
0
0
-2dB
0
0
0
1
0
0
0
1
-4dB
0
0
0
1
0
0
1
0
-6dB
0
0
0
1
0
0
1
1
-8dB
0
0
0
1
0
1
0
0
-10dB
0
0
0
1
0
1
0
1
-12dB
0
0
0
1
0
1
1
0
-14dB
0
0
0
1
0
1
1
1
-16dB
0
0
0
1
1
0
0
0
-18dB
0
0
0
1
1
0
0
1
Note: The output wave form becomes big depending on the surround or tone control setting. Please make sure the
output waveform is not distorted. If the waveform is distorted, reduce the gain setting of surround, tone control,
or input signal level.
No.8263-7/15
LV1115/1115M
Table11 Volume control
Sub Address
A7
D7
D6
D5
D4
D3
D2
D1
0dB
*
*
0
0
0
0
0
0
-1dB
*
*
0
0
0
0
0
1
-2dB
*
*
0
0
0
0
1
0
-3dB
*
*
0
0
0
0
1
1
-4dB
*
*
0
0
0
1
0
0
-5dB
*
*
0
0
0
1
0
1
-6dB
*
*
0
0
0
1
1
0
-7dB
*
*
0
0
0
1
1
1
-8dB
*
*
0
0
1
0
0
0
-9dB
*
*
0
0
1
0
0
1
-10dB
*
*
0
0
1
0
1
0
-11dB
*
*
0
0
1
0
1
1
-12dB
*
*
0
0
1
1
0
0
-13dB
*
*
0
0
1
1
0
1
-14dB
*
*
0
0
1
1
1
0
-16dB
*
*
0
0
1
1
1
1
-18dB
*
*
0
1
0
0
0
0
-20dB
*
*
0
1
0
0
0
1
-22dB
*
*
0
1
0
0
1
0
-24dB
*
*
0
1
0
0
1
1
-26dB
*
*
0
1
0
1
0
0
-28dB
*
*
0
1
0
1
0
1
-30dB
*
*
0
1
0
1
1
0
-32dB
*
*
0
1
0
1
1
1
-34dB
0
A6
0
A5
0
A4
0
A3
Data
0
A2
0
A1
1
A0
0
D0
*
*
0
1
1
0
0
0
-36dB
*
*
0
1
1
0
0
1
-38dB
*
*
0
1
1
0
1
0
-40dB
*
*
0
1
1
0
1
1
-42dB
*
*
0
1
1
1
0
0
-44dB
*
*
0
1
1
1
0
1
-46dB
*
*
0
1
1
1
1
0
-48dB
*
*
0
1
1
1
1
1
-50dB
*
*
1
0
0
0
0
0
-52dB
*
*
1
0
0
0
0
1
-54dB
*
*
1
0
0
0
1
0
-56dB
*
*
1
0
0
0
1
1
-58dB
*
*
1
0
0
1
0
0
-60dB
*
*
1
0
0
1
0
1
-62dB
*
*
1
0
0
1
1
0
-64dB
*
*
1
0
0
1
1
1
-66dB
*
*
1
0
1
0
0
0
-68dB
*
*
1
0
1
0
0
1
-70dB
*
*
1
0
1
0
1
0
-72dB
*
*
1
0
1
0
1
1
-74dB
*
*
1
0
1
1
0
0
-76dB
*
*
1
0
1
1
0
1
-78dB
*
*
1
0
1
1
1
0
-80dB
*
*
1
0
1
1
1
1
-∞dB
*
*
1
1
0
0
0
0
No.8263-8/15
LV1115/1115M
Table12 Volume channel control
Sub Address
A7
A6
A5
A4
A3
Data
A2
A1
A0
L-ch
0
R-ch
0
0
0
0
0
1
L/R
0
D7
D6
D5
D4
D3
D2
D1
0
1
*
*
*
*
*
D0
*
1
0
*
*
*
*
*
*
1
1
*
*
*
*
*
*
Pin Functions
Pin No
Function
Voltage
1
GND
0
2
INPUT-R
VREF
Internal equivalent circuit
Remarks
Input Impedance
ri=25kΩ
23
INPUT-L
3
DC1 Cut(R)
VREF
DC offset cancellation capacitor
connection pin
9
DC2 Cut(R)
16
DC2 Cut(L)
22
DC1 Cut(L)
4
ST-1
VREF
Pseudo stereo phase shift capacitor
connection pin
21
ST-2
5
AViSS LPF
4
21
VREF
Capacitor connection pin for surround low
pass filter
6
TREBLE(R)
VREF
Capacitor connection pin for configuring
treble filter
19
TREBLE(L)
7
BASS-1(R)
VREF
Bass band filter configuration capacitor
and resistor connection pins
8
BASS-1(L)
17
BASS-2(R)
18
BASS-2(L)
Continued on next page.
No.8263-9/15
LV1115/1115M
Continued from preceding page.
Pin No
10
Function
EVR-OUT(R)
Voltage
VREF
Internal equivalent circuit
Remarks
Output Impedance
ro=500Ω
10
15
15
EVR-OUT(L)
11
VREF
12
VCC
VCC
13
I2C-DATA
0/Hi-Z
0.5 VCC
Reference voltage
I2C control data input
13
14
I2C-CLK
0/Hi-Z
20
AViSS HPF
VREF
I2C control data input
20
24
DET-OUT
4.5V
AVL DET OUT
No.8263-10/15
LV1115/1115M
Treble / Bass Band Block Equivalent Circuit Diagram
From L-Input Block
SW3
+
-
SW3
+
-
SW2
To L-OUT Block
SW2
SW1
SW4
SW1
SW4
0dB
±2dB
R1=10.633kΩ
±4dB
R2=8.446kΩ
±6dB
R3=6.709kΩ
±8dB
R4=5.329kΩ
±10dB
R5=4.233kΩ
±12dB
R6=3.363kΩ
±14dB
R7=2.671kΩ
±16dB
R8=2.122kΩ
±18dB
R9=1.665kΩ
0dB
Total=51.7kΩ
R10=6.510kΩ
±2dB
R1=15.220kΩ
±4dB
R2=12.089kΩ
±6dB
R3=9.603kΩ
±8dB
R4=7.628kΩ
±10dB
R5=6.059kΩ
±12dB
R6=4.813kΩ
±14dB
R7=3.823kΩ
±16dB
R8=3.037kΩ
±18dB
R9=2.412kΩ
±20dB
R10=1.916kΩ
R12=100Ω
L-TC1
L-BC2
Total=66.7kΩ
R11=100Ω
L-BC1
During boost, SW1 and SW3 are ON, during cut, SW2 and SW4 are ON, when 0dB, 0dBSW and SW2 and SW3 are ON.
Tone Circuit Constant Calculation Examples
Treble Band Circuit: The shelving characteristics can be obtained for the treble band.
The equivalent circuit and calculation formula during boost are indicated below.
• Calculation example 1: Specification
Set frequency: f = 24000Hz
Gain during maximum boost: G+18dB = 17.5dB
Let us use R1 = 6.51kΩ and R2 = 45.19kΩ
The above constants are inserted in the following formula
R2
R1
C
R2
G = 20 × Log10 1+
+
-
R12+(1/ ω C)2
1
C=
2πf
2
R2
10G/20-1
-R12
1
=
2π24000
45190
7.50 - 1
2
- 65102
≈2700 (pF)
No.8263-11/15
LV1115/1115M
Bass Band Circuit: The equivalent circuit and the formula for calculating the external RC with a mean frequency of
100Hz are shown below.
• Calculation example 1: specification
Mean frequency: f0 = 100Hz
Gain during maximum boost: G+20dB = 20dB
Let us use R1 = 0kΩ and R2 = 66.7kΩ, and C1 = C2 = C.
+
R1
R2
We obtain R2 from G = 20dB
C1
R2
G = 20 × Log10 1+
R3 =
R3
2R3
R2
2 (10
C2
G+20dB/20
- 1)
66700
2 (10 - 1)
=
≈3.6kΩ
We obtain C from mean frequency f0 = 100Hz
f0 =
C=
2π
1
(R3R2C1C2)
1
2πf0
R3R2
=
2π × 100
1
66700 × 3600
≈0.1μF
We obtain Q
Q=
R3R2
2R3
1
R3R2
×
≈2.15
Note item when using
(1) When turning on the power, the setting inside is unsettled. Before setting control data, it does a mute.
(2) To prevent the digital noise of the high frequency influence a terminal (SCL, SDA).
It can be protected by a signal line in the ground pattern or by the shielding cable.
(3) To prevent the noise in changing a mode, please set the mute ON.
Sample Application Circuit
1 F
47 F
1 F
4.7 F
0.1 F
47 F
4.7 F
0.1 F
3.6k
0.1 F
2700pF
0.1 F
2700pF
0.01 F
3.6k
0.1 F
4.7 F
5600pF
4.7 F
1 F
0.068 F
1 F
1 F
No.8263-12/15
LV1115/1115M
Volume control Characteristics
[Vcc = 9.0V / fin = 1kHz / Vin = 0dBV / Total Mode]
Gain control Characteristics
[Vcc = 9.0V / fin = 1kHz / Vin = -10dBV / Matrix Mode]
-30
Vout (dB)
Vout (dB)
-10
-50
-70
-90
-90
-80
-70
-60
-50
-40
-30
-20
-10
10
8
6
4
2
0
-2
-4
-6
-8
-10
0
-10 -9 -8 -7 -6 -5 -4 -3 -2 -1
Volume setting (dB)
1
2
3
4
5
6
Treble Band Freq. Characteristics
(Vcc=9.0V / Vin=-20dBV / C=2700pF)
0
0
-5
-5
-10
-10
-15
Vout (dBV)
Vout (dBV)
Bass Band Freq. Characteristics
(Vcc=9.0V / Vin=-20dBV / C=0.1μF / R=3.6kΩ)
-20
-25
-30
-15
-20
-25
-35
-30
-40
-35
-45
-40
10
100
1000
10000
10
100
1000
fin (Hz)
10000
100000
fin (Hz)
Surround Mode Freq. Characteristics
(Vcc=9.0V / Vin=-10dBV)
Pseudo mode Lch - Rch Phase Characteristics
[Vcc = 9.0V / Vin = -10dBV]
360
5
Mode-B
Mode-C
-5
Mode-D
Mode-E
-10
Phase (Deg.)
Mode-A
0
Vout (dBV)
0
Gain setting (dB)
Mode-F
270
180
90
0
-15
10
100
1000
10
10000
100
1000
10000
fin (Hz)
fin (Hz)
AVL Function Characteristics
[Vcc=9.0V, fin=1kHz, Det.level = 100mV setting]
AVL Function Characteristics
[Vcc=9.0V, fin=1kHz, Det.level = 700mV setting]
400
Level 2
Level 3
200
Level 4
Level 5
100
Level 1
Vout (mVrms)
Vout (mVrms)
1100
Level 1
300
Level 2
Level 3
Level 4
800
Level 5
Level 6
0
Level 6
500
0
400
800
1200
Vin (mVrms)
1600
2000
0
400
800
1200
1600
2000
Vin (mVrms)
No.8263-13/15
LV1115/1115M
AVL Function Characteristics
[Vcc=9.0V, fin=1kHz, Slope.level = 1]
AVL Function Characteristics
[Vcc=9.0V, fin=1kHz, Slope.level = 6]
800
Det.100
600
Det.200
500
Det.300
400
Det.400
300
Det.500
200
Det.600
Vout (mVrms)
Vout (mVrms)
700
Det.700
100
0
0
400
800
1200
1600
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
Det.100
Det.200
Det.300
Det.400
Det.500
Det.600
Det.700
2000
0
400
800
Vin (mVrms)
Vin - THD Characteristics
(Vcc=9.0V, fin=1kHz, [VR / Bass / Treble setting=0dB])
2000
10
1
Total
0.1
Matrix
THD (%)
THD (%)
1600
Vcc - THD Characteristics
(fin=1kHz, Vin=-10dBV, [VR / Bass / Treble setting=0dB])
1
Mono
Pseudo
0.01
Pseudo Surround
Total
Matrix
0.1
Mono
Pseudo
Pseudo Surround
0.01
0.001
0.001
-40 -35 -30 -25 -20 -15 -10 -5
0
5
8
8.5
9
Vin (dBV)
9.5
10
10.5
Vcc (V)
fin - THD Characteristics
(Vcc=9.0V, Vin=-10dBV, [VR / Bass / Treble setting=0dB])
Vcc - Vomax Characteristics
(fin=1kHz, [VR / Bass / Treble setting=0dB / Surround mode=A])
10
3.0
1
Total
Matrix
0.1
THD (%)
THD (%)
1200
Vin (mVrms)
Mono
Pseudo
Pseudo Surround
0.01
0.001
100
Total
2.5
Matrix
Mono
Pseudo
2.0
Pseudo Surround
1.5
1000
10000
8
8.5
9
fin (Hz)
9.5
10
10.5
fin (Hz)
AVL Function THD Characteristics
[Vcc=9.0V, fin=1kHz, Slope.level = 1]
AVL Function THD Characteristics
[Vcc=9.0V, fin=1kHz, Slope.level = 6]
10
10
Det.100
Det.200
1
Det.300
Det.400
Det.500
0.1
Det.600
THD (%)
THD (%)
Det.100
Det.200
1
Det.300
Det.400
Det.500
0.1
Det.600
Det.700
0.01
Det.700
0.01
0
400
800
1200
Vin (mVrms)
1600
2000
0
400
800
1200
1600
2000
Vin (mVrms)
No.8263-14/15
LV1115/1115M
VCC - ICCO Characteristics
VCC - VREF Reg. Characteristics
60.0
5.5
VREF (V)
ICCO (mA)
5.0
55.0
50.0
4.5
4.0
3.5
45.0
8.0
8.5
9.0
9.5
Vcc (V)
10.0
10.5
8.0
8.5
9.0
9.5
10.0
10.5
Vcc (V)
SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using
products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd.
products described or contained herein.
SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all
semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or
malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise
to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt
safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not
limited to protective circuits and error prevention circuits for safe design, redundant design, and structural
design.
In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are
controlled under any of applicable local export control laws and regulations, such products may require the
export license from the authorities concerned in accordance with the above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise,
without the prior written consent of SANYO Semiconductor Co.,Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the
SANYO Semiconductor Co.,Ltd. product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed
for volume production.
Upon using the technical information or products described herein, neither warranty nor license shall be granted
with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third
party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's
intellectual property rights which has resulted from the use of the technical information and products mentioned
above.
This catalog provides information as of January, 2008. Specifications and information herein are subject
to change without notice.
PS No.8263-15/15