Ordering number : ENA1512 Bi-CMOS LSI LV5652T 3-channel Switching Regulator Controller Overview The LV5652T is a 3-channel switching regulator controller. Features • Low-voltage (3V) operation • Reference voltage precision : ±1% • Independent standby functions for each of three channels. • Is capable of driving MOS transistors. • switching regulator controller : 3-channel ch1 : Supports synchronous rectification ch2 : Supports inverting step-up operation ch3 : Supports step-up operation Specifications Maximum Ratings at Ta = 25°C Parameter Symbol Conditions Ratings Unit Maximum supply voltage 1 VCC max VCC pin -0.3 to 16 Maximum supply voltage 2 VBIAS max VBIAS pin -0.3 to 18 V V Maximum clock input voltage VCLKIN max CLKIN pin 5.5 V Allowable power dissipation Pd max Mounted on a specified board* 1 W Operating temperature Topr -30 to +85 °C Storage temperature Tstg -55 to +125 °C * Specified board: 114.3mm × 76.1mm × 1.6mm, glass epoxy board. Recommended Operating Conditions at Ta = 25°C Parameter Symbol Conditions Ratings Unit Supply voltage 1 VCC VCC pin 3 to 15 V Supply voltage 2 VBIAS VBIAS pin 3 to 15 V Clock input voltage VCLKIN CLKIN pin Timing resistor RT 7 to 30 Timing capacitor CT 100 to 1000 Triangle wave frequency fOSC 5 0.1 to 1.3 V kΩ pF MHz Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. 80509 SY 20080922-S00001 No.A1512-1/9 LV5652T Electrical Characteristics at Ta = 25°C, VCC = VBIAS = 3.6V, SCP = 0V Parameter Symbol Conditions Ratings min typ Unit max Error amplifier 1 IN+ pin internal bias voltage VB Value added to the error amplifier offset at Output low voltage ch1 to ch3 VLow FB the error amplifier + side voltage IN- = 2.0V, IFB = 20μA Output high voltage ch1 to ch3 VHi FB IN- = 0V, IFB1 = -20μA 0.504 0.51 0.516 0.2 2.0 V V V Error amplifier 2 IN2-RE pin offset voltage VOFF2 Output low voltage VLow FB2RE IN2-RE = 2.0V, IFB = 20μA Output high voltage VHi FB2RE IN2-RE = -10V, IFB1 = -500μA -6 6 V 0.2 V 2.0 V Protection circuit Threshold voltage VSCP SCP pin current ISCP 1.1 Short circuit detection signal pin VSCPOUT Open collector, ISCPOUT = 100μA CSOFT = 0V 1.25 1.4 V μA 4 0.2 V Software start block 3.2 4 4.8 μA 160 200 240 kΩ Soft start current ch1 to ch3 ISF Soft start resistance ch1 to ch3 RSF ch1 Duty MAX 1 Out monitor , IN- = 0V 100 80 85 90 % 80 85 90 % Fixed duty Maximum on duty 1 % Maximum on duty 2 ch2 Duty MAX 2 Out monitor , IN- = 0V Maximum on duty 3 ch3 Duty MAX 3 Out monitor , IN- = 0V OUT pin high side on resistance ROUT SOUR IO = 10mA 28 50 Ω OUT pin low side on resistance ROUT SINK IO = 10mA 18 35 Ω Current setting pin voltage VT RT RT = 10kΩ 0.57 Output current IOH CT Output current ratio ∆IO CT CT pin, rise/fall Oscillation frequency fOSC RT = 10kΩ , CT = 270pF Output block Triangle wave oscillator block V μA 190 2 2.5 3 390 510 620 kHz - 10 mV Reference voltage block Reference voltage VREF Line regulation VLN REF 1.240 VCC = 3V to 15V V Control circuit On state voltage VON CTL OFF state voltage VOFF CTL 2.0 0.6 V V Pin input current IIN CTL 60 μA Standby circuit On voltage VON STBY OFF voltage VOFF STBY 2.0 0.6 V V Pin input current IIN STBY 60 μA 5 mA 1 μA All circuits VCC current consumption ICC IN1- to IN3- = 1V Standby mode current consumption IOFF VSTBY = VCTL = 0V, IOFF = ICC + IBIAS 4 No.A1512-2/9 LV5652T Package Dimensions Allowable power dissipation, Pd max --W unit : mm (typ) 3253B 9.75 0.5 5.6 7.6 19 36 1 0.18 18 0.15 Specified board: 114.3×76.1×1.6mm3 glass epoxy board. 1.0 0.8 0.6 0.4 0.2 0 -30 -20 0.08 (1.0) (0.63) 1.2max (0.5) Pd max -- Ta 0 20 40 60 Ambient temperature, Ta -- °C 80 100 SANYO : TSSOP36(275mil) Pin Assignment VBIAS 1 36 ( NC ) OUT2 2 35 ( NC ) OUT3 3 34 GND_P(VS) SCPOUT 4 33 OUT1 CLKIN 5 32 OUT1N STBY3 6 31 CSOFT1 STBY2 7 30 ( NC ) 29 CSOFT2 ( NC ) 8 SCP 10 CTL 11 LV5652T STBY1 9 28 CSOFT3 27 VCC 26 IN1- IN3- 12 25 FB1 FB3 13 24 ( NC ) IN2+RE 14 23 ( NC ) IN2-RE 15 22 VREF FB2RE 16 21 CT FB2 17 20 RT IN2- 18 19 GND_S Top view No.A1512-3/9 LV5652T Block Diagram and Sample Application Circuit VREF VREF SCP SCP SCP_OUT Signal system power supply VCC Pre-output stage VBIAS power supply FB1A + + + - IN1FB1 FB1A OUT1 Step-down (DOWN) OUT1N CSOFT1 Vo1 3.3V/100mA FB2A IN2-RE IN2+RE FB2RE IN2- + + + + - FB2 FB2A OUT2 Inversion (INVERT) Vo2 -4V/100mA CSOFT2 FB3A FB3A IN3FB3 + - + + - Step-up (UP) OUT3 Vo3 6V/100mA ON/OFF Setting CSOFT3 GND_P(VS) GND_S STBY1 STBY2 STBY3 CLKIN STBY OSC (Stand by) (Oscillation circuit) CTL CT RT The CLKIN pin must be connected to GND,when the external clock synchronization (CLKIN) is not used. No.A1512-4/9 LV5652T Pin Function Block Pin No. Pin Name Functions ch1 9 STBY1 Standby input. H/ch1 ; ON, L/ch1 ; OFF. (Step-down) 26 IN1- Error amplifier Inverting input. 25 FB1 Error amplifier output. 31 CSOFT1 Soft start setting capacitor connection. Connect to GND through a capacitor. 33 OUT1 Output. External transistor P-channel gate connection. 32 OUT1N Output. External transistor N-channel gate connection. ch2 7 STBY2 Standby input. H/ch2 ; ON, L/ch2 ; OFF. (Inversion) 14 IN2+RE Inversion amplifier, +(noninverting) input. 15 IN2-RE Inversion amplifier, -(Inverting) input. 16 FB2RE Inversion amplifier output. 18 IN2- Error amplifier, - (Inverting) input. 17 FB2 Error amplifier output. 29 CSOFT2 Soft start setting capacitor connection. Connect to GND through a capacitor. 2 OUT2 Output. External transistor P-channel gate connect. ch3 6 STBY3 Standby input. H/ch3 ; ON, L/ch3 ; OFF. (Step-up) 12 IN3- Error amplifier, - (Inverting) input. 13 FB3 Error amplifier output. 28 CSOFT3 Soft start setting capacitor connection. Connect to GND through a capacitor. 3 OUT3 Output. External transistor N-channel gate connect. 27 VCC Power supply input (signal system). 1 VBIAS Power supply input (pre-output stage). 19 GND_S Ground (signal system). 34 GND_P (VS) Ground (pre-output stage). 22 VREF Reference voltage output. 11 CTL Output control. 10 SCP Connection pin for the delay time setting capacitor of short circuit detection circuit. 4 SCPOUT SCP_OUT pin (SCP output). 21 CT Triangle wave oscillation frequency setting capacitor connection. 20 RT Triangle wave oscillation frequency setting resistor connection. POWER CONTROL OSC OTHER 5 CLKIN External clock input. 8 ( NC ) Not use. 23 ( NC ) Not use. 24 ( NC ) Not use. 30 ( NC ) Not use. 35 ( NC ) Not use. 36 ( NC ) Not use. No.A1512-5/9 LV5652T Equivalent Circuits Pin No. Pin Name 11 CTL 9 STBY1 7 STBY2 6 STBY3 Description Equivalent Circuit CTL : Controls operation of all circuits. CTL/STBY* STBY* : Independently controls operation of the corresponding channel. Operation is high active. High : ON Low : OFF GND_S 18 IN1IN2- 12 IN3- 26 Error amplifier inverting input. VREG (Internal constant voltage) The regulator output is divided by a resistor and connected to IN*- IN*- 500Ω 5kΩ 5kΩ GND_S 25 FB1 Error amplifier output. 17 FB2 These pins, in combination with IN*-, 13 FB3 configure the error amplifier filters VREG (Internal constant voltage) 20Ω FB* 500Ω GND_S 14 15 IN2+RE IN2-RE Inversion step-up (Channel2) error VREG (Internal constant voltage) amplifier input. These pins, in combination with FB2RE,configure the operational amplifier (independent) IN2-RE IN2+RE GND_S 16 FB2RE Inversion step-up (Channel2) error VREG (Internal constant voltage) amplifier output. This pin, in combination with IN2+RE and IN2-RE, configures the operational amplifier (independent) FR2RE GND_S Continued on next page. No.A1512-6/9 LV5652T Continued from preceding page. Pin No. Pin Name 31 CSOFT1 Soft start. Description 29 CSOFT2 Connect to GND via a capacitor to set the 28 CSOFT3 soft start time. Equivalent Circuit VREG (Internal constant voltage) 500Ω CSOFT* 10kΩ 200kΩ GND_S 33 OUT1 Output. 2 OUT2 Connect external PchFET. 3 OUT3 VBIAS OUT* GND_P (VS) 32 OUT1N Output. VBIAS Connect external NchFET. VOUT1N GND_P (VS) 20 RT Connect to GND through a resistor. VREG (Internal constant voltage) This pin, together eith CT, sets the oscillation frequency. RT GND_S 21 CT Connect to GND through a capacitor. VREG (Internal constant voltage) This pin, together eith RT, sets the oscillation frequency. CT GND_S 4 SCP_OUT Short circuit detection circuit output. VREG (Internal constant voltage) When SCP exceeds the threshold voltage, the open collector goes OFF and this pin goes High. SCP_OUT GND_S Continued on next page. No.A1512-7/9 LV5652T Continued from preceding page. Pin No. Pin Name Description 10 SCP Connect to GND via a capacitor to set the Equivalent Circuit VREG (Internal constant voltage) short circuit detection circuit delay time. 1.5kΩ SCP 13kΩ GND_S 22 VREF Internal constant voltage circuit output. VREG (Internal constant voltage) Connect a stabilizing capacitor. VREF 14.8kΩ GND_S 5 CLKIN External clock input. VREG (Internal constant voltage) Apply an external clock of the internal oscillation frequency or higher. CLKIN GND_S 27 VCC 1 VBIAS Signal system power supply Power system power supply (Output stage) 19 GND_S 34 GND_P (VS1) Signal system GND Output stage GND (pre-stage) 8 ( NC ) Use prohibited. 23 ( NC ) (Not connect pins.) 24 ( NC ) 30 ( NC ) 35 ( NC ) 36 ( NC ) VCC VBIAS GND_S GND_P (VS) ( NC ) No.A1512-8/9 LV5652T Notes (1) Soft start time setting method The soft start time is set with the capacitor connected between CSOFT* and GND_S. This IC has an independent soft start function for each channel, so a capacitor must be connected for each CSOFT to set the soft start time. (Description of soft start operation) (Outline of soft start pin) VREG (Internal constant voltage) CSOFT* [V] CSOFT* voltage VB (=0.515 [V] (TYP)) 4μA (ISF) CSOFT* 200kΩ (RSF) GND_S T [s] Soft start time (Tsoft [s]) CSOFT pin charging starts The output voltage reaches the set voltage (Output voltage constant) VB (0.515[V]) TSOFT = CSOFT × RSFIn ( VB ) RSF × ISF = 0.206 × 106 × CSOFT [s] (2) Setting the oscillation frequency The internal oscillation frequency is set by the resistor connected to the RT pin and the capacitor connected to the CT pin. The waveform generated on CT is a triangular wave with the charging/discharging waveform determined by RT and CT. 1 fOSC = 1.32 Х CT Х RT [Hz] The actual internal oscillation frequency deviates from the calculated value due to overshoot, undershoot and other factors, so the frequency should be confirmed in an actual set. (3) External input CLK function (CLK_IN) Switching operation can be synchronized with external clock input (CLK_IN) by using the CLK_IN pin. • External clock (CLK_IN) frequency and input level When using external clock (CLK_IN) input, input a frequency equal to the internal oscillation frequency +20% or more to CLK_IN. In addition, the CLK_IN configuration is shown in the figure “CLK_IN (input) equivalent circuit (outline)” below. The 0.8V reference voltage and CLK_IN are compared to determine the edges, so input a signal of 0.8V or more (VCC voltage or less) as the external clock (CLK_IN). • External/internal clock switching Set the CTL pin Low before switching between the external clock and the internal clock. Switching clocks when running may give rise to output voltage fluctuations. • Maximum ON duty The maximum ON duty (Duty_MAX*) of channel 2 to channel 3 is the 85% (typ.) setting. When using the external clock (CLK_IN), the maximum ON duty (Duty_MAX*) becomes smaller, so care must be taken for the set output voltage. (CLK_IN (input) equivalent circuit (outline)) CLK_IN 0.8V No.A1512-9/9 LV5652T (4) SCP (short circuit protection) function • Description of operation When any one of FB1 to FB4 goes High due to the load being shorted or other reason, charging to the SCP pin starts. If output does not recover during the set time Tscp and SCP pin voltage exceeds the threshold voltage, the protective circuit (SCP) operates and all channel outputs are turned OFF. All outputs are latched off by the protection circuit (SCP). This latched state (output OFF) is canceled by setting the CTL pin Low or by turning the power supply OFF. When not using the protection function (SCP), the SCP pin must be shorted to GND_S with a line that is as short as possible. The SCP operation time is set by the capacitor connected to the SCP pin. (SCP charging operation) (SCP function) ⋅When STBY* is regarded as High (the output is turned on by setting CTL Low to High). SCP [V] Charging with Iscp = 4 [μA] 1.25 [V] (TYP) CTL SCP tscp Output short circuit T [s] Capacitor charging starts with the load being shorted Threshold voltage 1.25V (TYP) SCP_OUT SCP operation SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of August, 2009. Specifications and information herein are subject to change without notice. PS No.A1512-10/10