INTERSIL ISL54405IVZ-T

ISL54405
®
Data Sheet
June 5, 2008
CD/MP3 Quality Stereo 2:1 Multiplexer
with Click and Pop Elimination
The Intersil ISL54405 is a single supply, bidirectional, dual
single-pole/double-throw (SPDT) ultra low distortion, high
OFF-Isolation analog switch that can pass analog signals that
are positive and negative with respect to ground. It is primarily
targeted at consumer and professional audio switching
applications such as Computer Sound Cards and Home
Theater products. The inputs can accommodate ground
referenced signals up to 2VRMS while operating from a single
3.3V or 5V DC supply. The digital logic inputs are 1.8V
logic-compatible when using a single 3.3V or 5V supply. It can
be used in both AC or DC coupled ground referenced
applications.
FN6699.1
Features
• Clickless Audio Switching
• 2VRMS Signal Switching from 3.3V or 5V Supply
• -106dB THD+N into 20kΩ Load @ 2VRMS
• -108dB THD+N into 32Ω Load @ 3.9mW
• Signal to Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >124dBV
• ±0.01dB Insertion Loss at 1kHz, 20kΩ Load
• ±0.007dB Gain Variation 20Hz to 20kHz
• 125dB Signal Muting into 20kΩ Load
• 90dB PSRR 20Hz to 20kHz
• Single Supply Operation . . . . . . . . . . . . . . . . . . . . 3.3V or 5V
The ISL54405 features a soft-switch feature and click/pop
circuitry at each signal pin that eliminates clicks and pops
associated with power-up/down conditions of the preceding
amplifier outputs.
With -106dB THD+N performance with a 2VRMS signal into
20kΩ load, superior signal muting, high PSRR and very flat
frequency response the ISL54405 meets the exacting
requirements of consumer and professional audio engineers.
• Available in 16 Ld TSSOP, 16 Ld TQFN, and 16 Ld µTQFN
• Pb-Free (RoHS Compliant)
Applications
• Computer Sound Cards
• Home Theater Audio Products
• SACD/DVD Audio
The ISL54405 is available in 16 Ld TSSOP, 16 Ld 3mmx3mm
TQFN, and 16 Ld 2.6mmx1.8mm µTQFN packages. Its
specified for operation over the -40°C to +85°C temperature
range.
• DVD Player Audio Output Switching
• Headsets for MP3/Cellphone Switching
• Hi-Fi Audio Switching Application
TABLE 1. FEATURES AT A GLANCE
Block Diagram
ISL54405
Number of Switches
5V_Supply
2
Switch Type
DIR_SEL
SPDT or 2 to 1 MUX
AC/DC
MUTE
SEL
Insertion Loss
±0.01dB
THD+N, 2VRMS, 20kΩLoad
-106dB
OFF-Isolation (MUTE)
125dB
Packages
16 Ld TSSOP, 16 Ld 3x3 TQFN,
16 Ld 2.6x1.8 µTQFN
ISL54405
LOGIC
AND
CLICK/POP
CONTROL
VDD
CAP_SS
L1
L2
L
R1
R
R2
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
• Application Note AN557 “Recommended Test Procedures
for Analog Switches”
1
GND
For 5V operation connect the 5V_Supply pin to 5V and float the
VDD pin. For 3.3V operation connect the VDD pin to 3.3V and float
the 5V_Supply pin.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL54405
Pinouts (Note 1)
ISL54405
(16 LD TQFN)
TOP VIEW
AC/DC
5V_Supply
VDD
CAP_SS
AC/DC
5V_Supply
VDD
CAP_SS
ISL54405
(16 LD µTQFN)
TOP VIEW
16
15
14
13
16
15
14
13
L
2
11
L2
L
2
11
L2
R
3
10
R1
R
3
10
R1
SEL
4
9
R2
SEL
4
9
R2
5
6
7
8
5
6
7
8
GND
L1
GND
12
DIR_SEL
1
GND
MUTE
GND
L1
GND
12
DIR_SEL
1
GND
MUTE
ISL54405
(16 LD TSSOP)
TOP VIEW
5V_Supply
1
16 VDD
AC/DC
2
15 CAP_SS
MUTE
3
14 L1
L
4
13 L2
R
5
12 R1
SEL
6
11
GND
7
10 GND
DIR_SEL
8
9
R2
GND
NOTE:
1. See Page 1 for ISL54405 Block Diagram.
2
FN6699.1
June 5, 2008
ISL54405
Truth Table
INPUTS
OUTPUTS
AC/DC
DIR
MUTE
SEL
L1, R1
L2, R2
COM (L,R)
C/P Shunts
L1, R1
C/P Shunts
L2, R2
C/P Shunts
0
X
0
0
ON
OFF
OFF
OFF
OFF
0
X
0
1
OFF
ON
OFF
OFF
OFF
0
X
1
X
OFF
OFF
OFF
OFF
OFF
1
0
0
0
ON
OFF
OFF
OFF
ON
1
0
0
1
OFF
ON
OFF
ON
OFF
1
0
1
X
OFF
OFF
OFF
ON
ON
1
1
0
0
ON
OFF
OFF
OFF
OFF
1
1
0
1
OFF
ON
OFF
OFF
OFF
1
1
1
X
OFF
OFF
ON
OFF
OFF
NOTE: MUTE, AC/DC, DIR: Logic “0” ≤ 0.5V, Logic “1” ≥ 1.4V or Float with a 3.3V Supply or 5V supply.
SEL: Logic “0” ≤0.5V, Logic “1” ≥ 1.4V with a 3.3V Supply or 5V supply.
X = Don’t Care
Pin Descriptions (Continued)
Pin Descriptions
PIN
PIN
VDD
5V_Supply
GND
FUNCTION
System Power Supply Pin (+3V to +3.6V)
(Float pin for 5V applications)
5V Supply Pin (+4.5V to +5.5V)
(Float pin for 3.3V applications)
SEL
AC/DC
DIR_SEL
Ground Connection
FUNCTION
Input Select Control Pin
AC/DC Select Control Pin
DIRECTION Select Control Pin
R
Analog Switch Common Pin
L
Analog Switch Common Pin
CAP_SS
Soft-Start Capacitor Pin
L2, R2
Analog Switch Normally Open Pin
MUTE
Signal Mute Control Pin
L1, R1
Analog Switch Normally Closed Pin
Ordering Information
PART NUMBER
PART MARKING
TEMP. RANGE (°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL54405IVZ
(Note 2)
54405 IVZ
-40 to +85
16 Ld TSSOP
M16.173
ISL54405IVZ-T*
(Note 2)
54405 IVZ
-40 to +85
16 Ld TSSOP
M16.173
ISL54405IRTZ (Note 2)
05TZ
-40 to +85
16 Ld 3x3 TQFN
L16.3x3A
ISL54405IRTZ-T*
(Note 2)
05TZ
-40 to +85
16 Ld 3x3 TQFN
L16.3x3A
ISL54405IRUZ-T*
(Note 3)
GAD
-40 to+ 85
16 Ld µTQFN
L16.2.6x1.8A
*Please refer to TB347 for details on reel specifications.
NOTES:
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100%
matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering
operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu
plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020
3
FN6699.1
June 5, 2008
ISL54405
Absolute Maximum Ratings
Thermal Information
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 4.0V
5V_Supply to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V
Input Voltages
SEL, MUTE, AC/DC, DIR_SEL (Note 4) . . -0.3 to ((VDD) + 0.3V)
L1, L2, R1, R2 (Note 4) . . . . . . . . . . . . . . . . -3.1 to ((VDD) + 0.3V
Output Voltages
R, L (Note 4). . . . . . . . . . . . . . . . . . . . . . . . -3.1 to ((VDD) + 0.3V)
Continuous Current L1, L2, R1, R2 or L, R . . . . . . . . . . . . . ±300mA
Peak Current L1, L2, R1, R2 or L, R
(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . ±500mA
ESD Rating:
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>5kV
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>200V
Charged Device Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>2kV
Thermal Resistance (Typical)
θJA (°C/W)
θJC (°C/W)
16 Ld TSSOP Package (Note 5) . . . . .
150
N/A
16 Ld TQFN Package (Notes 6, 7). . . .
75
11
16 Ld µTQFN Package (Note 6) . . . . .
93
N/A
Maximum Junction Temperature (Plastic Package). . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
4. Signals on L1, L2, R1, R2, MUTE, SEL, AC/DC, DIR_SEL, R, and L exceeding VDD or GND by specified amount are clamped. Limit current to
maximum current ratings.
5. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
6. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
7. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications - 3.3V Supply Test Conditions: VDD = +3.0V to +3.6V, GND = 0V, VDIR_SEL = VAC/DC = GND,
V5V_SUPPLY = Float, VSIGNAL = 2VRMS, RLOAD = 20kΩ, f = 1kHz,
VSELH = VMUTEH = 1.4V, VSELL = VMUTEL = 0.5V, CAP_SS = 0.1µF, (Note 8),
Unless Otherwise Specified.
TEM
P
(°C)
MIN
(Notes 9, 10)
TYP
3.3V,
5V
Full
-
2
-
VRMS
VDD = 3.3V, IR or IL = 80mA, VLx or VRx =
-2.828V to +2.828V (See Figure 4)
3.3V
25
-
1.9
-
Ω
Full
-
2.6
-
Ω
rON Matching Between
Channels, ΔrON
VDD = 3.3V, IR or IL = 80mA, VLx or VRx = Voltage
at max rON over -2.828V to +2.828V (Note 13)
3.3V
rON Flatness, rFLAT(ON)
VDD = 3.3V, IR or IL = 80mA, VLx or VRx = -2.828V,
0V, +2.828V (Note 11)
3.3V
L, R, Lx, Rx Pull-down
Resistance
VDD = 3.6V, VLx or VRx = -2.83V, 2.83V, VL or
VR = -2.83V, 2.83V, VAC/DC = 0V, VMUTE = 3.6V,
Measure Current, calculate Resistance.
3.6V
PARAMETER
TEST CONDITIONS
SUPPL
Y
MAX
(Notes 9, 10) UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range,
VANALOG
ON-Resistance, rON
25
-
0.023
-
Ω
Full
-
0.045
-
Ω
25
-
0.003
0.01
Ω
Full
-
0.009
-
Ω
25
225
300
375
kΩ
Full
-
345
-
kΩ
25
-
-106
-
dB
VSIGNAL = 1.9VRMS, f = 1kHz, A-weighted Filter,
RLOAD = 20kΩ
25
-
-113
-
dB
VSIGNAL = 1.8VRMS, f = 1kHz, A-weighted Filter,
RLOAD = 20kΩ
25
-
-116
-
dB
VSIGNAL = 0.707VRMS, f = 1kHz, A-weighted Filter,
RLOAD = 32Ω
25
-
-100
-
dB
25
-
>124
-
dBV
DYNAMIC CHARACTERISTICS
THD+N
SNR
VSIGNAL = 2VRMS, f = 1kHz, A-weighted Filter,
RLOAD = 20kΩ
f = 20Hz to 20kHz, A-weighted Filter, Inputs
grounded, RLOAD = 20kΩ or 32Ω
4
3.3V,
5V
3.3V,
5V
FN6699.1
June 5, 2008
ISL54405
Electrical Specifications - 3.3V Supply Test Conditions: VDD = +3.0V to +3.6V, GND = 0V, VDIR_SEL = VAC/DC = GND,
V5V_SUPPLY = Float, VSIGNAL = 2VRMS, RLOAD = 20kΩ, f = 1kHz,
VSELH = VMUTEH = 1.4V, VSELL = VMUTEL = 0.5V, CAP_SS = 0.1µF, (Note 8),
Unless Otherwise Specified. (Continued)
PARAMETER
TEST CONDITIONS
SUPPL
Y
TEM
P
(°C)
MIN
(Notes 9, 10)
TYP
MAX
(Notes 9, 10) UNITS
Insertion Loss, GON
f = 1kHz, RLOAD = 20kΩ
3.3V
25
-
±0.01
-
dB
Gain vs Frequency, Gf
f = 20Hz to 20kHz, RLOAD = 20kΩ, Reference to
GON at 1kHz
3.3V
25
-
±0.007
-
dB
Stereo Channel Imbalance
L1 and R1, L2 and R2
f = 20Hz to 20kHz, RLOAD = 20kΩ
3.3V
25
-
±0.003
-
dB
OFF-Isolation (Muting)
f = 20Hz to 22kHz, L = R = 2VRMS, RLOAD = 20kΩ,
MUTE = AC/DC = 3.3V, DIR_SEL = GND,
SEL = “X”
3.3V,
5V
25
-
120
-
dB
f = 20Hz to 22kHz, L1, R1, L2, R2 = 2VRMS, RLOAD
= 20kΩ, MUTE = AC/DC = DIR_SEL = 3.3V,
SEL = “X”
25
-
120
-
dB
f = 20Hz to 22kHz, VL or VR = 0.7VRMS,
RLOAD = 32Ω
25
-
125
-
dB
25
-
120
-
dB
25
-
120
-
dB
25
-
110
-
dB
25
-
90
-
dB
Crosstalk (Channel-toChannel)
RL = 20kΩ, f = 20Hz to 20kHz, VSIGNAL = 2VRMS,
Signal source impedance = 20Ω, Note: Crosstalk is
inversely proportional to source impedance.
3.3V
RL = 32Ω, f = 20Hz to 20kHz, VSIGNAL = 0.7VRMS
Signal source impedance = 20Ω, Note: Crosstalk is
inversely proportional to source impedance.
PSRR
f = 1kHz, VSIGNAL= 100mVRMS, Inputs Grounded
f = 20kHz, VSIGNAL= 100mVRMS, Inputs
Grounded
3.3V,
5V
Bandwidth, -3dB
RLOAD = 50Ω
3.3V
25
-
230
-
MHz
ON to Mute Time,
TTRANS-OM
CAP_SS = 0.1µF
3.3V
25
-
50
-
ns
Mute to ON Time,
TTRANS-MO
CAP_SS = 0.1µF
(Selectable via Soft-Start Capacitor Value)
3.3V
25
-
58
-
ms
Turn-ON Time, tON
VDD = 3.3V, VLx or VRx = 1.5V, VMUTE = 0V,
RL = 20kΩ, (See Figure 1)
3.3V
25
-
45
-
μs
Turn-OFF Time, tOFF
VDD = 3.3V, VLx or VRx = 1.5V, VMUTE = 0V,
RL = 20kΩ, (See Figure 1)
3.3V
25
-
50
-
ns
Break-Before-Make Time
Delay, tD
VDD = 3.6V, VLx or VRx = 1.5V, VMUTE = 0V,
RL = 20kΩ, See Figure 2
3.6V
25
-
45
-
μs
OFF-Isolation
RL = 50Ω, f = 1MHz, VL or VR = 1VRMS,
(See Figure 3)
3.3V
25
-
100
-
dB
Crosstalk (Channel-toChannel)
RL = 50Ω, f = 1MHz, VL or VR = 1VRMS,
(See Figure 5)
3.3V
25
-
70
-
dB
Lx, Rx OFF Capacitance,
COFF
f = 1MHz, VLx or VRx = VL or VR = 0V
(See Figure 6)
3.3V
25
-
10
-
pF
L, R ON Capacitance,
CCOM(ON)
f = 1MHz, VLx or VRx = VCOM = 0V (See Figure 6)
3.3V
25
-
27
-
pF
3.3V
Full
3
-
3.6
V
5V
Full
4.5
-
5.5
V
POWER SUPPLY CHARACTERISTICS
Power Supply Range, VDD 5V_Supply = Float
Power Supply Range,
5V_Supply
VDD = Float
5
FN6699.1
June 5, 2008
ISL54405
Electrical Specifications - 3.3V Supply Test Conditions: VDD = +3.0V to +3.6V, GND = 0V, VDIR_SEL = VAC/DC = GND,
V5V_SUPPLY = Float, VSIGNAL = 2VRMS, RLOAD = 20kΩ, f = 1kHz,
VSELH = VMUTEH = 1.4V, VSELL = VMUTEL = 0.5V, CAP_SS = 0.1µF, (Note 8),
Unless Otherwise Specified. (Continued)
SUPPL
Y
TEM
P
(°C)
MIN
(Notes 9, 10)
TYP
3.6V
25
-
54
65
μA
Full
-
59
-
μA
3.6V
25
-
14
18
μA
3.6V
Full
-
15
-
μA
3.6V
25
-
55
65
μA
3.6V
Full
-
58
-
μA
Input Voltage Low, VSELL,
VMUTEL
3.3V,
5V
Full
-
-
0.5
V
Input Voltage High, VSELH,
VMUTEH
3.3V,
5V
Full
1.4
-
-
V
Input Current, ISELH, ISELL VDD = 3.6V, VMUTE = 0V, VSEL = 0V or VDD
3.6V
Full
-0.5
0.01
0.5
µA
Input Current, IAC/DCL,
IDIR_SELL
VDD = 3.6V, VAC/DC, VDIR_SEL = 0V,
VMUTE = Float, VSEL = VDD
3.6V
Full
-1.3
-0.7
0.3
µA
Input Current, IAC/DCH,
IDIR_SELH
VDD = 3.6V, VAC/DC, VDIR_SEL = VDD,
VMUTE = 0V, VSEL = 0V
3.6V
Full
-0.5
0.01
0.5
µA
Input Current, IMUTEL
VDD = 3.6V, VSEL = VDD, VMUTE = 0V
3.6V
Full
-1.3
-0.7
0.3
µA
Input Current, IMUTEH
VDD = 3.6V, VSEL = 0V, VMUTE = VDD
3.6V
Full
-0.5
0.01
0.5
µA
PARAMETER
Positive Supply Current, I+
TEST CONDITIONS
VDD = +3.6V, VMUTE = 0V, VSEL = 0V or VDD
VDD = +3.6V, VMUTE = VDD, VSEL = 0V or VDD
VDD = +3.6V, VMUTE = 0V, VSEL = 1.8V
MAX
(Notes 9, 10) UNITS
DIGITAL INPUT CHARACTERISTICS
NOTES:
8. VIN = input voltage to perform proper function.
9. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
10. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
11. Flatness is defined as the difference between maximum and minimum value of ON-resistance at the specified analog signal voltage points.
12. Limits established by characterization and are not production tested.
13. rON matching between channels is calculated by subtracting the channel with the highest max rON value from the channel with lowest max rON
value.
Test Circuits and Waveforms
VDD
LOGIC
INPUT
VDD
tr < 20ns
tf < 20ns
50%
C
0V
tOFF
SWITCH V
Lx OR VRx
INPUT
VOUT
Lx OR Rx
L or R
SEL
VOUT
90%
SWITCH
OUTPUT
SWITCH
INPUT
90%
LOGIC
INPUT
GND
MUTE
RL
CL
0V
tON
Logic input waveform is inverted for switches that have the opposite
logic sense.
FIGURE 1A. MEASUREMENT POINTS
6
Repeat test for all switches. CL includes fixture and stray
capacitance.
RL
V OUT = V (Lx or Rx) -----------------------R L + r ON
FIGURE 1B. TEST CIRCUIT
FN6699.1
June 5, 2008
ISL54405
Test Circuits and Waveforms (Continued)
FIGURE 1. SWITCHING TIMES
VDD
VDD
C
LOGIC
INPUT
0V
Lx
VNX
VOUT
R OR L
Rx
CL
RL
90%
SWITCH
OUTPUT
VOUT
SEL
0V
tD
GND
LOGIC
INPUT
MUTE
Repeat test for all switches. CL includes fixture and stray
capacitance.
FIGURE 2B. TEST CIRCUIT
FIGURE 2A. MEASUREMENT POINTS
FIGURE 2. BREAK-BEFORE-MAKE TIME
VDD
C
VDD
C
SIGNAL
GENERATOR
MUTE
Lx or Rx
rON = V1/80mA
Lx or Rx
SEL
0V OR VDD
VNX
80mA
SEL
V1
0V OR VDD
L, R
ANALYZER
GND
L, R
RL
GND MUTE
Signal direction through switch is reversed, worst case values
are recorded. Repeat test for all switches.
Repeat test for all switches.
FIGURE 3. OFF-ISOLATION TEST CIRCUIT
FIGURE 4. rON TEST CIRCUIT
VDD
C
VDD
C
SIGNAL
GENERATOR
Lx OR Rx
L, R
Lx or Rx
SEL
SEL
0V OR VDD
Lx or Rx
L, R
ANALYZER
0V OR VDD
IMPEDANCE
ANALYZER
L, R
NC
GND
RL
MUTE
Signal direction through switch is reversed, worst case values
are recorded. Repeat test for all switches.
FIGURE 5. CROSSTALK TEST CIRCUIT
7
GND
MUTE
Repeat test for all switches.
FIGURE 6. CAPACITANCE TEST CIRCUIT
FN6699.1
June 5, 2008
ISL54405
Sound Card AC Coupled Application Block Diagrams
FLOAT
DIR_SEL
AC/DC
MUTE
LOGIC
µCONTROLLER
SEL
3.3V
5V_Supply
VDD
ISL54405
LOGIC
AND
CLICK/POP
CONTROL
CAP_SS
0.1µF
L
L
SOFT-START
CAPACITOR
L1
L1
L2
FRONT PANEL
LINE OUT
OR
HEAD-PHONE
JACK
R1
AUDIO
CODEC
R1
R
R
R2
L2
BACK PANEL
LINE OUT
OR
HEAD-PHONE
JACK
R2
GND
FLOAT
DIR_SEL
AC/DC
MUTE
LOGIC
µCONTROLLER
SEL
3.3V
5V_Supply
VDD
ISL54405
LOGIC
AND
CLICK/POP
CONTROL
L
FRONT PANEL
LINE OUT
OR
HEAD-PHONE
JACK
CAP_SS
0.1µF
L1
L
SOFT-START
CAPACITOR
L1
L2
AUDIO
CODEC
R1
R2
R
R
R1
L2
AUDIO
GND
CODEC
R2
Detailed Description
The ISL54405 is a single supply, bi-directional, dual single
pole/double throw (SPDT) ultra low distortion, high
off-isolation analog switch. It was designed to operate from
either a 3.3V or 5V single supply. When operated with a 3.3V
or 5V single supply, the switches can accommodate
±2.83VPEAK (2VRMS) ground reference analog signals. The
switch rON flatness across this range is extremely small
resulting in excellent THD+N performance (0.0006% with
20kΩ load and 0.0014% with 32Ω load at 707mVRMS). The
T-Type configuration of the switch cells prevents signals
from getting through to the output when a switch is in the
OFF-state providing for superior mute performance
(>120dB) in audio applications.
8
The ISL54405 has special circuitry to eliminate click and
pops in the speakers during power-up and power-down of
the audio CODEC drivers, during removal and insertion of
headphones, and while switching between sources and
loads.
The ISL54405 was designed primarily for consumer and
professional audio switching applications such as computer
sound cards and home theater products. The “Application
Block Diagrams” on this page show two typical sound card
applications. In the upper block diagram the ISL54405 is being
used to route a single stereo source to either the front or back
panel line outs of the computer sound card. In the lower block
diagram the ISL54405 is being used to multiplex two stereo
sources to a single line out of the computer sound card.
FN6699.1
June 5, 2008
ISL54405
SPDT Switch Cell Architecture and Performance
Characteristics
The normally open (L2, R2) and normally closed (L1, R1) of
the SPDT switches are T-Type switches that have a typical
rON of 1.9Ω and an off-isolation of >120dB. The low onresistance (1.9Ω) and rON flatness (0.003Ω) provide very low
insertion loss and minimal distortion to applications that
require hi-fidelity signal reproduction.
The SPDT switch cells have internal charge pumps that
allow for signals to swing below ground. They were
specifically designed to pass audio signals that are ground
referenced and have a swing of ± 2.828VPEAK while driving
either 10k/20kΩ (receiver) or 32Ω (headphone) loads.
Each switch cell incorporates special circuitry to gradually
decrease the switch resistance when transitioning from the
OFF-state (high impedance) to the ON state (1.9Ω). The
gradual decrease in the switch resistance provides for a slow
ramp of the voltage at the load side of the switch which helps
to eliminate click and pops in the speaker by suppressing the
transient during switching events. The output voltage ramp
time is determined by the capacitor value of the soft-start
capacitor connected at the CAP_SS pin. With a 0.1µF
ceramic chip capacitor the ramp time is approximately
4.6V/s. The slow ramping of the signal at the output can be
disabled by floating the CAP_SS pin.
In addition to the slow ramp feature (soft-start feature) of the
in line switches, the part has special click and pop (C/P)
shunt circuitry at each of the signal pins (L, R, L1, L2, R1,
and R2). A pin’s C/P shunt circuitry is activated or deactivated depending on the logic levels applied at the AC/DC
and DIR_SEL control pins. This shunt circuitry serves two
functions:
1. In an AC coupled application they are activated and
directed to the source side of the switch to suppress or
eliminate click/pop noise in the speaker load when
powering up or down of the audio CODEC drivers.
2. For superior muting the C/P shunt circuitry is activated
and directed to the load side of the switch which gives
>120dB of off-isolation when driving a 10k/20kΩ receiver
load with an audio signal in the range of 20Hz to 22kHz.
If the AC/DC pin is driven LOW, all C/P shunt circuitry at all
the signal pins (L, R, L1, R1, L2, and R2) are deactivated
and not operable.
If the AC/DC pin is driven HIGH then the logic at the
DIR_SEL pin will determine whether the L and R (COM) C/P
shunt circuitry is activated or the L1, L2, R1, and R2 (NOx,
NCx) C/P shunt circuitry is activated. When the DIR_SEL is
driven LOW, the L1, R1, L2, R2 C/P shunt circuitry will be
activated while the L and R C/P shunt circuitry will be
deactivated. When the DIR_SEL is driven HIGH the L and R
C/P shunt circuitry will be activated while the L1, R1, L2, R2
C/P shunt circuitry will be deactivated. Note: Shunt circuitry
that is activated will be turned ON when a switch cell is
turned OFF and will be OFF when a switch cell is turned ON.
9
Supply Voltage, Signal Amplitude, Grounding
The power supply connected at VDD or the 5V_SUPPLY pin
provides power to the ISL54405 part. The ISL54405 is a
single supply device that was designed to be operated with a
3.3V ±10% DC supply connected at the VDD pin or a 5V
±10% DC supply connected at the 5V_SUPPLY pin.
It was specifically designed to accept ground referenced
2VRMS (± 2.828VPEAK) audio signals at its signal pins while
driving either 10k/20kΩ receiver loads or 32Ω headphone
loads.
When using the part in a 3.3V application the 5V_Supply pin
should be left floating. A 0.1µF decoupling capacitor should
be connected from the VDD pin to ground to minimize power
supply noise and transients. This capacitor should be
located as close to the pin as possible.
The part also has a 5V supply pin (5V_Supply) to allow it to
be used in 5V ±10% applications. Special circuitry within the
device converts the 5V, connected at the 5V_Supply pin, too
3.3V to properly power the internal circuitry of the device.
When using the part in a 5V application the VDD pin should
be left floating. A 0.1µF decoupling capacitor should be
connected from the 5V_Supply pin to ground to minimize
power supply noise. This capacitor should be located as
close to the pin as possible.
Grounding of the ISL54405 should follow a star configuration
(see Figure 7). All grounds of the IC should be directly
connected to the power supply ground return without
cascading to other grounds. This configuration isolates
shunt currents of the Click and Pop transients from the IC
ground and optimizes device performance.
+3.3V
MUTE
SEL
AC/DC
VDD
GND2
LOGIC
CONTROL
GND3
0.1µF
DIR_SEL
L
L1
L2
R
R1
R2
ISL54405
GND1
FIGURE 7. STAR GROUNDING CONFIGURATION
Mute Operation
When the MUTE logic pin is driven HIGH the part will go into
the Mute State. In the Mute State all switches of the SPDTs
are OPEN while the T-Shunt switches are closed. In addition
any activated click and pop shunt circuitry at the signal pins
is turned ON.
See “Logic Control” on page 10 for more details.
FN6699.1
June 5, 2008
ISL54405
MUTE TO ON
When the Mute pin is driven LOW the ISL54405 will
transition to the ON-state in the following sequence:
1. All active shunt switches turn-off quickly.
2. The resistance of the switches selected by the SEL pin
will gradually decrease in resistance. They will decrease
from their high OFF-resistance to their ON-resistance of
1.9Ω. This gradual decrease in resistance will allow for
the voltage at the load to increase gradually. The voltage
ramp rate at the load is determined by the value of the
capacitor connected at the CAP_SS pin. See Figures 27
and 28 in the “Typical Performance Curves” beginning on
page 13.
Table 2 indicates how the signal ramp rate at the load
changes as you change the CAP_SS capacitor value. It also
shows how the mute turn-on time is affected.
TABLE 2. SIGNAL RAMP-RATE LOAD CHANGE WITH
CAP SS
CAPACITOR
VALUE
RAMP RATE
TURN-ON TIME
No Capacitor
6250V/s
65µs
0.05µF
10.3V/s
30ms
0.1µF
4.6V/s
58ms
ON TO MUTE
When the Mute pin is driven HIGH the switches will turn OFF
quickly (50ns) and the active shunt switches will turn ON
quickly. Note: There is no gradual ramping of the switch
resistance in this direction.
OFF-ISOLATION IN THE MUTE STATE
When in the mute state, the level of OFF-Isolation across the
audio band is dependent on the signal amplitude, external
loading, and location of the activated C/P (click/pop) shunt
circuitry. During muting the logic of the ISL54405 can be
configured to activate the C/P shunt circuitry on the load side
of the switch or on the source side of the switch, or
deactivated on both sides of the switch.
With a 0.707VRMS signal driving a 32Ω headphone load the
location of the C/P shunt circuitry has little effect on the
off-isolation performance (> 120dB of off-isolation in all
configurations). See Figure 11 in the “Typical Performance
Curves” beginning on page 13.
With a 2VRMS signal driving a 20kΩ amplifier load the best
off-isolation is achieved by placing the C/P shunt circuitry on
the load side of the switch (>120dB across the audio band).
The off-isolation decreases when placing the C/P shunt
circuitry on the source side of the switch (>85dB across the
audio band). See Figure 10 in the “Typical Performance
Curves” beginning on page 13.
Note: For AC coupled applications when powering up or
down of the audio codecs the C/P shunts should be
10
activated on the source side of the switch. See “Click and
Pop Operation” on page 11.
When using the switch for muting of the audio signal the C/P
shunt circuitry should be de-activated on the source side of
the switch and directed to the load side of the switch for best
possible off-isolation.
Logic Control
The ISL54405 has four logic control pins; the AC/DC,
DIR_SEL, MUTE, and SEL. The MUTE and SEL control pins
determine the state of the switches. The AC/DC and
DIR_SEL control pins determine the location of the C/P
(click/pop) shunt circuitry and if it will be active or not. See
“Truth Table” on page 3.
The ISL54405 logic is 1.8V CMOS compatible (Low ≤ 0.5V
and High ≥ 1.4V) over a supply range of 3.0V to 3.6V at the
VDD pin or 4.5V to 5.5V at the 5V_SUPPLY pin. This allows
control via 1.8V or 3V µcontroller.
SEL, MUTE CONTROL PINS
The state of the SPDT switches of the ISL54405 device is
determined by the voltage at the MUTE pin and the SEL pin.
The SEL control pin is only active when MUTE is logic “0”.
The MUTE has an internal pull-up resistor to the internal
3.3V supply rail and can be driven high or tri-stated(floated)
by the µprocessor.
These pins are 1.8V logic compatible. When powering the
part by the VDD pin the logic voltage can be as high as the
VDD voltage which is typically 3.3V. When powering the part
by the 5V_SUPPLY pin the logic voltage can be as high as
the 5V_SUPPLY voltage which is typically 5V.
Logic Levels:
MUTE = Logic “0” (Low) when ≤ 0.5V
MUTE = Logic “1” (High) when ≥1.4V or Floating
SEL = Logic “0” (Low) when ≤ 0.5V
SEL = Logic “1” (High) when ≥1.4V
AC/DC AND DIR_SEL CONTROL PINS
The ISL54405 contains C/P (click/pop) shunt circuitry on its
COM pins (L, R) and on its signal pins (L1, R1, L2, R2). The
activation of this circuitry and whether it is located on the
COM or signal side of the switch is determined by the logic
levels applied at the AC/DC and DIR_SEL pins. The
DIR_SEL control pin is only active when AC/DC is logic “1”.
Note: Any activated C/P shunt circuitry is ON when in the
mute state (MUTE = Logic “1”) and OFF in the audio state
(MUTE = Logic “0”).
When AC/DC is logic “0”, all of the C/P shunt circuitry on
both sides of the switch is deactivated and not operable.
When AC/DC is logic “1” then the DIR_SEL logic level
determines whether the shunt circuitry will be activated on
the COM side of the switch or on the signal side of the
switch. When DIR_SEL = Logic “1” the C/P shunts on the
FN6699.1
June 5, 2008
ISL54405
COM side (L,R) are activated and inoperable on the signal
side (L1, R1, L2, R2) of the switch. When DIR_SEL = Logic
“0” the C/P shunts are activated on the signal side (L1, R1,
L2, R2) and inoperable on the COM side (L, R).
Logic Levels:
AC/DC, DIR_SEL = Logic “0” (Low) when ≤ 0.5V
AC/DC, DIR_SEL = Logic “1” (High) when ≥1.4V or Floating.
The AC/DC and DIR_SEL have internal pull-up resistors to
the internal 3.3V supply rail and can be driven high or
tri-stated (floated by the µprocessor). They should be driven
to ground for a logic “0” (Low). Note: For 5V applications, the
AC/DC and DIR_SEL pins should never be driven to the
external 5V rail. They need to be driven with 1.8V logic or 3V
logic circuit.
AC Coupled or DC Coupled Operation
The Audio CODEC drivers can be directly coupled to the
ISL54405 when the audio signals from the drivers are
ground referenced or do not have a significant DC offset
voltage, < 50mV. Otherwise the signal should be AC coupled
to the ISL54405 part.
CLICK AND POP OPERATION
The ISL54405 has special circuitry to eliminate click and
pops in the speakers during power-up and power-down of
the Audio CODEC Drivers and during removal and insertion
of headphones.
A different click and pop scheme is required depending on
whether the audio CODEC drivers are AC coupled or DC
coupled to the inputs of the ISL54405 part.
AC COUPLED CLICK AND POP OPERATION
Single supply audio drivers have their signal biased at a DC
offset voltage, usually at 1/2 the DC supply voltage of the
driver. As this DC bias voltage comes up or goes down
during power up or down of the driver a transient can be
coupled into the speaker load through the DC blocking
capacitor (see the “Application Block Diagrams” on page 8).
When a driver is OFF and suddenly turned ON the rapidly
changing DC bias voltage at the output of the driver will
cause an equal voltage at the input side of the switch due to
the fact that the voltage across the blocking capacitor cannot
change instantly. If the switch is in Audio mode or there is no
low impedance path to discharge the capacitor voltage at the
input of the switch, before turning on the switch, a transient
discharge will occur in the speaker, generating a Click and
pop noise.
Proper elimination of a click/pop transient at the speaker
load while powering up or down of the audio driver requires
that the ISL54405 have its C/P shunts activated on the
source side of the switch and then placed in Mute mode.
This allows the transient generated by the audio drivers to
be discharged through the Click and Pop shunt circuitry.
11
Once the driver DC bias has reached VDD/2 and the
transient on the switch side of the DC blocking capacitor has
been discharged to ground through the C/P shunt circuitry,
the switches can be turned ON and connected through to the
speaker loads without generating an undesirable click/pop in
the speakers.
With a typical DC blocking capacitor of 220µF and the C/P
shunt circuitry designed to have a resistance of 40Ω,
allowing a 100ms wait time to discharge the transient before
placing the switch in the Audio mode will prevent the
transient from getting through to the speaker load. See
Figures 25 and 26 in the “Typical Performance Curves”
beginning on page 13.
DC COUPLED CLICK AND POP OPERATION
The ISL54405 can pass ground referenced audio signals
which allows it to be directly connected to audio drivers that
output ground referenced audio signals, eliminating the need
for a DC blocking capacitor.
Audio drivers that swing around ground however do
generate some DC offset, from a few millivolts to tens of
millivolts. When switching between audio channels or muting
the audio signal these small DC offset levels of the drivers
can generate a transient that can cause un-wanted clicks
and pops in the speaker loads.
In a DC coupled application the C/P shunt resistors placed at
the source side of the switch have no effect in eliminating the
transients at the speaker loads when transitioning in and out
of the mute state or switching between channels. In fact
having these C/P shunts active on the source side only
increase un-neccesary power consumption. So, for DC
coupled connection the C/P shunt circuitry should not be
applied at the source (driver) side of the switch.
For DC coupled applications the ISL54405 has a special
soft-start feature that slowly ramps the DC offset voltage
from the audio driver to the speaker load when turning ON a
switch channel. The ramp rate at the load is determined by
the capacitor value connected at the CAP_SS pin.
Lab experimentation has shown that if you can slow the
voltage ramp rate at the speaker to < 10V/s, you can
eliminate click/pop noise in a speaker. A soft-start capacitor
value of 0.1µF provides for 4.5V/s ramp rate and is
recommended. See Figures 27 and 28 in the “Typical
Performance Curves” beginning on page 13.
See “MUTE to ON” section on page 10 for more detail of
how soft-start works.
Supply Sequencing and Overvoltage Protection
With any CMOS device, proper power supply sequencing is
required to protect the device from excessive input currents
which might permanently damage the IC. All I/O pins contain
ESD protection diodes or diode stacks from the pin to VDD
and to GND (see Figure 8). To prevent forward biasing these
FN6699.1
June 5, 2008
ISL54405
diodes, VDD must be applied before any input signals, and
the signal voltages must remain between VDD and -3V and
the logic voltage must remain between VDD and ground.
If these conditions cannot be guaranteed, then precautions
must be implemented to prohibit the current and voltage at
the logic pin and signal pins from exceeding the maximum
ratings of the switch. The following two methods can be used
to provided additional protection to limit the current in the
event that the voltage at a signal pin goes below ground by
more than -3V or above the VDD rail and the logic pin goes
below ground or above the VDD rail.
Logic inputs can be protected by adding a 1kΩ resistor in
series with the logic input (see Figure 8). The resistor limits
the input current below the threshold that produces
permanent damage, and the sub-microamp input current
produces an insignificant voltage drop during normal
operation.
This method is not acceptable for the signal path inputs.
Adding a series resistor to the switch input defeats the
purpose of using a low rON switch. Connecting Schottky
diodes to the signal pins (as shown in Figure 8) will shunt the
fault current to the supply or to ground thereby protecting the
switch. These Schottky diodes must be sized to handle the
expected fault current and to clamp when the voltage
reaches the overvoltage limit.
12
.
OPTIONAL
SCHOTTKY
DIODE
VDD
OPTIONAL
PROTECTION
RESISTOR
LOGIC
INPUT
VNX
VCOM
GND
OPTIONAL
SCHOTTKY
DIODE
FIGURE 8. OVERVOLTAGE PROTECTION
High-Frequency Performance
In 50Ω systems, the ISL54405 has a -3dB bandwidth of
230MHz (see Figure 29). The frequency response is very
consistent over varying analog signal levels.
An OFF-switch acts like a capacitor and passes higher
frequencies with less attenuation, resulting in signal
feedthrough from a switch’s input to its output. Off-Isolation
is the resistance to this feedthrough, while crosstalk
indicates the amount of feedthrough from one switch to
another. Figure 30 details the high Off-Isolation and crosstalk
rejection provided by this part. At 1MHz, Off-Isolation is
about 100dB in 50Ω systems, decreasing approximately
20dB per decade as frequency increases. Higher load
impedances decrease off-Isolation and Crosstalk rejection
due to the voltage divider action of the switch off impedance
and the load impedance.
FN6699.1
June 5, 2008
ISL54405
Typical Performance Curves TA = +25°C, Unless Otherwise Specified
80
3.0
VDD = 3.3V
+85°C
ICOM = 80mA
2.5
VDD = 3.3V OR V_Supply = 5V
C/P SHUNT ON SIGNAL SIDE
RLOAD = 20kΩ
VSIGNAL = 2VRMS
OFF- ISOLATION (dB)
100
2.0
rON (Ω)
90
+25°C
1.5
-40°C
1.0
110
120
NO C/P SHUNT
130
140
C/P SHUNT ON LOAD SIDE
150
0.5
160
0
-3
-2
-1
0
VCOM (V)
1
2
170
20
3
VDD = 3.3V OR V_Supply = 5V
RLOAD = 32Ω
VSIGNAL = 0.707VRMS
120
C/P SHUNT ON SIGNAL SIDE
140
No C/P SHUNT
C/P SHUNT ON LOAD SIDE
150
CROSSTALK (dB)
OFF- ISOLATION (dB)
110
130
160
170
180
20
50
100
200
500 1k
FREQUENCY (Hz)
2k
5k
10k 20k
FIGURE 11. OFF-ISOLATION, 0.707VRMS SIGNAL, 32Ω LOAD
CROSS TALK (dB)
-95
-100
-80
-85
VDD = 3.3V
-90
RLOAD = 20kΩ
-95
VSIGNAL = 2VRMS
-100
-105
-110
-115
-120
-125
-130
-135
-140
-145
-150
-155
-160
-165
-170
20
50
100 200
500 1k
FREQUENCY (Hz)
VDD = 3.3V
0.045
RLOAD = 32Ω
VDD = 3.3V
RLOAD = 20kΩ
0.040
VSIGNAL = 2VRMS
VSIGNAL = 0.707VRMS
-105
-110
-115
-120
-125
-130
-135
2k
5k
10k 20k
2k
5k
10k 20k
0.035
0.030
0.025
0.020
0.015
0.010
-140
-145
-150
20
1k
0.050
INSERTION LOSS (dB)
-90
500
FIGURE 12. CHANNEL-TO-CHANNEL CROSSTALK
-80
-85
200
FIGURE 10. OFF-ISOLATION, 2VRMS SIGNAL, 20kΩLoad
80
100
100
FREQUENCY (Hz)
FIGURE 9. ON-RESISTANCE vs SWITCH VOLTAGE
90
50
0.005
50
100 200
500 1k 2k
FREQUENCY (Hz)
5k
10k 20k
FIGURE 13. CHANNEL-TO-CHANNEL CROSSTALK
13
0.000
20
100
1k
FREQUENCY (Hz)
10k
20k
FIGURE 14. INSERTION LOSS vs FREQUENCY
FN6699.1
June 5, 2008
ISL54405
Typical Performance Curves TA = +25°C, Unless Otherwise Specified (Continued)
0.05
0.020
VDD = 3.3V
0.04
RLOAD = 20kΩ
0.03
VSIGNAL = 2VRMS
0.01
0.00
-0.01
-0.02
STEREO IMPBALNCE (dB)
RELATIVE TO 1kHz
0.02
GF (dB)
VDD = 3.3V
RLOAD = 20kΩ
0.015
VSIGNAL = 2VRMS
0.010
0.005
L2 AND R2
0
-0.005
L1 AND R1
-0.010
-0.03
-0.015
-0.04
-0.05
20
100
1k
10k
-0.020
20
20k
100
FREQUENCY (Hz)
FIGURE 15. GAIN vs FREQUENCY
-90
-94
-96
0.0020
20k
VDD = 3.3V
RLOAD = 32Ω
A-WEIGHTED FILTER
-98
THD+N (%)
-100
THD+N (%)
10k
FIGURE 16. STEREO IMBALANCE vs FREQUENCY
VDD = 3.3V
RLOAD = 32Ω
A-WEIGHTED FILTER
-92
1k
FREQUENCY (Hz)
-102
-104
1VP-P
-106
-108
0.0010
0.0009
0.0008
0.0007
0.0006
0.0005
1VP-P
0.0004
510mVP-P
0.0003
-110
510mVP-P
-112
0.0002
-114
-116
-118
-120
20
50
100
200
500
1k
2k
5k
0.0001
10k 20k
20
50
100
FREQUENCY (Hz)
1k
2k
5k
10k 20k
FIGURE 18. THD+N vs SIGNAL LEVELS vs FREQUENCY
0.0010
0.0009
0.0008
0.0007
VDD = 3.3V
RLOAD = 20kΩ
A-WEIGHTED FILTER
VDD = 3.3V
RLOAD = 20kΩ
A-WEIGHTED FILTER
0.0006
2VRMS
0.0005
THD+N (%)
THD+N( dB)
500
FREQUENCY (Hz)
FIGURE 17. THD+N vs SIGNAL LEVELS vs FREQUENCY
-100
-101
-102
-103
-104
-105
-106
-107
-108
-109
-110
-111
-112
-113
-114
-115
-116
-117
-118
-119
-120
200
1.9VRMS
0.0004
2VRMS
0.0003
1.9VRMS
0.0002
1.8VRMS
1.8VRMS
1.5VRMS
1.5VRMS
20
50
100
200
500 1k
2k
FREQUENCY (Hz)
5k
10k 20k
FIGURE 19. THD+N vs SIGNAL LEVELS vs FREQUENCY
14
0.0001
20
50
100
200
500 1k
2k
FREQUENCY (Hz)
5k
10k 20k
FIGURE 20. THD+N vs SIGNAL LEVELS vs FREQUENCY
FN6699.1
June 5, 2008
ISL54405
-100
-101
-102
-103
-104
-105
-106
-107
-108
-109
-110
-111
-112
-113
-114
-115
-116
-117
-118
-119
-120
VDD = 3.3V
RLOAD = 20kΩ
10Hz to 30k FILTER
2VRMS
1.9VRMS
1.7VRMS TO 1.8VRMS
THD+N (%)
THD+N( dB)
Typical Performance Curves TA = +25°C, Unless Otherwise Specified (Continued)
1.6VRMS
1.5VRMS
20
50
100
200
500 1k
2k
FREQUENCY (Hz)
5k
10k 20k
VDD/2
2V/DIV
PSRR (dB)
6
5
4
3
2
VOLTAGE (V)
VOLTAGE (V)
2V/DIV
2
1
-1
200mV/DIV
LIN
-2
0
-1
-3
-4
-7
1.5VRMS
20
50
100
200
500
1k
2k
5k
10k
20k
LOUT
-5
200mV/DIV
-0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0
TIME (s) 100ms/DIV
VDD/2
2V/DIV
LIN
200mV/DIV
LOUT
200mV/DIV
-6
0.1
0.2
0.3
0.4
FIGURE 25. 20kΩ AC COUPLED CLICK/POP REDUCTION
15
2V/DIV
MUTE
-2
-4
-6
1.6VRMS
1
-3
-5
1.7VRMS TO 1.8VRMS
7
MUTE
3
0
1.9VRMS
FIGURE 24. PSRR vs FREQUENCY
7
4
2VRMS
-50
-55
5V_Supply = 5VDC + 100MVRMS SIGNAL
-60
RLOAD = 20kΩ OR 32Ω
-65
-70 INPUTS GROUNDED
-75
-80
-85
-90
-95
-100
AUDIO MODE
-105
-110
-115
MUTE MODE
-120
(C/P SHUNT ON LOADSIDE)
-125
-130
-135
-140
20
50 100 200
500 1k 2k
5k 10k 20k 40k
FREQUENCY (Hz)
FIGURE 23. PSRR vs FREQUENCY
5
10Hz TO 30k FILTER
FIGURE 22. THD+N vs SIGNAL LEVELS vs FREQUENCY
-60
-65
VDD = 3.3VDC + 100mVRMS SIGNAL
-70
RLOAD = 20kΩ OR 32Ω
-75
INPUTS GROUNDED
-80
-85
-90
-95
AUDIO MODE
-100
-105
-110
-115
MUTE MODE
-120
(C/P SHUNT ON LOADSIDE)
-125
-130
-135
-140
20
50 100 200
500 1k
2k
5k 10k 20k 40k
FREQUENCY (Hz)
6
VDD = 3.3V
RLOAD = 20kΩ
FREQUENCY (Hz)
FIGURE 21. THD+N vs SIGNAL LEVELS vs FREQUENCY
PSRR ( dB)
0.00100
0.00095
0.00090
0.00085
0.00080
0.00075
0.00070
0.00065
0.00060
0.00055
0.00050
0.00045
0.00040
0.00035
0.00030
0.00025
0.00020
0.00015
0.00010
-7
-0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0
TIME (s) 100ms/DIV
0.1
0.2
0.3
0.4
FIGURE 26. 32Ω AC COUPLED CLICK/POP REDUCTION
FN6699.1
June 5, 2008
ISL54405
Typical Performance Curves TA = +25°C, Unless Otherwise Specified (Continued)
80
80
LEFT INPUT
LEFT INPUT
60
60
40
40
LEFT OUTPUT
0
RIGHT OUTPUT
-20
4.6V/s
-40
-60
-20
-20
0
20
TIME (ms)
40
60
80
RIGHT OUTPUT
-20
0
20
40
60
80
100
TIME (ms)
FIGURE 27. SOFT-START (0.1µF) CLICK/POP REDUCTION
FIGURE 28. SOFT-START (0.05µF) CLICK/POP REDUCTION
0
VDD = 3.3V
RLOAD = 50Ω
0
10.3V/s
VDD = 3.3V
CAP_SS = 0.05µF
-80
-100 -80 -60 -40
100
LEFT OUTPUT
RIGHT INPUT
-60
VDD = 3.3V
10.3V/s
0
-40
RIGHT INPUT
CAP_SS = 0.1µF
-80
-100 -80 -60 -40
OFF-ISOLATION (dB)
-2
-3
0
VDD = 3.3V
RLOAD = 50Ω
-1
NORMALIZED GAIN (dB)
20
20
-20
40
-40
CROSSTALK
60
-60
80
-80
CROSSTALK (dB)
20
VOLTAGE (mV)
VOLTAGE (mV)
4.6V/s
ISOLATION
100
120
1
10
FREQUENCY (MHz)
100
FIGURE 29. FREQUENCY RESPONSE
300
-100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
100M
-120
500M
FIGURE 30. CROSSTALK AND OFF-ISOLATION
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP):
GND
TRANSISTOR COUNT:
3376
PROCESS:
Submicron CMOS
16
FN6699.1
June 5, 2008
ISL54405
Thin Shrink Small Outline Plastic Packages (TSSOP)
M16.173
N
16 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
E
0.25(0.010) M
E1
2
INCHES
GAUGE
PLANE
-B1
B M
0.05(0.002)
-A-
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
-
0.043
-
1.10
-
A1
3
L
A
D
-C-
e
α
A1
b
0.10(0.004) M
0.25
0.010
SEATING PLANE
c
0.10(0.004)
C A M
0.05
0.15
-
A2
0.033
0.037
0.85
0.95
-
b
0.0075
0.012
0.19
0.30
9
c
0.0035
0.008
0.09
0.20
-
B S
0.002
D
0.193
0.201
4.90
5.10
3
0.169
0.177
4.30
4.50
4
0.026 BSC
E
0.246
L
0.020
N
α
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AB, Issue E.
0.006
E1
e
A2
MILLIMETERS
0.65 BSC
0.256
6.25
0.028
0.50
16
0o
-
0.70
6
16
8o
0o
-
6.50
7
8o
Rev. 1 2/02
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.15mm (0.006
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees)
17
FN6699.1
June 5, 2008
ISL54405
Ultra Thin Quad Flat No-Lead Plastic Package (UTQFN)
D
L16.2.6x1.8A
B
16 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
MILLIMETERS
6
INDEX AREA
2X
A
N
SYMBOL
E
0.10 C
1 2
2X
MIN
NOMINAL
MAX
NOTES
A
0.45
0.50
0.55
-
A1
-
-
0.05
-
0.10 C
A3
TOP VIEW
0.10 C
C
A
0.05 C
0.127 REF
-
b
0.15
0.20
0.25
5
D
2.55
2.60
2.65
-
E
1.75
1.80
1.85
-
e
0.40 BSC
-
SEATING PLANE
A1
SIDE VIEW
L
0.35
0.40
0.45
-
L1
0.45
0.50
0.55
-
N
16
2
Nd
4
3
Ne
4
3
e
PIN #1 ID
θ
1 2
0
-
NX L
L1
(DATUM A)
4
Rev. 4 8/06
NX b 5
16X
0.10 M C A B
0.05 M C
(DATUM B)
12
BOTTOM VIEW
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on D and E side,
respectively.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
CL
(A1)
NX (b)
L
5
8. Maximum allowable burrs is 0.076mm in all directions.
e
SECTION "C-C"
7. Maximum package warpage is 0.05mm.
TERMINAL TIP
C C
9. JEDEC Reference MO-255.
10. For additional information, to assist with the PCB Land Pattern
Design effort, see Intersil Technical Brief TB389.
3.00
1.80
1.40
1.40
2.20
0.90
0.40
0.20
0.50
0.20
0.40
10 LAND PATTERN
18
FN6699.1
June 5, 2008
ISL54405
Thin Quad Flat No-Lead Plastic Package (TQFN)
Thin Micro Lead Frame Plastic Package (TMLFP)
)
2X
L16.3x3A
0.15 C A
D
A
16 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
9
D/2
MILLIMETERS
D1
D1/2
2X
N
6
INDEX
AREA
0.15 C B
1
2
3
E1/2
E/2
MIN
NOMINAL
MAX
NOTES
A
0.70
0.75
0.80
-
A1
-
-
0.05
-
A2
-
-
0.80
9
0.30
5, 8
A3
E1
E
b
9
0.20 REF
0.18
D
2X
B
TOP VIEW
0.15 C A
A2
A
D2
/ / 0.10 C
0
C
A3
SIDE VIEW
9
5
NX b
4X P
E
3.00 BSC
-
2.75 BSC
9
1.35
1.50
1.65
7, 8, 10
0.50 BSC
-
k
0.20
-
-
-
L
0.30
0.40
0.50
8
2
8
Nd
4
3
NX k
Ne
4
3
D2
2 N
1
(DATUM A)
2
3
6
INDEX
AREA
8
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
5
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
SECTION "C-C"
C
L
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
L
TERMINAL TIP
FOR ODD TERMINAL/SIDE
9
4. All dimensions are in millimeters. Angles are in degrees.
A1
e
9
12
3. Nd and Ne refer to the number of terminals on each D and E.
NX b
10
0.60
-
2. N is the number of terminals.
BOTTOM VIEW
C
L
-
-
NOTES:
9
CORNER
OPTION 4X
(Nd-1)Xe
REF.
-
θ
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
E2/2
N e
P
Rev. 0 6/04
(Ne-1)Xe
REF.
E2
7
NX L
C C
7, 8, 10
16
7
L1
9
1.65
N
4X P
8
1.50
0.10 M C A B
D2
(DATUM B)
A1
-
2.75 BSC
1.35
e
SEATING PLANE
9
E1
E2
0.08 C
0.23
3.00 BSC
D1
0.15 C B
2X
4X
SYMBOL
L1
10
L
e
FOR EVEN TERMINAL/SIDE
9. Features and dimensions A2, A3, D1, E1, P & θ are present when
Anvil singulation method is used and not present for saw
singulation.
10. Compliant to JEDEC MO-220WEED-2 Issue C, except for the E2
and D2 MAX dimension.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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19
FN6699.1
June 5, 2008