E7804 133 MHZ Quad Pin Electronics Driver and Window Comparator TEST AND MEASUREMENT PRODUCTS Description Features • Four Integrated Three-Statable Drivers and Window Comparators • Driver Voltage Range –0.2V, +5.2V • Comparator Voltage Range –2.0V to +5.5V • Internal Disconnect Switches • Internal Switches to an External PMU, Range –4.75V to +9.75V, up to ±40 mA • Per Pin Pull-Up/Down 2KΩ to (0V to +5V) • Per Pin Continuity Test (Force Current up to –250 µA, Limit Voltage 0 to –2V) • Self-Calibrating Driver Source Impedance to an External Reference (48Ω to 110Ω) • Low Power Dissipation (250mW/channel quiescent) • 128 Pin MQFP Package (with Internal Heat Spreader) The E7804 is a quad channel, monolithic ATE pin electronics solution manufactured in a high-performance BiCMOS process. The E7804 operates up to 133 MHz with up to 3V signals, and 100 MHz with 5V signals. Each channel has a three-statable driver capable of generating 5.4V swings over a –0.2V, +5.2V range. Drivers have independent high and low input levels that are buffered internally. Drivers feature a self-calibrating source impedance, programmable in the range 48Ω to 110Ω. The source impedance of all drivers matches REREF/100, where REREF is the external reference resistor. Each channel’s dual comparator has a range of –2.0V to +5.5V. Applications A channel’s driver and comparators are connected internally via high voltage switches to the VIO pin. These switches provide a means to disconnect the driver and comparator from the VIO pin. • Design for Test/Structural Pins in ATE •Low Cost – Logic Testers – Memory Testers The E7804 contains an independent network of high voltage switches intended to connect an external Parametric Measurement Unit (EPMU) to any channel (or channels) output on the channel’s POUT pin. The EPMU can have a range of –4.75V to +9.75V, up to ±40 mA. Typically, a channel’s VIO and POUT pins are connected together externally. EREF SDIN CLKIN DVH[0] DHI[0] Each channel contains a continuity test circuit (CTC) with a switch to connect it to the channel’s POUT pin. This circuit forces a current up to –250 µA, and tests the resulting voltage with a 0 to –2V programmable limit. The result is tested by the channel’s comparator. 48 110Ω DEN[0] DVL[0] OPN[0] CVA[0] QA[0] VIO[0] POUT[0] QB[0] CVB[0] LOAD RESET* Each channel contains a 2KΩ pull-up resistor with a switch to connect to the channel’s POUT pin. CTC 2K Control Logic DVH[3] DHI[3] The channel’s function and connections are programmed using a serial interface. An individual channel’s function can be programmed, or a function of any set of channels (of multiple E7804s) can be programmed in parallel where each channel can belong to none, one, or more (up to 8) sets. 48 110Ω DEN[3] DVL[3] OPN[3] CVA[3] QA[3] VIO[3] POUT[3] QB[3] CVB[3] The E7804 features the inclusion of all four channels of pin electronics into a 128 pin package. Revision 7 / February 26, 2007 PUV EPMUS EPMUF CTCLV CTCFIV Functional Block Diagram CTC 2K SDOUT ANODE PMU_OUT United States Patent 7,064,575 www.semtech.com E7804 TEST AND MEASUREMENT PRODUCTS PIN Description Pin # Pin Name Description 12, 27, 76, 91 OPN[0:3] LV_TTL input that opens switches that disconnect the driver and comparator from VIO. This input overrides the individual switch register bits non destructively. 15, 24, 79, 88 VIO[0:3] Device input/output of each channel. Driver, Comparator 127, 40, 63, 104 128, 39, 64, 103 1, 38, 65, 102 2, 37, 66, 101 126, 41, 62, 105 125, 42, 61, 106 DHI, DHI*[0:3] "Flex" differential input digital pins which select the driver high or low level. DEN, DEN*[0:3] "Flex" differential input pins which control the driver being active or in a high impedance state. DVH, DVL[0:3] High impedance analog voltage inputs which determine the driver high and low levels. Connect a 0.22µf capacitor to ground for bypassing reasons. 16, 23, 80, 87 14, 25, 78, 89 DBH, DBL[0:3] Driver level buffer outputs for high and low levels. Connect a 0.47 µF capacitor to ground for bypassing reasons. 124, 43, 60, 107 123, 44, 59, 108 CVA, CVB[0:3] Analog inputs which set the A and B comparator thresholds. 10, 29, 74, 93 9, 30, 73, 94 QA, QA*[0:3] Differential digital outputs of comparator A. 8, 31, 72, 95 7, 32, 71, 96 QB, QB*[0:3] Differential digital outputs of comparator B. PMU 111 PMU_OUT PMU test point for the anode of the thermal diode string. 5, 34, 69, 98 POUT[0:3] Parametric Measure Unit input/output of each channel. 110 EPMUF External parametric measurement for force input. 109 EPMUS External parametric measurement for sense input. 114 PUV 120 CTCLV Continuity test circuit limit voltage. 118 CTCFIV Continuity test circuit force current voltage. 54 RESET* Active low chip reset. Resets the internal registers. It is an asynchronous input not requiring any CLKIN transitions. 51 CLKIN Clock for the input data shift register. 50 SDIN Serial data input. 49 SDOUT 53 LOAD Pull-up voltage input. Control © 2007 Semtech Corp. / Rev. 7, 02/26/07 Serial data out. Loads input data into central register. www.semtech.com E7804 TEST AND MEASUREMENT PRODUCTS PIN Description (continued) Pin # Power Supplies Pin Name Description 11, 28, 75, 92 VCC[0:3] 117 VCC Analog positive power supply to channel high voltage circuitry (+8.25V). Analog positive power supply to high voltage circuitry (+8.25V). 6, 33, 70, 97 VAA[0:3] 113 VAA Analog positive power supply to core circuitry (+5.0V nominal). 13, 26, 77, 90, 115 VEE Analog negative power supply (–5.0V nominal). 17, 22, 81, 86 VDD[0:3] 46, 47, 48 VDD 19, 20, 83, 84 AGND[0:3] 55, 56, 57, 119 DGND 121 VXX Analog positive power supply to channel circuitry (+5.0V nominal). Digital positive power supply to channel comparator outputs (+3.3V nominal). Digital positive power supply for core logic (+3.3V nominal). Analog ground for channels. Digital ground for chip. Switch positive power supply (VCC to VEE + 15V). Miscellaneous 116 EREF 112 ANODE 3, 4, 18, 21, 35, 36, 45, 52, 58, 67, 68, 82, 85, 99, 100, 122 NC © 2007 Semtech Corp. / Rev. 7, 02/26/07 External reference resistor input. REREF should be connected between EREF and AGND. Anode terminal of the on-chip thermal diode string. The pin is ESD protected to VXX, so when measuring the forward drop of the diode string, VXX should be either floating or ≥2V. Cathode of diode string is connected to DGND. No connect pin. No connection is made internally. These pins can be connected to a ground plane to assist in heat removal from the package. www.semtech.com E7804 DHI*[0] DHI[0] DVH[0] DVL[0] CVA[0] CVB[0] NC VXX CTCLV DGND CTCFIV VCC EREF VEE PUV VAA ANODE PMU_OUT EPMUF EPMUS CVB[3] CVA[3] DVL[3] DVH[3] DHI[3] DHI*[3] 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 TEST AND MEASUREMENT PRODUCTS Pin Description (continued) DEN[0] 1 102 DEN[3] DEN*[0] 2 101 DEN*[3] NC 3 100 NC NC 4 99 NC POUT[0] 5 98 POUT[3] VAA[0] 6 97 VAA[3] QB*[0] 7 96 QB*[3] QB[0] 8 95 QB[3] QA*[0] 9 94 QA*[3] QA[0] 10 93 QA[3] VCC[0] 11 92 VCC[3] OPN[0] 12 91 OPN[3] VEE 13 90 VEE DBL[0] 14 89 DBL[3] VIO[0] 15 88 VIO[3] DBH[0] 16 87 DBH[3] VDD[0] 17 86 VDD[3] NC 18 85 NC AGND[0] 19 84 AGND[3] AGND[1] 20 83 AGND[2] NC 21 82 NC VDD[1] 22 81 VDD[2] DBH[1] 23 80 DBH[2] VIO[1] 24 79 VIO[2] DBL[1] 25 78 DBL[2] VEE 26 77 VEE OPN[1] 27 76 OPN[2] VCC[1] 28 75 VCC[2] QA[1] 29 74 QA[2] QA*[1] 30 73 QA*[2] QB[1] 31 72 QB[2] QB*[1] 32 71 QB*[2] VAA[1] 33 70 VAA[2] POUT[1] 34 69 POUT[2] NC 35 68 NC NC 36 67 NC DEN*[1] 37 66 DEN*[2] DEN[1] 38 65 DEN[2] E7804 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 DHI*[1] DHI[1] DVH[1] DVL[1] CVA[1] CVB[1] NC VDD VDD VDD SDOUT SDIN CLKIN NC LOAD RESET* DGND DGND DGND NC CVB[2] CVA[2] DVL[2] DVH[2] DHI[2] DHI*[2] 128 Pin MQFP 14 x 20 mm © 2007 Semtech Corp. / Rev. 7, 02/26/07 www.semtech.com E7804 TEST AND MEASUREMENT PRODUCTS REREF EREF VXX CTCFIV CTCLV EPMUF EPMUS PUV DGND CLKIN SDIN VDD Circuit Description DBH[0] DVH[0] DHI[0] DHI*[0] DEN[0] DEN*[0] 48 110Ω DVL[0] S3[0] VCC[0] VAA[0] S1[0] VDD[0] DBL[0] VIO[0] OPN[0] CVA[0] QA*[0] QA[0] S2[0] A QB[0] B QB*[0] POUT[0] S4[0] ~50KΩ VINP CTC AGND[0] S5[0] VEE[0] CVB[0] S6[0] 2K Control Logic LOAD RESET* DBH[3] DVH[3] DHI[3] DHI*[3] DEN[3] DEN*[3] 48 110Ω S3[3] VCC[3] DVL[3] S1[3] VAA[3] DBL[3] VDD[3] VIO[3] OPN[3] CVA[3] QA*[3] QA[3] S2[3] A QB[3] B QB*[3] ~50KΩ POUT[3] S4[3] VINP AGND[3] CTC CVB[3] S5[3] S6[3] VEE[3] 2K DGND SDOUT S7 ANODE PMU_OUT CONTINUITY TEST CIRCUIT (CTC) (Force I, Limit V) ICTC CONTFIV CONTLV Figure 1. Detailed Block Diagram of E7804 Quad Driver and Window Comparator © 2007 Semtech Corp. / Rev. 7, 02/26/07 www.semtech.com E7804 TEST AND MEASUREMENT PRODUCTS Circuit Description (continued) Introduction The four driver and window comparator channels of the E7804 are shown in Figure 1. Driver Refer to Table 1 showing the modes of operation of the driver. Each channel’s driver states of HiZ, force DVH voltage, force DVL voltage and Open can be controlled either by external input pins or via internal registers and bits programmed through the serial interface. The HiZ/DVH/DVL states are controlled by the differential, external inputs, DHI/DHI* and DEN/DEN*. Each channel also has internal register bits (see Table 2, CH[0:3]_Relays_ &_States registers) SDHI and SDEN that accomplish the same functions as DHI and DEN. The serial register has another bit, SEN (Serial Enable) that allows the SDI and SDEN bits to override the external input pins DHI and DEN. If SEN is a logical “0”, the SDHI and SDEN bits are ignored. The DHI/DHI* and DEN/DEN* inputs are LV_TTL and differential LVDS, LV_PECL compatible. Unused DHI/DHI* or DEN/DEN* must be tied to valid logic levels. Optimizing Driver Waveforms The driver output pin, VIO, will normally be connected to the parametric output pin, POUT, when designed into a system. See the recommended 7804 Hookup drawing farther on in this datasheet. The POUT pin has a lumped capacitance associated with it that will degrade the signal integrity of the driver output waveform if not properly compensated for. The recommendation is to insert ferrite devices between the connection of POUT to VIO to accomplish this. For more details on how and why this approach is used, please read Semtech Application Note #ATE-A3 ATE-to-DUT Interface: Using Ferrites to Replace Relays for Lower Cost and Improved Performance. The driver output impedance has a reactive component to it and will not completely absorb reflections from an © 2007 Semtech Corp. / Rev. 7, 02/26/07 unterminated transmission line. This is common for all drivers, but more so in CMOS drivers than high speed bipolar stages. The figure here shows how transmission line length, here in the form of coaxial cable, will sum the reflections constructively and destructively to alter the peak-to-peak waveform excursions across frequency. More data on this performance and methods for optimizing signal integrity and extending Fmax will be available from Semtech staff. Check with Semtech for the latest information. From the graph below one can see that E7804 driver signals in excess of 150MHz are possible. Driver Levels Each channel’s DVH and DVL are high input impedance voltage inputs which establish the channel driver’s high and low levels. The driver’s output range is –0.2V, +5.2V. DVH to VIO and DVL to VIO offset errors are small, which allow the E7804 to be configured with common input levels to each channel (i.e. DVH[0:3] may be connected together externally, and the same for DVL[0:3]). Driver Source Impedance Drivers feature a self-calibrating source impedance calibrated to match an external resistor, REREF, connected between the EREF pin and analog ground. The source impedance can be chosen to calibrate in the range 48W to 110W using the calculation REREF/100. A driver’s source impedance is affected by its DVH and DVL levels, and therefore needs recalibrating whenever driver levels into the chip are changed. The calibration routine is initiated via the serial interface (see Table 2, calibrate_output_z register). When initiated, all channels are recalibrated in parallel. www.semtech.com E7804 TEST AND MEASUREMENT PRODUCTS Circuit Description (continued) Driver Connect/Disconnect Comparator The driver output connects to the VIO output pin through an internal, normally open switch (S1). Refer to the Functional Block diagram in Figure 1 for Switch S1. This switch can be closed by serially programming the internal register bit for the appropriate channel (see Table 2, CH[0:3]_Relays_ &_States registers) denoted as S1 to a logical “1”. Logical “0” will open the switch. An external pin, OPN[0:3] one input for each channel, is combined with the register bit and will override the internal register bit and Open the S1 switch for the channel. In its low state, the OPN input will not override and force the switch closed however. (It should be noted that OPN=1 will also open S2 to disconnect the channel’s window comparators from the VIO pin.) OPN is a fast way of disconnecting the lower voltage driver and comparator circuitry from the VIO pin. When the driver (and comparator) are disconnected, the voltage at VIO may be in the range of the VEE to VXX power supplies. Each channel’s two comparators, A and B, are combined to form a window comparator to determine whether its input, VINP, is above, below, or in between the two comparator thresholds (CVA and CVB). VINP is tied to the positive input of both comparators. The high voltage disconnect switches permit an external Parametric Measurement Unit (PMU) to be connected to the VIO pin having a maximum range from VEE to VXX volts and up to ±40 mA. This high voltage isolation also permits an external driver to apply up to VXX volts (when switches S1 and S2 are open) for high voltage applications. Each driver may also be connected, internally, to EPMUS in order to measure its output for purposes of calibrating the DVH/L levels via switch S3. OPN=0 Digital Inputs OPN=1 S1 Closed S1 Open X VIO VIO VIO 0 DVL Open Open 1 DVH Open Open 0 0 HiZ Open Open 0 1 HiZ Open Open DEN DHI 1 1 OPN (Open Channel Input) Open (Driver, Comp open/disconnected (see Table 3) DVL (Driver Low) X (Don’t Care) DVH (Driver High) S1 (Driver Output Switch HiZ (High Impedance) Table 1. Driver Modes of Operation © 2007 Semtech Corp. / Rev. 7, 02/26/07 The CVA/B inputs should be driven from low impedance sources. There is an input non-linear current shift of ~15µA when the VINP signal to the comparator crosses polarity with respect to the CVA/B input. If the source impedance is too great, this could affect the accuracy of the compare points. The voltage source’s output impedance should be below 4KW to avoid this. DAC or op amp outputs will have no issue with this. (If resistor dividers are used to create the CVA/B voltages, the voltage should be buffered to prevent this shift.) VINP has a range of –2V, +5.5V, but is restricted to the range of the drivers whenever a comparator is connected to its driver (S1 and S2 switches both closed), namely –0.2V, +5.2V. The comparator outputs are differential LVDS compatible on the QA/QA* and QB/QB* device pins. The output states of the comparators for each channel can also be read back using the serial interface. See Table 3, CH[0:3]_switches_&_states read back instruction for the individual channels. Comparator Levels Each channel’s CVA and CVB are the window comparator’s two threshold levels. CVA and CVB are high impedance voltage inputs that determine the thresholds at which the window comparator changes state. CVA and CVB have a range of –2.0V, +5.5V. Comparator Connect/Disconnect The window comparator input (VINP) connects to the VIO pin through an internal switch (S2). This switch can be closed to VIO by serially programming the internal register bit for the appropriate channel (see Table 2, CH[0:3]_switches_&_states registers) denoted as S2 to a logical “1”. Logical “0” will open the switch from VIO. The comparator input is connected to approximately zero volts www.semtech.com E7804 TEST AND MEASUREMENT PRODUCTS Circuit Description (continued) when disconnected from VIO through ~50KW. To prevent the comparator outputs from switching due to noise when not in use, the CVA/B inputs should be parked >250mV from ground. An external pin, OPN[0:3] one input for each channel, is combined with the register bit, and will override the internal register bit and open the S2 switch for the channel. In its low state, the OPN input will not override and force the switch closed. (It should be noted that OPN=1 will also open S1 to disconnect the channel’s driver output from the VIO pin.) OPN is a fast way of disconnecting the lower voltage driver and comparator circuitry from the VIO pin. When the comparator (and driver) are disconnected, the voltage at the VIO pin may be in the range of the VEE to VXX power supplies. Parametric Measurements The E7804 incorporates a switch matrix which permits an External Parametric Measurement Unit (EPMU) to be connected to one or more channel’s POUT pin. The EPMU range is a function of the VEE and VXX power supplies with ±40 mA capability. Typically, POUT is connected directly to the VIO pin or connected by an inductor so as to minimize the effect of the capacitance at the POUT pin on the driver’s waveform and maximum frequency. The EPMUF and EPMUS inputs are force and sense inputs respectively and connect to the POUT output pin through an internal, normally open, dual switch (S4). There is one dual switch for each channel [0:3]. This switch can be closed by serially programming the internal register bit for the appropriate channel (see Table 2, CH[0:3]_switches_&_states registers) denoted as S4 to a logical “1”. Logical “0” will open the switch. The switch and metal lines for the EMPUF path are sized to accommodate the higher currents (up to 40mA). Do not use EPMUS for higher currents. The EPMUS line is the Kelvin sense path for the external PMU. Continuity Test Circuit The relationship between the CTCFIV input voltage and the resulting current produced by the CTC uses the resistor REREF, as a reference. This gives a good degree of voltage to current accuracy. The relationship is: ICTC = –1.09 * [CTCFIV(V) / REREF(W)]. CTCLV input determines the voltage limit to which CTC may sink current. CTCLV has a range of 0 to –2.0V and is common to all channels’ CTCs. With POUT, connected externally to VIO, then with CTC connected and sinking current, the resultant voltage at VIO can be tested by the channel’s comparators. As this voltage could be as low as –2V, when performing a continuity test, a channel’s driver should be disconnected in order to protect the driver, which has a range of –0.2V to +5.2V. The driver output should be disconnected by opening switch S1 when connecting the CTC to the POUT pin. The CTC connects to the POUT pin through the normally open switch S5. Switch S5 can be closed by serially programming a logical “1” via the internal register for the appropriate channel. See Table 2,”CH[0:3]_switches_&_states write instruction for the individual channels. Note that the CTC’s use the external resistor on the EREF pin to calculate the ICTC test currents. The driver output impedance calibration also uses this reference. If any CTC is switched in-circuit (S5 closed), then attempting to calibrate the driver output impedance will fail and not occur. No change to the calibration values will take place. A typical continuity test will program the CTC’s force current to –100 µA, its voltage limit at –2V, and CVA and CVB at –0.5V and –1.5V, respectively, so as to detect shorts, opens and continuity. typically, in this test, the DUT power supplies are all set to zero volts. The continuity test will determine if each pin of the DUT is connected to the pin channel in the tester without shorts to supplies or ground. 0V Each channel has a programmable Continuity Test Circuit (CTC) which can be switched to its POUT pin. The CTC sinks current in the range –15 to –250 µA as determined by the voltage of the CTCFIV input pin which is common to all CTC’s. CVA = -0.5V CVB = -1.5V CTCLV = -2V Short Continuity Open The tested pins will test good if the resulting voltage from a –100µA load on them results in ~–0.7V. This is the voltage © 2007 Semtech Corp. / Rev. 7, 02/26/07 www.semtech.com E7804 TEST AND MEASUREMENT PRODUCTS Circuit Description (continued) that will be present if the pin substrate or ESD diodes are present. A short can be detected if the resulting voltage is close to zero volts. An Open will be detected if the voltage goes close to –2V. The figure above ilustrates this test with the CVA =– 0.5V and CVB = –1.5V. Pull-Up Resistor Each channel has a 2KW (typ.) pull-up resistor that can be switched to its POUT. The effective pull-up, including resistor and switch, is in the range 1KW to 3KW. PUV is a single input and is buffered at each channel to the pull-up resistors. The buffer and resistor are capable of sourcing or sinking (pull-up or pull-down) currents for 0 to 5V external signals. Programming Functional Description The E7804 features a serial data input programming structure to program the channels functions and switches, assign or invoke Set functions, as well as control more global chip functions such as Reset and Calibration. The majority of the functions are both Read and Write. The serial streams are all 24-bits long and are referred to as “instructions” because the serial streams are built up with address, function, read and select bits as well as data into the 24-bit stream which is clocked serially into the device. The following is a description of the 24-bit instruction stream. Thermal Monitor Data Bits An on-chip thermal diode string of three diodes in series allows accurate die temperature measurements (see diagram below). A bias current of 100 µA is injected through the string, and the measured voltage corresponds to a specific junction temperature with the following equation: Tj[° C] = (0.7195 – VANODE/3) / (0.001967) F S Read/Write Bit Chan/Set PMU_OUT ANODE Bias Current Temperature Coefficient = -5.9mV/oC The ANODE of the diodes may be switched internally to the EPMU bus such that temperature measurements can be performed by the EPMU. The connection to the diode string’s ANODE pin for the EPMU is performed externally by shorting the PMU_OUT pin to the ANODE pin. This external connection is available to make it possible to access the diode string when the device is not powered up. This is useful for calibration purposes of the diode string. The ANODE pin is internally ESD protected in the positive direction to VXX. To use the diode string, VXX needs to either be floating (unpowered operation) or ≥2V. © 2007 Semtech Corp. / Rev. 7, 02/26/07 D12 D11 Address D1 MSB D0 A3 A2 A1 Function A0 F3 F2 F1 F0 LSB Chan/Set Bit Mode Bit Last Bit Written Bit #24 First Bit Written Bit #1 Data: 13 bits This field contains the data to be written into various registers which control the function of the part, or the selected channel(s). Channel/Set Address Select: 1 bit This bit determines whether a single channel or a set of channels is being addressed. 0 = channel direct functions 1 = set of channels Channel/Set Address: 4 bits This field contains the address of the channel or set being operated on. Mode: 1 bit This determines whether the instruction refers to a chiplevel control (such as chip reset), or refers to a channel or set of channels. 0 = chip function 1 = channel or set function www.semtech.com E7804 TEST AND MEASUREMENT PRODUCTS Circuit Description (continued) Read/Write: 1 bit This determines whether a particular address/function is being written or read. (Note that some functions are readonly or write-only). 0 = write a control/data register 1 = read back the contents of a register supplies become stable in order to put the E7804 into a known starting state. After power-up, the RESET* may be exercised or a soft reset instruction may be programmed. Function: 4 bits Data is shifted into the WRITE shift register using CLKIN. The data stored in the shift register will be stored into the E7804 by asserting the LOAD input signal during the 24th CLKIN high-going edge. The LATCH will hold the instruction inside the E7804 for address decoding and data storage into the appropriate on-chip registers. Seven (7) more CLKIN high-going edges should be given after a LOAD for full decode and all instruction executions. Write Serial Data This determines which function within a channel or set is being set or read. Refer to Figure 2 for a block diagram of the Write and Read logic for the serial programming. The serial data is input into the device SDIN pin. The data at SDIN is clocked in on the high-going edge of the CLKIN input signal. The data at the SDOUT pin is clocked out on the low-going edge of the CLKIN input signal for ease of “daisy chaining” multiple devices. Refer to Figure 3 for a timing diagram of the writing operation. Notice that the SDOUT data that is clocked out on the low-going edge of CLKIN is a bit for bit representation of the data that had been shifted into the E7804 24 clock edges beforehand. This echoing of the data allows the user to “daisy chain” multiple E7804 devices to minimize the number of serial data streams that need to be implemented. The compromise is the length of time it takes to clock through all the 24-bit instructions for all the devices in the chain. RESET* There is a single input pin to the entire E7804 chip that will clear all on-chip registers and open all on-chip switches. This input pin, RESET*, is active low and is asynchronous, not requiring any CLKIN transitions to operate. It is advised that, upon power-up in a system, this pin is either held low or cycled low for a brief time while the system and power DATA D[20:24] D[5:17] "Don't Care" D[0:4] SIN READBACK 24-Bit Shift Register SOUT – READ RESET RESET* Read Bit Only True for 24 Clocks CLKIN 13 10 DATA ADR CK SDOUT READBIT LATCH RESET LOAD 24 Q SDIN WRITE 24-Bit Shift Register SOUT – WRITE RESET Figure 2. Block Diagram of Read and Write Shift Registers © 2007 Semtech Corp. / Rev. 7, 02/26/07 10 www.semtech.com E7804 TEST AND MEASUREMENT PRODUCTS Circuit Description (continued) First Instruction "N" SDIN Bit 22N Bit 23N Instruction "N+1" Bit 0N+1 Bit 1N+1 Bit 22N+1 Instruction "N+2" Bit 23N+1 Bit 0N+2 Bit 1N+2 Bit 22N+2 Bit 23N+2 CLKIN LOAD SDOUT Bit 0N Bit 22N Bit 23N Instruction "N" Echo Bit 0N+1 Bit 1N+1 Bit 21N+1 Bit 22N+1 Bit 23N+1 Bit 0N+2 Instruction "N+1" Echo Figure 3. Serial Data Programming - Write Instruction Figure 4 depicts two topologies to serially read and write multiple E7804 devices on a single assembly. Figure 4a daisy chains the serial I/O (SDOUT to SDIN) pins, and the CLKIN and LOAD functions are common for all the E7804s. This topology uses a minimum amount of I/O from the control logic. However, in order to read or write the E7804’s an instruction string of 24 x N bits long needs to be created, clocked all the way through the devices, and a parallel LOAD signal asserted for all devices. NO_OP instructions may be used for the devices that are not being addressed. Figure 4b shows a topology from the control logic that offers rapid programming time and complete independence. This topology relies on enough I/O signals being available from the control logic. Notice that the CLKIN pins are still all common because independence is allowed by the individual LOAD signals to each E7804. If it is determined that readback from the E7804s are not necessary, the control logic can be further simplified. Readback is not necessary for the operation of the E7804. It is offered as a good diagnostic tool and possible programming aid. Read Serial Data stream and written to the E7804. The instruction stream must be properly constructed for address and select bits to insure that the proper register will be accessed for readback. The data bits D0:D12 in this Read instruction are Don’t_Care. Refer to Figure 5 for a timing diagram of the readback process and Figure 2 for a block diagram of how the readback operation works. Once the LOAD signal is asserted on the 24th high-going CLKIN edge to latch in the READ instruction for a particular address, the internal READ line will assert true and switch the SDOUT pin to output data from the internal readback shift register. The readback data will immediately start to output from the SDOUT pin on the low-going edge of CLKIN. The readback will continue for 24 bits. The first 5 bits of data readback should be ignored. The next 13 bits will be the requested register’s readback data. Finally, the last 6 bits are logical zeros. While clocking out the readback data, a new instruction can be simultaneously clocked in at SDIN. At the conclusion of the 24-bit readback, the SDOUT data will revert back to echoing the SDIN data shifted by 24 clocks. In order to readback data, an instruction is constructed with the Read_Bit set to a logical ”1” in the instruction © 2007 Semtech Corp. / Rev. 7, 02/26/07 11 www.semtech.com E7804 TEST AND MEASUREMENT PRODUCTS Circuit Description (continued) SDIN SDIN CLKIN CLKIN CLKOUT LOAD E7804 #1 SOUT1 LOAD1 SDOUT LOAD E7804 #1 SDOUT SIN1 SOUT SDIN SDIN CLKOUT CLKIN SOUT2 CLKIN LOADOUT LOAD LOAD2 LOAD SIN DIGITAL ASIC E7804 #2 SIN2 SDOUT E7804 #2 SDOUT SOUT"N" SDIN LOAD"N" CLKIN SIN"N" LOAD SDIN CLKIN LOAD DIGITAL ASIC E7804 "N" SDOUT E7804 "N" SDOUT a. Minimum # of Control Lines from ASIC b. Independent Control of Each E7804 Figure 4. Serial Control of Multiple E7804s Figure 5 depicts the conclusion of a Read instruction being written to the E7804. The first LOAD pulse straddling the rising edge of CLKIN latches in the Read instruction, echoing at SDOUT stops, and the readback of the register begins. After 24 low-going clocks, the data at SDOUT resumes echoing the written data at SDIN. Even without the second LOAD pulse, the echoing will begin. Figure 5 depicts a Write instruction following the Read. This could be another Read instruction, in which case the echoing of SDIN would not begin as indicated. Instead, another sequence of 24 readback bits would begin. The readback data format and address are defined in Table 3. The Read operation will continue for 24 low-going clock edges. The SDOUT will begin outputting data from the write shift register after the 24th low-going clock edge. © 2007 Semtech Corp. / Rev. 7, 02/26/07 12 Address Map Table 2 shows the Write Table and Address Map. Across the top of the table are the 24 bits of data denoted as Bit #0 through Bit #23. Hex notation is also provided as well as the binary positions. The instruction is constructed of 13 Data bits, 8 address bits, 2 select bits and a read bit. Figure 3 shows the bit pattern in the write instructions. The instructions are separated into 3 main groups. The Chip Functions, the Channel Functions and the Set Functions. Each instruction has a Register Name associated with it. In the pages following Table 2 are descriptions of each of the register names and, where applicable, a bit-by-bit description of the data. www.semtech.com E7804 TEST AND MEASUREMENT PRODUCTS Circuit Description (continued) Chip Functions Channel Functions The Chip Functions group of instructions controls chip functions that are global in scope and not associated with a particular channel. Examples of these functions are the chip identification number and revision, the Reset function for chip wide reset, and initiation of calibration. The Channel Functions group of instructions address the functionality of individual registers and bits that are particular to specific channels of the E7804. Driver states, channel switches, calibration factors and set assignments are included in this group. Function Address – Instructions in the group are denoted by this set of bits. Read Bit–– Set to “1” only if user intends to read back a register. Chan Bit – Set to a “0” since this instruction group is not channel related. Chan/Set Adr – These 4 bits are “don’t care”. Since these would select either a channel or set number, and these are Chip Functions, they don’t apply. Set Select Bit – This bit is a “don’t care” for the Chip Functions group. Function Address – These bits denote which function of the particular channels is being addressed. Read Bit–– Set to “1” only if user intends to read back a register. Chan Bit – Set to a “1” because these instructions relate to specific channel registers. Chan/Set Adr – These bits will denote which channel is being addressed for the particular function. Valid range is 0x0 through 0x3 for the E7804. Set Select Bit – This bit is set to a “0” because this is the Channel Functions group. Read Instruction SDIN Bit 22 Bit 23 Echo Begins 24 Clocks Later Next Instruction A Write Instruction Bit 0 Bit 1 Bit 22 Bit 23 Bit 0 Bit 1 CLKIN LOAD SDOUT READ Bit 0 READ Bit 4 First 5 Bits Ignore READ Bit 5 READ Bit 17 13 Bits Valid Readback Data READ Bit 18 READ Bit 23 Bit 0 ECHO 6 Bits Zero Fill 24 Bits Readback Figure 5. Serial Data Programming - Readback Sequence © 2007 Semtech Corp. / Rev. 7, 02/26/07 13 www.semtech.com E7804 TEST AND MEASUREMENT PRODUCTS Circuit Description (continued) Set Functions Programming the Driver’s Source Impedance Set Functions are a group of 8 instructions corresponding to the 8 available Sets that will configure any channel that has been assigned to that Set. The Set Functions are writeonly, but the effects of a Set instruction can be read back from the individual channel’s registers. The Set is given control of any channel’s driver states or switches. The Set concept is a way of programming all channels on any E7804 that have been assigned to that particular SET to a particular configuration with one instruction write cycle. Figure 1 shows that each driver’s source impedance is programmable over a 48W to 110W range so as to match the impedance of the transmission line connecting VOP to the Device Under Test (DUT). The driver’s source impedance is automatically programmed to match REREF/100, where REREF is the external reference resistor connected to the EREF pin. Function Address – These addresses should all be “0”. Read Bit–– Set to “0” since there is no readback for set instructions. Chan Bit – Set to a “1”. Chan/Set Adr – These bits will denote which set is being programmed. Valid set values are 0x0 through 0x7 corresponding to the eight valid SETs. Set Select Bit – This bit is a “1” because this is the SET Functions group. SET Programming Referring to Table 2, a channel’s SETs Register may be programmed via the CH[0:3]_set_assign instructions. This is an independent 8-bit register per channel which determines the SETs to which the channel belongs. A channel may belong to none, one, or any combination of up to 8 sets. © 2007 Semtech Corp. / Rev. 7, 02/26/07 14 Initiating the source match auto-calibration sequence is a “chip function” (Table 2). Auto-calibration is performed on all channels in parallel. The Driver’s source impedance is affected by its DVH and DVL levels and, therefore, auto-calibration should be initiated whenever driver levels are changed. Following auto-calibration, a driver’s source impedances match (REREF/100) W when its output is at (DVH + DVL) / 2. If the output voltages of the driver are reprogrammed, then it is advised to recalibrate to maintain the best accuracy. Calibration will occur after writing the global function instruction calibrate_output_z. Calibration requires an additional 576 clock edges from CLKIN to complete the process. This is 24 instructions worth of clocks. Instructions for the device undergoing calibration may be any valid instruction except that which connects the CTC output to POUT, or simply applying the clocks without LOAD’ing instructions is also valid. At the end of the process, the new, calibrated output impedances will be applied to the driver output stage. The driver may be in the enabled or disabled state. If enabled, there could be a noticable perturbation on the output. www.semtech.com E7804 TEST AND MEASUREMENT PRODUCTS Circuit Description (continued) Bit # Hex Multiplier Binary Position 23 8 22 21 010x0000 4 2 20 19 1 8 18 17 01x0000 4 Register Name CHIP FUNCTIONS Write Only = Read Only = Read/Write = 2 16 15 1 8 14 13 0x1000 4 2 12 11 1 8 2 WO RO R/W (MSB) 0 D12 D0 D11 D10 5 0x0010 4 3 1 8 4 2 1 8 D8 D7 D6 D5 D4 D3 D2 D1 (LSB) 0 0 0 0 0 0 0 0 0 2 1 0x0001 4 2 0 1 Function Adr Set Sel Chan Read Bit Bit A3 A2 A1 A0 F3 F2 F1 F0 WO 0 0 0 0 0 0 0 0 0 0 0 W1 RO (see Readback Table for data) x x x x x 0 1 0 0 0 1 W2 chip_revision RO (see Readback Table for data) x x x x x 0 1 0 0 1 0 W3 calibrate_output_Z R/W CAL x x x x x 0 0/1 0 0 1 1 W4 S7 x x x x x 0 0/1 0 1 0 0 W5 x x x x x 0 0/1 0 1 0 1 W6 x x x x x 0 0/1 0 1 1 0 W8 x x x x x 0 0/1 x x x x x 0 0 1 1 1 1 W10 R/W R/W diagnostic (reserved) R/W 0 6 no_op chip_switches 0 7 chip_id global_calib_factor 0 D9 8 Chan/Set Adr 0x00 to 0xFF Z SETS ALL 0111 - 1110 W9 reset WO CH0_relays_&_states R/W INT SDEN SDHI S6 S5 S4 S3 S2 S1 0 0 0 0 0 1 0/1 0 0 0 0 W11 CH1_relays_&_states R/W INT SDEN SDHI S6 S5 S4 S3 S2 S1 0 0 0 0 1 1 0/1 0 0 0 0 W12 CH2_relays_&_states R/W INT SDEN SDHI S6 S5 S4 S3 S2 S1 0 0 0 1 0 1 0/1 0 0 0 0 W13 CH3_relays_&_states R/W INT SDEN SDHI S6 S5 S4 S3 S2 S1 0 0 0 1 1 1 0/1 0 0 0 0 W14 1 0/1 0 0 0 0 W15 reserved CHANNEL FUNCTIONS 4 Data Bits reserved 0100 - 1111 0 CH0_DVH_calib_Z R/W impedance calibration code 0 0 0 0 0 1 0/1 0 0 0 1 W16 CH1_DVH_calib_Z R/W impedance calibration code 0 0 0 0 1 1 0/1 0 0 0 1 W17 CH2_DVH_calib_Z R/W impedance calibration code 0 0 0 1 0 1 0/1 0 0 0 1 W18 CH3_DVH_calib_Z R/W impedance calibration code 0 0 0 1 1 1 0/1 0 0 0 1 W19 1 0/1 0 0 0 1 W20 reserved impedance calibration code 0 0 0 0 0 1 0/1 0 0 1 0 W21 R/W impedance calibration code 0 0 0 0 1 1 0/1 0 0 1 0 W22 R/W impedance calibration code 0 0 0 1 0 1 0/1 0 0 1 0 W23 R/W impedance calibration code 0 0 0 1 1 1 0/1 0 0 1 0 W24 1 0/1 0 0 1 0 W25 1 0/1 0 0 1 1 W26 CH0_DVL_calib_Z R/W CH1_DVL_calib_Z CH2_DVL_calib_Z CH3_DVL_calib_Z reserved CH0_sw_calib_Z 0100 - 1110 0 0100 - 1110 0 R/W impedance calibration code 0 0 0 0 0 CH1_sw_calib_Z R/W impedance calibration code 0 0 0 0 1 1 0/1 0 0 1 1 W27 CH2_sw_calib_Z R/W impedance calibration code 0 0 0 1 0 1 0/1 0 0 1 1 W28 CH3_sw_calib_Z R/W impedance calibration code 0 0 0 1 1 1 0/1 0 0 1 1 W29 1 0/1 0 0 1 1 W30 reserved SET FUNCTIONS 10 9 0x0100 0100 - 1110 0 CH0_set_assign R/W set7 set6 set5 set4 set3 set2 set1 set0 0 0 0 0 0 1 0/1 1 1 1 1 W31 CH1_set_assign R/W set7 set6 set5 set4 set3 set2 set1 set0 0 0 0 0 1 1 0/1 1 1 1 1 W32 CH2_set_assign R/W set7 set6 set5 set4 set3 set2 set1 set0 0 0 0 1 0 1 0/1 1 1 1 1 W33 CH3_set_assign R/W set7 set6 set5 set4 set3 set2 set1 set0 0 0 0 1 1 1 0/1 1 1 1 1 W34 Set0_relays_&_states W0 INT SDEN SDHI S6 S5 S4 S3 S2 S1 1 0 0 0 0 1 0 0 0 0 0 W35 Set1_relays_&_states W0 INT SDEN SDHI S6 S5 S4 S3 S2 S1 1 0 0 0 1 1 0 0 0 0 0 W36 Set2_relays_&_states W0 INT SDEN SDHI S6 S5 S4 S3 S2 S1 1 0 0 1 0 1 0 0 0 0 0 W37 Set3_relays_&_states W0 INT SDEN SDHI S6 S5 S4 S3 S2 S1 1 0 0 1 1 1 0 0 0 0 0 W38 Set4_relays_&_states W0 INT SDEN SDHI S6 S5 S4 S3 S2 S1 1 0 1 0 0 1 0 0 0 0 0 W39 Set5_relays_&_states W0 INT SDEN SDHI S6 S5 S4 S3 S2 S1 1 0 1 0 1 1 0 0 0 0 0 W40 Set6_relays_&_states W0 INT SDEN SDHI S6 S5 S4 S3 S2 S1 1 0 1 1 0 1 0 0 0 0 0 W41 Set7_relays_&_states W0 INT SDEN SDHI S6 S5 S4 S3 S2 S1 1 0 1 1 1 1 0 0 0 0 0 W42 1 0 0 0 0 0 W43 reserved 1 1000 - 1111 Table 2 . E7804 Instruction Table/Address Map © 2007 Semtech Corp. / Rev. 7, 02/26/07 15 www.semtech.com E7804 TEST AND MEASUREMENT PRODUCTS Circuit Description (continued) CHANNEL FUNCTIONS GLOBAL FUNCTIONS Register Name Bit # 23 22 21 20 19 18 17 TRAILING 0's MSB 16 15 14 13 12 11 10 VALID DATA READBACK 9 8 7 6 5 4 3 2 1 0 LEADING BITS LSB Notes chip_id RO 0 0 0 0 0 1 1 1 1 0 0 1 1 1 1 1 0 0 X X X X X X R1 1 chip_revision RO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X X X X X X R2 2 calibrate_output_Z R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAL X X X X X X R3 chip_switches R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 S7 X X X X X X R4 8-bit global cal factor global_calib_factor R/W 0 0 0 0 0 0 0 0 0 0 X X X X X X R5 diagnostic (reserved) R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Z X X X X X X R6 CH0_switches_&_states R/W 0 0 0 0 0 0 0 QA QB SEN SDEN SDHI S6 S5 S4 S3 S2 S1 X X X X X X R7 CH1_switches_&_states R/W 0 0 0 0 0 0 0 QA QB SEN SDEN SDHI S6 S5 S4 S3 S2 S1 X X X X X X R8 CH2_switches_&_states R/W 0 0 0 0 0 0 0 QA QB SEN SDEN SDHI S6 S5 S4 S3 S2 S1 X X X X X X R9 CH3_switches_&_states R/W 0 0 0 0 0 0 0 QA QB SEN SDEN SDHI S6 S5 S4 S3 S2 S1 X X X X X X R10 CH0_DVH_calib_Z R/W 0 0 0 0 0 0 0 0 0 0 8-bit impedance calibration code X X X X X X R11 CH1_DVH_calib_Z R/W 0 0 0 0 0 0 0 0 0 0 8-bit impedance calibration code X X X X X X R12 CH2_DVH_calib_Z R/W 0 0 0 0 0 0 0 0 0 0 8-bit impedance calibration code X X X X X X R13 CH3_DVH_calib_Z R/W 0 0 0 0 0 0 0 0 0 0 8-bit impedance calibration code X X X X X X R14 CH0_DVL_calib_Z R/W 0 0 0 0 0 0 0 0 0 0 8-bit impedance calibration code X X X X X X R15 CH1_DVL_calib_Z R/W 0 0 0 0 0 0 0 0 0 0 8-bit impedance calibration code X X X X X X R16 CH2_DVL_calib_Z R/W 0 0 0 0 0 0 0 0 0 0 8-bit impedance calibration code X X X X X X R17 CH3_DVL_calib_Z R/W 0 0 0 0 0 0 0 0 0 0 8-bit impedance calibration code X X X X X X R18 CH0_sw_calib_Z R/W 0 0 0 0 0 0 0 0 0 0 0 7-bit impedance calibration code X X X X X X R19 CH1_sw_calib_Z R/W 0 0 0 0 0 0 0 0 0 0 0 7-bit impedance calibration code X X X X X X R20 CH2_sw_calib_Z R/W 0 0 0 0 0 0 0 0 0 0 0 7-bit impedance calibration code X X X X X X R21 0 7-bit impedance calibration code X X X X X X R22 CH3_sw_calib_Z R/W 0 0 0 0 0 0 0 0 0 0 CH0_set_assign R/W 0 0 0 0 0 0 0 0 0 0 set7 set6 set5 set4 set3 set2 set1 set0 X X X X X X R23 CH1_set_assign R/W 0 0 0 0 0 0 0 0 0 0 set7 set6 set5 set4 set3 set2 set1 set0 X X X X X X R24 CH2_set_assign R/W 0 0 0 0 0 0 0 0 0 0 set7 set6 set5 set4 set3 set2 set1 set0 X X X X X X R25 CH3_set_assign R/W 0 0 0 0 0 0 0 0 0 0 set7 set6 set5 set4 set3 set2 set1 set0 X X X X X X R26 Notes: 1 2 Device part number = 7804 decimal = 0x1E7C hex Rev A = 0x000, B = 0x001, … Table 3 . Registers’ Readback Bit Sequences © 2007 Semtech Corp. / Rev. 7, 02/26/07 16 www.semtech.com E7804 TEST AND MEASUREMENT PRODUCTS Circuit Description (continued) Chip Functions Register Name no_op 0x00 Function Address Channel/Set Address don't care 0 Channel Select Bit Default Value 0 0000 0000 0000 0x00 Description This bit stream is used as a null stream. No operation will result if shifted in and a LOAD is executed. It is useful if multiple devices are connected in serial arrangement and a chip is not being addressed, but a parallel LOAD will occur for all devices on the serial bus. Set Select Bit Mode 0 or 0 Write Only Register Name chip_id 0x01 Function Address Channel/Set Address don't care 0 Channel Select Bit Default Value 1 1110 0111 1100 0x1E7C Description This identifies the device part number, decimal equivalent is 7804. It is a read only register. Register Name chip_revision 0x02 Function Address Channel/Set Address don't care 0 Channel Select Bit Set Select Bit Mode Set Select Bit Mode 0 or 1 Read Only 0 or 1 Read Only Default Value 0 0000 0000 0000 Description This identifies the device die revision number. The first revision is decimal 0, the second will be decimal 1, etc. It is a read only register. Register Name calibrate_output_z 0x03 Function Address Channel/Set Address don't care 0 Channel Select Bit Default Value 0 0000 0000 0000 0x00 Description Writing to the LSB of this address will initiate a chip-wide calibration of the output impedances of the drivers. The internal state machine that performs the calibrations will require 21 microseconds for complete calibration of all channels. This is 30 instructions (x24 clocks) clocked at 33 MHz CLKIN. Because the calibration and Continuity Test Circuits (CTC) both share the EREF pin, z_calibration cannot occur if any CTC is switched into operation using S5. D0 – writing a one to this bit will initiate the calibration process. Once calibration is completed, this bit will readback as a 0. Register Name chip_switches 0x04 Function Address Channel/Set Address don't care 0 Channel Select Bit Default Value 0 0000 0000 0000 0x00 Description This register is used to switch non-channel specific switches. Set Select Bit Mode Set Select Bit Mode 0 or 1 Read/Write 0 or 1 Read/Write D0 – writing a one to this bit will close the S7 switch. The S7 switch is a dual pole switch that connects the EPMUS and the EPMUF signals to the PMU_OUT pin. The primary use is when PMU_OUT is externally shorted to the temperature diode ANODE pin. Closing this switch will allow the external PMU to connect to the temperature diode string on an individual E7804 to perform die temperature measurements. Register Name global_calib_factor 0x05 Function Address Channel/Set Address don't care 0 Channel Select Bit Default Value 0x00 0 0000 1111 1111 Set Select Bit Mode 0 or 1 Read/Write This register holds the eight-bit calibration factor based upon the resistor value on the EREF pin. The value in this register is used in calculating the output impedances of the driver outputs during calibration. After RESET it will be 0xFF. D0-D7 – the eight-bit value of the calibration factor. D0=LSB. 0x06 0 or 1 Register Name diagnostic Function Address Set Select Bit Read/Write Channel/Set Address don't care Mode 0 Channel Select Bit Description Default Value 0 0000 0000 0000 Description This register is used for test access. Do not write to this register. 0x00 Register Name reset 0x0F Function Address Channel/Set Address don't care 0 Channel Select Bit Default Value 0 0000 0000 0000 0x00 Description This register is used for programmable (soft) reset of the device. D0 – ALL – writing a one to this bit will perform a soft reset of the entire chip. It is wire OR'd with the external RESET* pin. The ALL reset function requires 7 clock cycles after this bit is latched in by the LOAD signal. The RESET ALL instruction will clear the SDIN and SDOUT shift registers. It is advised to follow a RESET ALL instruction with a NO_OP instruction. D1 – SETS – writing a one to this bit will perform a soft reset of all the set assignments for all the channels of the device. This SET function function requires 5 clock cycles after this bit is latched in by the LOAD signal. © 2007 Semtech Corp. / Rev. 7, 02/26/07 Set Select Bit Mode 17 0 or 1 Write Only www.semtech.com E7804 TEST AND MEASUREMENT PRODUCTS Circuit Description (continued) Channel Functions Channel Relay and States Registers Register Name CH0_switches_&_states Function Address 0x00 Channel/Set Address 0x00 Channel Select Bit 1 Set Select Bit Mode Default Value 0 0000 0000 0000 0x00 Description This register is used for controlling the Channel_0 (CH0) switches. Bits are also present to control the CH0 driver state and read back the states of the CH0 comparator outputs. The comparator output states are indicated above as unknown unless the input voltage relationships are known. D0 – S1 – writing a one to this bit will close the switch that connects the driver output to the channels VIO pin. 0 Read/Write D1 – S2 – writing a one to this bit will close the switch that connects the window comparator input to the channel's VIO pin. D2 – S3 – writing a one to this bit will close the switch that connects the driver output to the external PMU sense line (EPMUS) for purposes of system diagnostics. D3 – S4 – writing a one to this bit will close the switches that connect both the external PMU bus sense (EPMUS) and force (EPMUF) lines to the channel's POUT pin. D4 – S5 – writing a one to this bit will close the switch that connects the continuity test circuit (CTC) to the channel's POUT pin. If any channel has S5 closed, then output impedance calibration cannot occur. D5 – S6 – writing a one to this bit will close the switch that connects the pull-up resistor and voltage to the channel's POUT pin. D6 – SDHI (Serial Data Hi) – writing a logical one to this bit will force the channel's driver to output the DVH voltage. Writing a zero to this bit will force the driver to output the DVL voltage. The SDHI bit will only have effect if the SEN bit (D8) in this register is set to a logical one, allowing the SDHI bit to override the state of the external DHI signal to this channel's driver. D7 – SDEN (Serial Data Enable) – writing a logical one to this bit will enable the channel's driver to output either DVH or DVL (based on the SDHI bit). Writing a zero to this bit disables the driver output to high impedance. The SDEN bit will only have effect if the SEN bit (D8) in this register is set to a logical 1, allowing the SDEN bit to override the state of the external DEN signal to this channel's driver. D8 – SEN (Serial Enable) – writing this bit to a logical one will allow the D6 and D7 bits in this register override the external driver control signals DHI and DEN. D9 – QB – this bit is a Read Only bit that is the state of the channel's comparator B output. Writing to this bit will have no effect. D10 – QA – this bit is a Read Only bit that is the state of the channel's comparator A output. Writing to this bit will have no effect. Register Name CH1_switches_&_states Function Address 0x00 Channel/Set Address 0x01 Channel Select Bit 1 Default Value 0 0000 0000 0000 0x00 Description This register is used for controlling the Channel_1 (CH1) switches. Bits are also present to control the CH1 driver state and read back the states of the CH1 comparator outputs. See the bit definitions above for the CH0_relay_&_switches register. Register Name CH2_switches_&_states Function Address 0x00 Channel/Set Address 0x02 Channel Select Bit 1 Set Select Bit Mode Set Select Bit Mode 0 Read/Write 0 Read/Write Default Value 0 0000 0000 0000 Description This register is used for controlling the Channel 2 (CH2) switches. Bits are also present to control the CH2 driver state and read back the states of the CH2 comparator outputs. See the bit definitions above for the CH0_relay_&_switches register. Register Name CH3_switches_&_states Function Address 0x00 Channel/Set Address 0x03 Channel Select Bit 1 Default Value 0 0000 0000 0000 0x00 Description This register is used for controlling the Channel 3 (CH3) switches. Bits are also present to control the CH3 driver state and read back the states of the CH3 comparator outputs. See the bit definitions above for the CH0_relay_&_switches register. © 2007 Semtech Corp. / Rev. 7, 02/26/07 18 Set Select Bit Mode 0 Read/Write www.semtech.com E7804 TEST AND MEASUREMENT PRODUCTS Circuit Description (continued) Channel Functions (continued) Channel Calibration Registers _ DVH Register Name CH0_DVH_calib_z Function Address 0x01 Channel/Set Address 0x00 Channel Select Bit 1 Default Value 0x00 0 0000 0000 0000 Set Select Bit Mode 0 Read/Write Description This register is used to store the calibration 8-bit code for CH0's driver impedance to DVH. Data is written internally after a chipwide calibration of the output impedances has occurred. User can read back this data or write different data into the register. Register Name CH1_DVH_calib_z Function Address 0x01 Set Select Bit 0 Channel/Set Address 0x01 Mode Read/Write Channel Select Bit 1 Default Value 0 0000 0000 0000 Description This register is used to store the calibration 8-bit code for CH1's driver impedance to DVH. Data is written internally after a chipwide calibration of the output impedances has occurred. User can read back this data or write different data into the register. Register Name CH2_DVH_calib_z 0x00 Function Address 0x01 Channel/Set Address 0x02 Channel Select Bit 1 Set Select Bit Mode 0 Read/Write Default Value 0 0000 0000 0000 Description This register is used to store the calibration 8-bit code for CH2's driver impedance to DVH. Data is written internally after a chipwide calibration of the output impedances has occurred. User can read back this data or write different data into the register. Register Name CH3_DVH_calib_z Function Address 0x01 Channel/Set Address 0x03 Channel Select Bit 1 Default Value 0 0000 0000 0000 0x00 Description This register is used to store the calibration 8-bit code for CH3's driver impedance to DVH. Data is written internally after a chipwide calibration of the output impedances has occurred. User can read back this data or write different data into the register. Set Select Bit Mode 0 Read/Write Channel Calibration Registers _ DVL Register Name CH0_DVL_calib_z Function Address 0x01 Channel/Set Address 0x00 Channel Select Bit 1 Set Select Bit Mode Default Value 0 0000 0000 0000 0x00 Description This register is used to store the calibration 8-bit code for CH0's driver impedance to DVL Data is written internally after a chipwide calibration of the output impedances has occurred. User can read back this data or write different data into the register. 0 Read/Write Register Name CH1_DVL_calib_z Default Value Description Function Address 0x01 Set Select Bit 0 Channel/Set Address 0x01 Mode Read/Write Channel Select Bit 1 0 0000 0000 0000 0x00 This register is used to store the calibration 8-bit code for CH1's driver impedance to DVL Data is written internally after a chipwide calibration of the output impedances has occurred. User can read back this data or write different data into the register. Register Name CH2_DVL_calib_z Default Value Description Function Address 0x01 Set Select Bit 0 Channel/Set Address 0x02 Mode Read/Write Channel Select Bit 1 0 0000 0000 0000 0x00 This register is used to store the calibration 8-bit code for CH2's driver impedance to DVL Data is written internally after a chipwide calibration of the output impedances has occurred. User can read back this data or write different data into the register. Register Name CH3_DVL_calib_z Default Value Description Function Address 0x01 Set Select Bit 0 Channel/Set Address 0x03 Mode Read/Write Channel Select Bit 1 0 0000 0000 0000 0x00 This register is used to store the calibration 8-bit code for CH3's driver impedance to DVL Data is written internally after a chipwide calibration of the output impedances has occurred. User can read back this data or write different data into the register. © 2007 Semtech Corp. / Rev. 7, 02/26/07 19 www.semtech.com E7804 TEST AND MEASUREMENT PRODUCTS Circuit Description (continued) Channel Functions (continued) Channel Set Assignment Registers Register Name CH0_set_assign Function Address 0x01 Channel/Set Address 0x00 Channel Select Bit 1 Default Value 0 0000 0000 0000 0x00 Description This register is used to assign CH0 to any or no "SETs". A logical 1 in the bit position will assign CH0 to respond to global commands for the corresponding set. Bit # Set Select Bit Mode 0 Read/Write D7 D6 D5 D4 D3 D2 D1 D0 set7 set6 set5 set4 set3 set2 set1 set0 Register Name CH1_set_assign Function Address 0x01 Channel/Set Address 0x01 Channel Select Bit 1 Set Select Bit Mode Default Value 0 0000 0000 0000 0x00 Description This register is used to assign CH1 to any or no "SETs". A logical 1 in the bit position will assign CH0 to respond to global commands for the corresponding set. See bit positions in CH0_set assign register description above. Set Select Bit Mode 0 Read/Write Register Name CH2_set_assign Function Address 0x01 Channel/Set Address 0x02 Channel Select Bit 1 Default Value 0 0000 0000 0000 0x00 Description This register is used to assign CH2 to any or no "SETs". A logical 1 in the bit position will assign CH0 to respond to global commands for the corresponding set. See bit positions in CH0_set assign register description above. Register Name CH3_set_assign Function Address 0x01 Channel/Set Address 0x03 Channel Select Bit 1 Default Value 0 0000 0000 0000 0x00 Description This register is used to assign CH3 to any or no "SETs". A logical 1 in the bit position will assign CH0 to respond to global commands for the corresponding set. See bit positions in CH0_set assign register description above. © 2007 Semtech Corp. / Rev. 7, 02/26/07 20 Set Select Bit Mode 0 Read/Write 0 Read/Write www.semtech.com E7804 TEST AND MEASUREMENT PRODUCTS Circuit Description (continued) Set Functions Register Name Set0_switches_&_states Function Address 0x00 Channel/Set Address 0x00 Channel Select Bit 1 Set Select Bit Mode Default Value 0 0000 0000 0000 0x00 Description This register is used for controlling the Set_0 (CH0) switches on any channel that has been assigned to Set_0. Bits are also present to control the channels' driver states. D0 – S1 – writing a one to this bit will close the switch that connects the driver output to the channel's VIO pin. 1 Write Only D1 – S2 – writing a one to this bit will close the switch that connects the window comparator input to the channel's VIO pin. D2 – S3 – writing a one to this bit will close the switch that connects the driver output to the external PMU sense line (EPMUS) for purposes of system diagnostics. D3 – S4 – writing a one to this bit will close the switches that connect both the external PMU bus sense (EPMUS) and force (EPMUF) lines to the channel's POUT pin. D4 – S5 – writing a one to this bit will close the switch that connects the continuity test circuit (CTC) to the channel's POUT pin. D5 – S6 – writing a one to this bit will close the switch that connects the pull-up resistor and voltage to the channel's POUT pin. D6 – SDHI (Serial Data Hi) – writing a logical one to this bit will force the channel's driver to output the DVH voltage. Writing a zero to this bit will force the driver to output the DVL voltage. The SDHI bit will only have effect if the SEN bit (D8) in this register is set to a logical one, allowing the SDHI bit to override the state of the external DHI signal to this channel's driver. D7 – SDEN (Serial Data Enable) – writing a logical one to this bit will enable the channel's driver to output either DVH or DVL (based on the SDHI bit). Writing a zero to this bit disables the driver output to high impedance. The SDEN bit will only have effect if the SEN bit (D8) in this register is set to a logical 1, allowing the SDEN bit to override the state of the external DEN signal to this channel's driver. D8 – SEN (Serial Enable) – writing this bit to a logical one will allow the D6 and D7 bits in this register override the external driver control signals DHI and DEN. Register Name Set1_switches_&_states Function Address 0x00 Channel/Set Address 0x01 Channel Select Bit 1 Set Select Bit Mode Default Value 0 0000 0000 0000 0x00 Description This register is used for controlling the Set_0 (CH0) switches on any channel that has been assigned to Set_1. Bits are also present to control the channels' driver states. See the bit definitions to the Set0_relays_&_states for bit definitions. 1 Write Only Sets 2 through 6 Register Name Set7_switches_&_states Function Address 0x00 Channel/Set Address 0x01 Channel Select Bit 1 Default Value 0 0000 0000 0000 0x00 Description This register is used for controlling the Set_7 (CH0) switches on any channel that has been assigned to Set_7. Bits are also present to control the channels' driver states. See the bit definitions to the Set0_relays_&_states for bit definitions. © 2007 Semtech Corp. / Rev. 7, 02/26/07 21 Set Select Bit Mode 1 Write Only www.semtech.com E7804 TEST AND MEASUREMENT PRODUCTS Application Information PUV EPMUF/S REREF ANODE PMU_OUT VAA 4 DVL/H, CVA/B 5 98 DHI, DEN 6 97 POUT VAA 4 4 VCC OPN 93-96 7-10 VIO DBL * DBH VDD VIO CH[0] CH[3] 91 13 * * DBH * DBL OPN VCC OPN VEE 90 14 89 15 88 16 87 17, 22 81, 86 19, 20 83, 84 23 80 24 79 25 78 26 77 VEE *** QA/B VCC 92 12 VEE *** TO DUT 4 100-104 11 TO DUT ** 105-108 VAA 114 115 116 VEE 1,2,127,128 POUT QA/B VCC 113 112 111 109-110 4 DHI, DEN 119 123-126 ** DGND 117 VXX 4 121 DVL/H, CVA/B 2 2 118, 120 CTCLV, CTCFIV *** * DBL * DBH TO DUT VDD * DBH * DBL VIO TO DUT VEE CH[1] 27 CH[2] 28 76 *** OPN VCC 75 4 4 VAA 29-32 71-74 33 24 69 POUT VDD 4 4 63-66 55-57 49-51, 53, 54 37-40 41-44 DHI, DEN 70 46-48 POUT QA/B VAA DHI, DEN 59-62 QA/B 4 VIO 4 DVL/H, CVA/B DGND ** 5 DVL/H, CVA/B ** SDOUT, SDIN, CLKIN, LOAD, RESET Figure 6. E7804 Hookup VEEs of all Channels must be connected together; same for VCCs, VAAs, VDD and GNDs. NOTE: All capacitors are 0.1mF unless otherwise noted. *DBH/L capacitors are 0.47mF. **DVH/L each have 0.22mF capacitors. Not necessary for CVA/B. ***Two ferrites in series. Each 600W; 1206 and 0603 package sizes. Steward Part #MI0603J601R-00 and #MI1206K601R-00. See text for further explanation. © 2007 Semtech Corp. / Rev. 7, 02/26/07 22 www.semtech.com E7804 TEST AND MEASUREMENT PRODUCTS Application Information (continued) Low Cost Pin Electronics with the E7804 Figure 7 shows 16 channels of ‘Low Cost’ Pin Electronics featuring the E7804, E6435 (Level DACs) and E4287 (PMU). 1/4 X E6435 1/2 E4287 PMU IVMON HLV VINP Level DACs LLV IVMAX IVMIN F -16 channels with levels per-pin and shared PMU per 16 pins S 1 X E6435 -133 MHz clocks VIO[0] - PMU, -3.25V, +9.75V with 4 current ranges to ± 40mA POUT[0] CTC - Continuity test per pin - Per-pin pull-up resistor 2K Level DACs - Compatible Power (common) supply (VCC, VDD, VEE, etc.) requirements for each chip VIO[15] POUT[15] CTC 2K 4 x E7804 16 Channel Driver, Comparator Figure 7. “Low Cost”, 16 Channel Pin Electronics © 2007 Semtech Corp. / Rev. 7, 02/26/07 23 www.semtech.com E7804 TEST AND MEASUREMENT PRODUCTS Application Information (continued) The diagram below shows the power consumption of the E7804 as a function of clocking frequency of all channels. E7804 Total Power versus (3V) Data Rate 2.5 Power (W) 2.0 1.5 Typ Max 1.0 0.5 0.0 0 50 100 150 Data Rate (MHz) The power consumption goes up with frequency and output voltage swing. Cooling Considerations Depending on the maximum operating frequencies and voltage swings the E7804 will need to drive, it may require the use of heatsinking to keep the maximum die junction termperature within a safe range and below the specified maximum of 100½C. The E7804 package has an internal heatspreader located at the top side of the package to efficiently conduct heat away from the die to the package top. The thermal resistance of the package to the top is the qJC (junction-to-case) and is specified at 4½C/Watt. In order to calculate what type of heatsinking should be applied to the E7804, the designer needs to determine the worst case power dissipation of the device in the application. The graph above gives a good visual relationship of the power dissipation to the maximum operating frequency (all channels simultaneously) and driver output voltage swings. Another variable that needs to be determined is the maximum ambient air temperature that will be surrounding or blowing on the device and/or the heatsink © 2007 Semtech Corp. / Rev. 7, 02/26/07 24 system in the application (assuming an air cooled system). A heatsinking solution should be chosen to be at or below a certain thermal impedance known as Rq in units of °C/ Watt. The heatsinking system is a combination of factors including the actual heatsink chosen and the selection of the intertface material between the E7804 and the heatsink itself. This could be thermal grease or thermal epoxy, and they also have their own thermal impedances. The heatsinking solution will also depend on the volume of air passing over the heatsink and at what angle the air is impacting the heatsink. There are many options available in selecting a heatsinking system. The formula below shows how to calculate the required maximum thermal impedance for the entire heatsink system. Once this is known, the designer can evaluate the options that best fit the system design and meet the required Rq. Rq(heatsink_system) = (TJmax - Tambient - P * qJC) / P where, Rq(heatsink_system) is the thermal resistance of the entire heatsink system TJmax is the maximum die temperature (100°C) Tambient is the maximum ambient air temp expected at the heatsink (°C) P is the maximum expected power dissipation of the E7804 (Watts) qJC is the thermal impedance of the E7804 junction to case (4°C/W) The graph below uses the power estimates from the previous graph and indicates the required maximum thermal impedances required for the heatsinking system using the above formula with Tambient at 35°C. Required Heatsinking Thermal Resistances All Drivers and Comparators Switching, Max Tj, Max Supplies, Process Corners, 3V into 20cm, 50ohm Transmission Line 65 60 55 Power (W) Computing Maximum Power Consumption 50 Typ Max 45 40 35 30 25 20 0 50 100 150 Data Rate (MHz) The value of the thermal resistance of the E7804 package www.semtech.com E7804 TEST AND MEASUREMENT PRODUCTS Application Information (continued) junction to air with 400 linear feet per minute (LFPM) of airflow is specified at 22°C/W. At operating points greater than or equal to this value, no additional heatsinking is needed to keep the die temperatures below the maximum 100°C as long as the ambient temperature of the 400 LFPM air does not exceed 35°C. More information on heatsink system selections can be read on heatsink vendors’ web sites and in the Semtech Application Note #ATE-A2 Cooling High Power, High Density Pin Electronics. Protection Considerations The E7804 has ESD protection on its input and outputs. The E7804 has internal, high voltage, disconnect switches for VIO and POUT pins. When open, these provide protection against voltages input into VIO and POUT which might have damaged drivers, comparators, and other internal circuits. The following sequencing can be used as a guideline when powering up: 1. 2. 3. 4. 5. 6. 7. VDD Digital Inputs Analog Inputs The recommended power-down sequence is the reverse order of the power-up sequence. One approach to ensure that the power supply polarities do not become reversed is to use Schottky diodes, as shown in Figure 8. One set of these diodes should be used per board. The optimum type of Schottky will depend on how much current the power supplies can source. VXX VCC Power Supply Sequencing/Latch-Up Protection VDD VAA In order to avoid the possibility of latch-up when powering this part up (or down), be careful that the conditions listed in the Absolute Maximum Ratings are never violated. That is, the power supplies should never be reverse-polarity with respect to ground, and the input signals should never go beyond the power supply rails. Low forward voltage drop Schottky's such as 1N5820 VEE Figure 8. Board Level Supply Diodes Furthermore, the lower-voltage analog supplies should never be greater than the higher-voltage supplies (VAA < VCC < VXX). This can easily be implemented by utilizing the diode circuit depicted in Figure 14 for each PCB that has E7804 devices on it. The following conditions must be met at all times during power-up and power-down. 1. 2. 3. 4. VEE VXX VCC VAA VEE GND VAA VCC VXX GND VDD VCC VEE Analog Inputs VCC or VXX GND Digital Inputs VDD © 2007 Semtech Corp. / Rev. 7, 02/26/07 25 www.semtech.com E7804 TEST AND MEASUREMENT PRODUCTS Package Information 128-Pin MQFP 14mm x 20mm x 2mm (with Internal Heat Spreader) E DIMENSIONS INCHES MILLIMETERS DIM MIN NOM MAX MIN NOM MAX D N 1 D/2 D1 D B A e/2 e E/2 aaa C A-B D 4X N/4 TIPS A A1 A2 b c D D1 E E1 e L L1 R N ND N 0 aaa bbb ccc - .093 .000 .010 .075 .079 .083 .011 .007 .009 .004 .913 BSC .783 .787 .791 .677 BSC .547 .551 .555 .020 BSC .029 .035 .041 (.063) .095 .115 .135 128 38 26 0-7° .008 .003 .003 2.35 0.00 0.25 1.90 2.00 2.10 0.27 0.19 0.23 0.11 23.20 BSC 19.90 20.00 20.10 17.20 BSC 13.90 14.00 14.10 0.50 BSC 0.73 0.88 1.03 (1.60) 2.42 2.92 3.42 128 38 26 0-7° 0.20 0.08 0.08 SEE DETAIL A E1 ccc C A A2 SEATING PLANE C bxN A1 bbb C A-B D H c GAGE PLANE L (L1) 0.25 0 DETAIL A NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. DATUMS -A- , -B- AND -D- TO BE DETERMINED AT DATUM PLANE -H- . 3. DIMENSIONS "E1" AND "D1" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. © 2007 Semtech Corp. / Rev. 7, 02/26/07 26 www.semtech.com E7804 TEST AND MEASUREMENT PRODUCTS Absolute Maximum Ratings Parameter Positive Analog Supply – VCC or VXX Symbol VCC, VXX Min -0.5 Max VEE + 16 Units V Positive Analog Supply – VAA VAA -0.5 6.0 V Negative Analog Supply – VEE VEE -5.5 0.5 V Digital Power Supplies – VDD VDD -0.5 6.0 V VCC to VEE VCC to VAA -0.5 -0.5 16.0 16.0 V V VDD + 0.5 V Total Power Supply Ranges Digital Input Voltages SDIN, CLKIN, LOAD, RESET*, OPN DGND - 0.5 Driver/Comparator Pin Comparator Only Connected VIO VIO VEE CVL - 6 VCC CVH + 6 V V VIO DVL - 0.7 DVH + 0.7 V POUT POUT POUT VEE VEE 0 VXX VAA VAA V V V Storage Temperature TS -65 150 ˚C Junction Temperature TJ 125 ˚C TSOL 260 ˚C Driver Connected Parametric Pin CTC and PUV not Connected CTC Connected PUV Connected Soldering Temperature (5 seconds, .25"" from the pin) Stresses above those listed in “Absolute Maximum Ratings” section may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these, or any other conditions beyond those listed, is not implied. Exposure to absolute maximum conditions for extended periods may affect device reliability. Recommended Operating Conditions Parameter Positive Analog Supply to Switches Symbol VXX to AGND Min VCC Typ 9.5 Max VEE + 15.0 Units V Positive Analog Power Supply – Channels VCC to AGND 8 8.25 8.5 V Positive Analog Power Supply – Channels VAA to AGND 4.75 5 5.5 V Negative Power Supply – Channels VEE to AGND -5.25 -5 -4.75 V VCC to VEE 12.75 13.75 V VDD to DGND 3.13 3.46 V Total Analog Supply Range Digital, Logic Power Supplies 3.3 Thermal Resistance - Junction to Case (Top) θJC 4 ˚C/W Thermal Resistance - Junction to Ambient Still Air 100 lfpm 400 lfpm θJA θJA θJA 28 25.2 22.1 ˚C/W ˚C/W ˚C/W Junction Temperature TJ 25 100 ˚C Note: AGND and DGND must be connected together externally. © 2007 Semtech Corp. / Rev. 7, 02/26/07 27 www.semtech.com E7804 TEST AND MEASUREMENT PRODUCTS DC Characteristics Digital Inputs/Outputs Parameter Symbol Min Typ Max Units 0.8 V V nA Digital Inputs (CLKIN, SDIN, LOAD, RESET*, OPN) Input Low Voltage Input High Voltage Input Current Digital Output (SDOUT) Output Low Voltage Output High Voltage Output Current Low Output Current High Capacitive Load VIL VIH IIN VOL VOH IOL IOH 2.0 –200 200 0.4 VDD 2.0 2.4 15 V V mA mA pF Max Units –2.0 CLOAD Driver Circuit Parameter Analog Inputs (DVH, DVL) High Level Low Level Input Current Driver Output (VIO) Range Driver Swing DC Output Current Output Impedance (Note 1) Output Impedance Accuracy (Note 2) HiZ Leakage (DEN= 0) (Note 3) Open Circuit Leakage (Driver, comparator disconnected) at VIO (VEE to VXX) DC Accuracy (Note 4) Offset Voltage (DVH – VIO, DVL – VIO) Gain Linearity Digital Inputs to Driver Input Voltage Range Differential Input Swing Input Current External Reference Resistor Symbol Min Typ DVH DVL IIN DVL + 0.5 -0.25 -10 VAA + 0.1 DVH - 0.5 20 V V µA DRNG DSWG IOUT ROUT RACC IOZ IOC -0.2 0.5 -50 48 VAA 5.4 50 110 -1 -10 1 10 V V mA Ω % µA nA VOS -20 0.99 -0.1 20 1.01 0.1 mV V/V % FSR DHI(*), DEN(*) |Input – Input*| IIN 0 ±0.24 -0.2 VDD VDD 0.2 V V µA REREF 4.5 11 KΩ 4 DC conditions (unless otherwise specified): Over the full Recommended Operating Conditions”, including the full range of the power supplies. Note 1: At VIO = (DVH + DVL) / 2. Note 2: Following calibration. Accuracy is measured as a percentage of REREF/100. Note 3: Comparator disconnected. Driver leakage specified for 0 ≤ [VVIO and DVH and DVL] ≤ VAA. Note 4: Offset measured with input voltage (DVL or DVH) at the minimum value, and the gain error measured with the input voltage at the maximum allowed value. Measurements made with VIO unloaded. © 2007 Semtech Corp. / Rev. 7, 02/26/07 28 www.semtech.com E7804 TEST AND MEASUREMENT PRODUCTS DC Characteristics (continued) Comparator Circuit Parameter Max Units -2.0 5.5 V IIN -5 30 µA Input Differential Voltage Range [(VIO – CVA), (VIO – CVB)] VDIFF -6.0 6.0 V Hysteresis VHYS Input Leakage (Driver disconnected) at VIO (–2.0 to +5.5V) I_BIAS -5 25 µA Input Leakage (Driver, Comparator disconnected) at VIO (VEE to VXX) IOC -10 10 nA Offset Voltage VOS -20 20 mV VOD VCM ∆VOD 250 450 1.375 mV 1.125 Min Typ Analog Inputs (CVA, CVB) Voltage Range Input Current Digital Outputs (Figure 9) Differential Output Swing Common Mode Output Voltage Range Change in VOD between Complimentary Output States Symbol Min VCVA, VCVB Typ 10 mV ±45 V mV Continuity Test Circuit (CTC) Parameter Symbol CTCLV (Limit Voltage) Voltage Range Input Current Offset Error Gain Error IIN CTCFIV Input Current IIN CTC Output Compliance Voltage CTC Output Current (Note 1) Programmable Range Offset Gain Error ICTC Max Units -2.0 -1 -20 -5 0.0 10 20 5 V µA mV % -200 200 nA CTCLV + 0.25 VAA - 1 V -250 -15 -15 -15 15 15 µA µA % DC conditions (unless otherwise specified): Over the full Recommended Operating Conditions”, including the full range of the power supplies. Note 1: Programmed by CTCFIV using the formula: ICTC = 1.09 * [CTCFIV(V) / REREF(W)]. Offset and gain are calculated from calibraiton points at 10% and 90% of the 250µA full-scale range. Q* VOD VCM Q Figure 9. Comparator Outputs © 2007 Semtech Corp. / Rev. 7, 02/26/07 29 www.semtech.com E7804 TEST AND MEASUREMENT PRODUCTS DC Characteristics (continued) External PMU Switches, VIO/POUT Capacitance Parameter Symbol Min On-Resistance (EPMU Force Switch S4 to POUT) (±40mA) Typ Max Units 40 110 Ω 500 Ω On-Resistance (EPMU Sense Switch S4 to POUT) (±4mA) On-Resistance (EPMUF and EPMUS Switch S7 to PMU_OUT) (±100µA) 100 7000 Ω On-Resistance (Driver Output to EPMUS Switch S3) (±100µA) 100 7000 Ω Leakage Current @ EPMUS (all channel's switches onto EPMU bus are open) -10 10 nA Leakage Current @ EPMUF (all channel's switches onto EPMU bus are open) -15 15 nA Capacitance @ EPMUS (all channels' switches onto EPMUS bus are open) 15 pF Capacitance @ EPMUF (all channel's switches onto EPMU bus, open) (0 to 50 MHz) 35 pF Capacitance at POUT (Switches Open) (Note 1) 12 pF Capacitance @ VIO (S1 = Open, S2 = Closed) 15 pF Capacitance @ VIO (S1 = S2 = Closed) 38 pF Leakage Current at POUT (Switches Open) (Note 1) -10 10 nA Max Current for EPMU Force Paths -40 40 mA Max Current for EPMU Sense Paths -4 4 mA POUT Output Range with EPMUF ≤ +40 mA VEE VXX - 2.5 V POUT Output Range with EPMUF ≥ –40 mA VEE + 2.5 VXX V VEE VXX V -1 1 µA POUT Output Range with EPMUF ±40 µA PMU_OUT Leakage DC conditions (unless otherwise specified): Over the full Recommended Operating Conditions” Note 1: Includes the EPMU, Continuity Test and Pull-up Switches. © 2007 Semtech Corp. / Rev. 7, 02/26/07 30 www.semtech.com E7804 TEST AND MEASUREMENT PRODUCTS DC Characteristics (continued) Pull-Up Resistor Parameter Pull-Up Resistor (including its switch) Symbol Min 1 Typ Max 3 Units KΩ PUV Voltage Range 0 VAA V PUV Gain Error -2 2 % PUV Input Current -3 3 µA 0 VAA V Typ Max Units 60 18 55 -45 1 90 30 80 mA mA mA mA mA V(POUTS6) POUT Voltage Range with S6 Closed Power Supplies Parameter Symbol Max Quiescent Power Supply Consumption (Note 1) Positive Analog Supply 1 Positive Analog Supply 2 Digital Supply Negative Power Supply Switch Power Supply Min ICC IAA IDD IEE IXX -80 4 Note 1: CLKIN Low, no VIO output currents, comparators with 100W floating terminations. E7804 Typical Supply Currents versus Data Rate (500mm Transmission Line) Current (mA) 120 100 80 ICC IEE IAA 60 40 20 0 0 50 100 150 Data Rate (MHz) The above graph depicts supply current variation with respect to all the Drivers concurrently driving the same 3V output swings over frequency into a 50Ω unterminated transmission line while also connected to the window comparators. © 2007 Semtech Corp. / Rev. 7, 02/26/07 31 www.semtech.com E7804 TEST AND MEASUREMENT PRODUCTS AC Characteristics a. Analog Output 50W Transmission Line (20 inches, ~2ns) VIO 600W 0603 POUT b. Comparator Outputs 953W Oscilloscope VIO VGEN Q 50W c. Comparator Input 100 50W Q* Ferrites 600W 1206 NOTE: Driver propagation delays specified with transmission line delay removed. Figure 10. AC Test Circuits © 2007 Semtech Corp. / Rev. 7, 02/26/07 32 www.semtech.com E7804 TEST AND MEASUREMENT PRODUCTS AC Characteristics (continued) Comparator Circuit (Driver S1 Open) Parameter Propagation Delay (0 to 3V Input) (Figure 16) Note 4 Note 5 Digital Output Rise and Fall Times (20% - 80%) (into 100Ω floating termination) Minimum Pulse Width (Note 1) Propagation Delay Matching (Note 5) Symbol Min Tpd(+),(–) Tpd(+),(–) 3.5 3.0 Typ Units 7.5 ns ns 6.0 Tr, Tf 550 ps Tpd(+),(–) Driver Circuit Parameter Propagation Delay (0 to 3V Output) (Note 2, Figure 17) Data (DHI) to Output Note 4 Note 5 Enable to HiZ (Figure 12) Enable to Output Active (Figure 12) Symbol Min TPLH, TPHL TPLH, TPHL TPAZ TPZA 3.5 3.4 3.0 3.0 Propagation Delay Match (Tpd(+) to Tpd(–)) (Note 5) Tpd(+) to (–) Rise/Fall Times 0 to 800 mV (20% - 80%) 0 to 3V (10% - 90%) 0 to 5V (10% - 90%) Tr/Tf Tr/Tf Tr/Tf 2.4 Fmax (Note 3, Figure 13) 800 mV 3V 5V Fmax Fmax Fmax 133 133 100 Minimum Pulse Width (Note 3, Figure 14) 0 to 800 mV 0 to 3V 0 to 5V Max Typ Tpw+, Tpw– Tpw+, Tpw– Tpw+, Tpw– 6 ns 1.0 ns Max Units 6.5 5.7 6.5 6.5 ns ns ns ns 1.0 ns 2.0 2.5 3.0 ns ns ns MHz MHz MHz 3.0 3.0 4.5 ns ns ns AC Test Conditions (unless otherwise specified): “Recommended Operating Conditions.” Note 1: Note 2: Note 3: Note 4: Note 5: For 3V input while maintaining less than 300ps of propagation delay variation. Driver propagation delays are measured with LVDS differential logic inputs at DHI and DEN. Output delay is specified with transmission line delay removed. At less than 10% output amplitude attenuation, DVL = 0V. Over all recommended operating conditions and junction temperatures. VDD at 3.3V, VCC = 8.2V, VEE = -5V, junction temperature at 45°C. © 2007 Semtech Corp. / Rev. 7, 02/26/07 33 www.semtech.com E7804 TEST AND MEASUREMENT PRODUCTS AC Characteristics (continued) Driver Performance Parameter Symbol Driver Temp. Coefficient (∆pd/∆T) (Note 4) ∆Tpd/˚C Driver Tpd Dispersion vs. Amplitude (Note 1, Figure 11) Driver Tpd Dispersion vs. Common Mode (Note 2, Figure 11) Driver Tpd Dispersion vs. Pulse Width (Note 3, Figure 15) Min Typ Max Units 10 ps/˚C ∆Tpd (Swing) 0.7 1 ns ∆Tpd (cm) 0.8 1 ns ∆Tpw 0.3 0.4 ns Comparator Performance Parameter Symbol Comparator Temp. Coefficient (∆pd/∆T) ∆Tpd/˚C Min Typ Max Units 6 10 ps/˚C Comparator Tpd Dispersion vs. Overdrive (Figure 17) 1.5 2 ns Comparator Tpd Dispersion vs. Common Mode (Figure 18) 1.1 1.5 ns Comparator Tpd Dispersion vs. Edge Rate (Figure 19) 0.8 1.0 ns Comparator Waveform Tracking Dispersion (Figure 20) 3.0 3.5 ns Comparator Tpd Dispersion vs. Pulse Width (Figure 21) 0.4 0.7 ns Typ Max Units 1 1 µs µs 1 µs Internal Switches Parameter Symbol OPN Input to S1 and S2, Time to: Disconnect Connect PMU to POUT, S4, Connect/Disconnect (measured from valid LOAD and CLKIN edges) (Note 5) Note 1: Note 2: Note 3: Note 4: Note 5: Min Variation in propagation delay when DVL = 0, vary DVH from 0.5V to 5.0V. Driver Output = 0.8V swing. Common mode = 1.0V to 3.0V. Propagation delay change when going from long to short pulse widths. DVL = 0V, DVH = 3V. Switches S1-S6 open on the fourth (4th) low-going CLKIN edge after a LOAD signal is applied. S1-S6 will close on the fifth (5th) low-going CLKIN edge. Switch S7 will open or close on the fourth (4th) low-going CLKIN edge after LOAD. © 2007 Semtech Corp. / Rev. 7, 02/26/07 34 www.semtech.com E7804 TEST AND MEASUREMENT PRODUCTS AC Characteristics (continued) 50% VIO TPLH TPHL DHI* DHI Figure 11. Driver Propagation Delay Measurements VIO +0.5V 90% 10% 0.0V Time TPZA TPAZ DEN* DEN Transmission line terminated 50W to ground. Figure 12. Driver HiZ Enable/Disable Delay Measurement Definition OUT(H) = 0.8V, 3.0, 5.0V VIO 1 / Fmax OUT(H) 0.90 OUT(H) Time 0.0V Figure 13. Driver Fmax Measurement Definition © 2007 Semtech Corp. / Rev. 7, 02/26/07 35 www.semtech.com E7804 TEST AND MEASUREMENT PRODUCTS AC Characteristics (continued) VOH = 0.8, 3.0, 5.0 VOL = 0V Period = 100ns VIO Tpw+ Tpw VOH VOL + 0.9 * (VOH VOL) Output Signal (VOH+VOL)/2 VOL + 0.1 * (VOH VOL) VOL Time Figure 14. Driver Minimum Pulse Width Measurement Definition Period = 100 ns; Tpw1 = 95 ns; Tpw2 = 5 ns (DHI DHI*) Tpw,in1 Tpw,in2 0.0V VIO Time OUTPUT: OUT(H) = 3.0V; OUT(L) = 0.0V 3.0V 1.5V 0.0V Tpw,out2 Time Tpw,out1 ∆Tpw = |(Tpw,in1 Tpw,out1) (Tpw,in2 Tpw,out2)| Figure 15. Driver Dispersion: Pulse Width Measurement Definition © 2007 Semtech Corp. / Rev. 7, 02/26/07 36 www.semtech.com E7804 TEST AND MEASUREMENT PRODUCTS AC Characteristics (continued) SR = 1.5V/ns VIO 100% 50% CVA, CVB 0% Tpd(+) Tpd( ) QA*/QB* QA/QB Figure 16. Comparator Propagation Delay Measurements VGEN INPUT: Freq = 10 MHz; 50% Duty Cycle, SR = 1V/ns 20–80% Tr,f for 500 mV p-p = 0.3 ns; for 5V p-p = 3 ns 2.5V 2.5V 250 mV CVA/B 250 mV 2.5V 0.0V (QA – QA*) Time TPLH TPHL Time 0.0V Figure 17. Comparator Dispersion: Overdrive Measurement Definition © 2007 Semtech Corp. / Rev. 7, 02/26/07 37 www.semtech.com E7804 TEST AND MEASUREMENT PRODUCTS AC Characteristics (continued) INPUT: Freq = 10 MHz; 500 mV pp; 0V < Vos < 5.0V 50% duty cycle, 20-80% Tr,f = 0.3 ns VGEN CVA/B = 50% +5.0V CVA/B = 50% 0.0V CVA/B = 50% 0V (QA QA*) Tpd(+) Tpd( ) 0.0V Time Figure 18. Comparator Dispersion: Common Mode Measurement Definition VGEN INPUT: Freq = 10 MHz; 0-3.0V; 50% Duty Cycle; 0.5 ns 20-80% Tr,f 5.0 ns 3.0V CVA/B = 1.5V 0.0V (QA QA*) Time Tpd(+) Tpd( ) Time 0.0V Figure 19. Comparator Input Slew Rate Measurement Definition © 2007 Semtech Corp. / Rev. 7, 02/26/07 38 www.semtech.com E7804 TEST AND MEASUREMENT PRODUCTS AC Characteristics (continued) INPUT: Freq = 10 MHz; 0-3.0V; 50% Duty Cycle; 10 90% Tr,f = 1.6 ns (SR = 1.5V/ns) VGEN 3.0V 90% 50% 10% 0.0V Time (QA QA*) Tpd4 Tpd1 0.0V Time (QA QA*) Tpd5 Tpd2 Time 0.0V (QA QA*) Tpd6 Tpd3 Time 0.0V Figure 20. Comparator Dispersion: Waveform Tracking Measurement Definition INPUT: Period = 100 ns; 1.0V pp; 5.0 ns < P.W. < 95 ns; 20-80% Tr,f = 1.0 ns VGEN 1.0V CVA/B = 0.50V Time 0.0V Tpw,in1 Tpw,in2 (QA QA*) Tpw,out1 Tpw,out2 0.0V Time Figure 21. Comparator Dispersion: Pulse Width Measurement Definition © 2007 Semtech Corp. / Rev. 7, 02/26/07 39 www.semtech.com E7804 TEST AND MEASUREMENT PRODUCTS AC Characteristics (continued) Logic Specifications (Figure 22) Parameter Set up Times (to CLKIN rising edge) SDIN LOAD Symbol Min TSU_SDIN TSU_LD 3 5.0 ns ns AC50 AC51 THLD_SDIN THLD_LD 5.0 8.0 ns ns AC52 AC53 Output Delay Times (to CLKIN falling edge) SDOUT TSDOUT 0.5 7.0 ns AC54 CLKIN Fmax Clock High Time Clock Low Time RESET to Clock Hold-Off Time (Note 1) Fmax TCLKH TCLKL TRST_IN 33.0 10 10 10 MHz ns ns ns AC55 AC56 AC58 AC59 PW RESET 20 ns AC57 Hold Times (to CLKIN rising edge) SDIN LOAD RESET Pulse Width Typ Max Units Note 1: After an external RESET* event, valid input signals (SDIN and CLKIN) should be held off to allow internal gates to exit RESET. SDIN and CLKIN edges may be present before TRST_IN, but the clocked states cannot be guaranteed. The RESET signal is asynchronous on both assertion and de-assertion. SDIN TSU_SDIN THLD_SDIN TCLKH CLKIN TCLKL TSDOUT TRST_IN SDOUT THLD_LD LOAD TSU_LD RESET* PWRESET Figure 22. Logic Timing Diagram © 2007 Semtech Corp. / Rev. 7, 02/26/07 40 www.semtech.com E7804 TEST AND MEASUREMENT PRODUCTS Ordering Information Model Number Package E7804BHFT 128-Pin, 14x20x2mm MQFP 0.5mm Lead Pitch (with Internal Heat Spreader) EVM7804BHFT E7804 Evaluation Board Pb This product is lead-free. Contact Information Semtech Corporation Test and Measurement Division 10021 Willow Creek Rd., San Diego, CA 92131 Phone: (858)695-1808 FAX (858)695-2633 © 2007 Semtech Corp. / Rev. 7, 02/26/07 41 www.semtech.com