FUJITSU MICROELECTRONICS DATA SHEET DS04–27265–3E ASSP For Power Management Applications (Rechargeable Battery) Synchronous Rectification DC/DC Converter IC for Charging Li-ion Battery MB39A132 ■ DESCRIPTION MB39A132, which is used for charging Li-ion battery, is a synchronous rectification DC/DC converter IC adopting pulse width modification (PWM). It can control charge voltage and charge current separately and supports the N-ch MOS driver. In addition, MB39A132 is suitable for down-conversion. MB39A132 has an AC adapter detection comparator, which is independent of the DC/DC converter control block, and can control the source supplying voltage to the system. MB39A132 supports a wide input voltage range, enables low current consumption in standby mode, and can control the charge voltage and charge current with high precision, which is perfect for the built-in Li-ion battery charger used in devices such as notebook PC. ■ FEATURES • • • • • • • • • • • • • • • Supports 2/3/4-Cell battery pack Two built-in constant current control loops Built-in AC adapter detection function (ACOK pin) Charge voltage setting accuracy: ±0.5% (Ta = + 25 °C to + 85 °C) Charge voltage control setting can be selected without using any external resistor. (4.00 V/Cell, 4.20 V/ Cell, 4.35 V/Cell) Output voltage can also be freely set by using the external resistor. Two built-in high-precision current detection amplifiers :Input offset voltage:+3 mV :Detection accuracy: ±1 mV (+INC1, +INC2 = 3 V to VCC) Charge current control setting can be selected without using any external resistor. (RS = 20 mΩ: 2.85 A) Charge current can also be freely set by using the external resistor. Switching frequency can be set by using the external resistor (MB39A132 has a built-in frequency setting capacitor.):100 kHz to 2 MHz Built-in off time control function In standby mode (Icc = 6 μA Typ), only the AC adapter detection function is in operation. Built-in output stage for N-ch MOS FET synchronous rectification Built-in charge stop function at low VCC pin voltage Built-in soft-start function whose setting time can be adjusted Equipped with the function enabling the independent operation of the AC adapter current detection amplifier Package: QFN-32 ■ APPLICATIONS • Internal charger used in notebook PC • Handy terminal device etc. Copyright©2008-2009 FUJITSU MICROELECTRONICS LIMITED All rights reserved 2009.3 MB39A132 ■ PIN ASSIGNMENT CTL2 CB OUT1 LX VB OUT2 PGND CELLS (TOP VIEW) 32 31 30 29 28 27 26 25 VCC 1 24 VIN -INC1 2 23 CTL1 +INC1 3 22 GND ACIN 4 21 VREF QFN-32 18 ADJ3 COMP1 8 17 BATT 9 10 11 12 13 14 15 16 COMP3 7 COMP2 ADJ1 ADJ2 19 CS -INC2 6 +INC2 -INE3 OUTC2 20 RT OUTC1 5 -INE1 ACOK (LCC-32P-M17) 2 DS04–27265–3E MB39A132 ■ PIN DESCRIPTIONS Pin No. Pin Name I/O Description 1 VCC ⎯ 2 -INC1 I Current detection amplifier (Current Amp1) inverted input pin. 3 +INC1 I Current detection amplifier (Current Amp1) non-inverted input pin. 4 ACIN I AC adapter voltage detection block (AC Comp.) input pin. 5 ACOK O AC adapter voltage detection block (AC Comp.) output pin. ACOK = Lo-Z when ACIN = H, ACOK = Hi-Z when ACIN = L 6 -INE3 I Error amplifier (Error Amp3) inverted input pin. 7 ADJ1 I Error amplifier (Error Amp1) non-inverted input pin. 8 COMP1 O Error amplifier (Error Amp1) output pin. 9 -INE1 I Error amplifier (Error Amp1) inverted input pin. 10 OUTC1 O Current detection amplifier (Current Amp1) output pin. 11 OUTC2 O Current detection amplifier (Current Amp2) output pin. 12 +INC2 I Current detection amplifier (Current Amp2) non-inverted input pin. 13 -INC2 I Current detection amplifier (Current Amp2) inverted input pin. Power supply pin for reference power and control circuit (Battery side). 14 ADJ2 I Input pin for the charge current control block. ADJ2 pin “GND to 4.4 V” :Charge current control block output = ADJ2 pin voltage ADJ2 pin “4.6 V to VREF” :Charge current control block output = 1.5 V 15 COMP2 O Error amplifier (Error Amp2) output pin. 16 COMP3 O Error amplifier (Error Amp3) output pin. 17 BATT I Charge voltage control block battery voltage input pin. Charge voltage control block setting input pin. ADJ3 pin “GND” :Charge voltage 4.00 V/Cell ADJ3 pin “1.1 V to 2.2 V” :Charge voltage 2 × ADJ3 pin voltage/Cell ADJ3 pin “2.4 V to 3.9 V” :Charge voltage 4.35 V/Cell ADJ3 pin “4.1 V to VREF” :Charge voltage 4.20 V/Cell 18 ADJ3 I 19 CS ⎯ Soft-start capacitor connection pin. 20 RT ⎯ Triangular wave oscillation frequency setting resistor connection pin. 21 VREF O Reference voltage output pin. 22 GND ⎯ Ground pin. 23 CTL1 I 24 VIN ⎯ Power supply pin for ACOK function and Current Amp1(AC adapter side). 25 CELLS I Charge voltage setting switch pin (2/3/4-Cell). CELLS = VREF: 4 Cells, CELLS = OPEN: 3 Cells, CELLS = GND: 2 Cells 26 PGND ⎯ Ground pin. 27 OUT2 O External low-side FET gate drive pin. 28 VB O FET drive circuit power supply pin. 29 LX ⎯ External high-side FET source connection pin. 30 OUT1 O External high-side FET gate drive pin. Power supply control pin. When the CTL1 pin is set to “H” level, the DC/DC converter becomes operable. When the CTL1 pin is set to “L” level, the DC/DC converter becomes stand-by. (Continued) DS04–27265–3E 3 MB39A132 (Continued) Pin No. Pin Name 4 I/O Description 31 CB ⎯ Boot strap capacitor connection pin. The capacitor is connected between the CB pin and the LX pin. 32 CTL2 I Power supply control pin for Current Amp1. When the CTL1 pin is set to “H” level, the DC/DC converter becomes operable. When the CTL1 pin is set to “L” level, the DC/DC converter becomes stand-by. DS04–27265–3E MB39A132 ■ BLOCK DIAGRAM TO SYSTEM LOAD ACIN CTL2 ACOK 4 32 5 <AC Comp.> VIN 24 -INE1 9 Buffer OUTC1 VCC 10 +INC1 -INC1 ADJ1 VIN 1 <Current Amp1> <Error Amp1> 3 VB ×25 2 <PWM Comp.> Adaptor Det. VB Reg. CB 3 mV 7 31 - 2.5 V GM Amp Buffer OUTC2 12 -INC2 13 Drive Logic B Drv1 <Current Amp2> +INC2 Off Time Control <Error Amp2> ×25 3 mV Io LX C VO RS 20 mΩ OUT2 Drv2 GM Amp Charge Current Control 14 B 2.85 A 30 29 OSC ADJ2 A OUT1 - 1.5 V 11 A 28 27 PGND CT 26 Battery <Sync Cnt.> -INE3 6 2.6 V BATT C <UV Comp.> 17 VCC 0.1 V ADJ3 VREF:4.20 V/Cell 2.4 V to 3.9 V: 4.35 V/Cell 1.1 V to 2.2 V: 2 × VADJ3/Cell GND:4.00 V/Cell CELLS <Error Amp3> 18 VO REFIN Control VCC UVLO VREF UVLO 25 GM Amp VB UVLO GND: 2 Cells OPEN: 3 Cells VREF: 4 Cells <SOFT> VREF Slope Control 10 μA CS 19 CTL1 <VR1> <Over Current Det.> +INC2 <REF> <CTL> 23 5.0 V ON/OFF VREF -INC2 0.2 V 15 8 COMP1 DS04–27265–3E 20 16 COMP2 COMP3 21 RT VREF 22 GND (32-pin) 5 MB39A132 ■ ABSOLUTE MAXIMUM RATINGS Parameter Symbol Condition Rating Min Max Unit VVCC VCC pin − 0.3 + 27 V VVIN VIN pin − 0.3 + 27 V CB pin input voltage VCB CB pin − 0.3 + 32 V CTL1, CTL2 pin input voltage VCTL CTL1, CTL2 pins − 0.3 + 27 V -INC1, +INC1 pins − 0.3 + 27 V -INC2, +INC2, BATT pins − 0.3 + 20 V VADJ ADJ1, ADJ2, ADJ3, CELLS pins − 0.3 VVREF + 0.3 V VINE -INE1, -INE3 pins − 0.3 VVREF + 0.3 V ACIN input voltage VACIN ACIN pin − 0.3 VVIN V ACOK pin output voltage VACOK ACOK pin − 0.3 + 27 V Output current IOUT OUT1, OUT2 pins − 60 + 60 mA ⎯ 4400*1,*2,*3 mW ⎯ 1900*1,*2,*4 mW ⎯ 1, 2, 3 1760* * * mW ⎯ 1, 2, 4 mW Power supply voltage VINC Input voltage Ta ≤ + 25 °C Power dissipation PD Ta = + 85 °C Storage temperature TSTG ⎯ − 55 760* * * + 125 °C *1 : See the diagram of “■ TYPICAL CHARACTERISTICS • Power Dissipation vs. Operating Ambient Temperature”, for the package power dissipation of Ta from + 25 °C to + 85 °C. *2 : When the IC is mounted on a 10x10 cm two-layer square epoxy board. *3 : IC is mounted on a two-layer epoxy board, which has thermal vias, and the IC's thermal pad is connected to the epoxy board. *4 : IC is mounted on a two-layer epoxy board, which has no thermal vias, and the IC's thermal pad is connected to the epoxy board. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 6 DS04–27265–3E MB39A132 ■ RECOMMENDED OPERATING CONDITIONS Parameter Symbol Condition Value Min Typ Max Unit VVCC VCC pin 8 ⎯ 25 V VVIN VIN pin 8 ⎯ 25 V CB pin input voltage VCB CB pin ⎯ ⎯ 30 V Reference voltage output current IVREF ⎯ −1 ⎯ 0 mA Bias output current IVB ⎯ −1 ⎯ 0 mA -INC1, +INC1 pins 0 ⎯ VVCC V -INC2, +INC2, BATT pins 0 ⎯ 19 V ADJ1 pin 0 ⎯ VVREF − 1.5 V 4.6 ⎯ VVREF V 0 ⎯ 0.2 V 0.4 ⎯ 4.4 V Power supply voltage VINC ADJ2 pin (when using the internal reference voltage) Input voltage VADJ VINE ADJ2 pin (external voltage setting) ADJ3 pin (when using the internal reference voltage) 4.1 ⎯ VVREF V 2.4 ⎯ 3.9 V 0 ⎯ 0.9 V ADJ3 pin (external voltage setting) 1.1 ⎯ 2.2 V CELLS pin 0 ⎯ VVREF V -INE1, -INE3 pins 0 ⎯ VVREF V ACIN pin input voltage VACIN ⎯ 0 ⎯ VVREF V ACOK pin output voltage VACOK ⎯ 0 ⎯ 25 V ACOK pin output current IACOK ⎯ 0 ⎯ 1 mA CTL1, CTL2 pin input voltage VCTL ⎯ 0 ⎯ 25 V − 45 ⎯ + 45 mA − 1200 ⎯ + 1200 mA 100 500 2000 kHz OUT1, OUT2 pins Output current IOUT Switching frequency fOSC Timing resistor RRT RT pin 8.2 33 180 kΩ Soft-start capacitor CCS CS pin ⎯ 0.22 ⎯ μF CB pin capacitor CCB ⎯ 0.1 ⎯ μF Bias output capacitor CVB VB pin ⎯ 1.0 ⎯ μF Reference voltage output capacitor CREF VREF pin ⎯ 0.1 1.0 μF OUT1, OUT2 pins Duty ≤ 5% (t = 1/fosc × Duty) ⎯ ⎯ (Continued) DS04–27265–3E 7 MB39A132 (Continued) Parameter Operating ambient temperature Symbol Condition Ta ⎯ Value Min Typ Max − 30 + 25 + 85 Unit °C WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. 8 DS04–27265–3E MB39A132 ■ ELECTRICAL CHARACTERISTICS (Ta = + 25 °C, VCC pin = 19 V, VB pin = 0 mA, VREF pin = 0 mA) Pin No. Condition VVREF1 21 ⎯ VVREF2 21 Ta = − 10 °C to + 85 °C VREF 21 VCC pin = 8 V to 25 V ⎯ 1 10 mV VREF 21 VREF pin = 0 mA to − 1mA ⎯ 1 10 mV Short-circuit output current Ios 21 VREF pin = 1 V − 70 − 35 − 17 mA Oscillation frequency fOSC 30 RT pin = 33 kΩ 450 500 550 kHz Frequency temperature variation df/fdT 30 Ta = − 30 °C to + 85 °C ⎯ 1* ⎯ % Input offset voltage VIO 7 COMP1 pin = 2 V ⎯ 1* 5 mV IADJ1 7 ADJ1 pin = 0 V − 100 ⎯ ⎯ nA Gm 8 ⎯ ⎯ 20* ⎯ μA/V VTH1 14 ⎯ 1.5* ⎯ V Gm 15 ⎯ 20* ⎯ μA/V Threshold voltage Reference Input stability Voltage Block Load stability [REF] Triangular Wave Oscillator Block [OSC] Value Symbol Parameter Error Amplifier Input bias Block current [Error Amp1] Transconductance Threshold Error Amplifier voltage Block [Error Amp2] Transconductance ADJ2 pin = VREF pin ⎯ Min Typ Max Unit 4.963 5.000 5.037 V 4.950 5.000 5.050 V (Continued) DS04–27265–3E 9 MB39A132 (Ta = + 25 °C, VCC pin = 19 V, VB pin = 0 mA, VREF pin = 0 mA) Parameter Symbol Pin No. Value Unit Min Typ Max 17 COMP3 pin = 2 V, Ta = + 25 °C to + 85 °C ADJ3 pin = CELLS pin = VREF pin − 0.5 0 + 0.5 % 17 COMP3 = 2 V, Ta = − 10 °C to + 85 °C ADJ3 pin = CELLS pin = VREF pin − 0.7 0 + 0.5 % 17 COMP3 = 2 V, Ta = + 25 °C to + 85 °C 2.4 V ≤ ADJ3 pin ≤ 3.9 V CELLS pin = VREF pin − 0.5 0 + 0.5 % 17 COMP3 pin = 2 V, Ta = − 10 °C to + 85 °C 2.4 V ≤ ADJ3 pin ≤ 3.9 V CELLS pin = VREF pin − 0.7 0 + 0.5 % 17 COMP3 pin = 2 V, Ta = + 25 °C to + 85 °C ADJ3 = GND pin, CELLS pin = VREF pin − 0.5 0 + 0.5 % VTH6 17 COMP3 pin = 2 V, Ta = − 10 °C to + 85 °C ADJ3 pin = GND pin, CELLS pin = VREF pin − 0.7 0 + 0.5 % IBATTH 17 2.4 V ≤ ADJ3 ≤ 3.9 V CELLS pin = VREF pin, BATT pin = 16.8 V ⎯ 34 60 μA IBATTL 17 VCC pin = 0 V, BATT pin = 16.8 V ⎯ 0 1 μA Gm 16 ⎯ 280* ⎯ μA/V VTH1 VTH2 VTH3 Threshold voltage VTH4 Error Amplifier Block [Error Amp3] VTH5 Input current Transconductance Condition ⎯ (Continued) 10 DS04–27265–3E MB39A132 (Ta = + 25 °C, VCC pin = 19 V, VB pin = 0 mA, VREF pin = 0 mA) Value Symbol Pin No. Condition I+INCH1 3 I+INCH2 12 I-INCH 2,13 I+INCL +INC1 pin = +INC2 pin = 3,12 0.1 V, ΔVin = − 100 mV I-INCL − INC1 pin = − INC2 pin = 2,13 0.1 V, ΔVin = − 100 mV VOFF1 10,11 +INC1 pin = +INC2 pin = 3 V to VCC pin 2 VOFF2 10,11 +INC1 pin = +INC2 pin = 0 V to 3 V VCM 10,11 ⎯ Voltage gain Av 10,11 Frequency bandwidth BW 10,11 AV = 0 dB Parameter Input current Input offset voltage Current Detection Amplifier Block Common [Current Amp1, mode input Current Amp2] voltage range Unit Min Typ Max +INC1 pin = 3 V to VCC pin, ΔVin = − 100 mV ⎯ 20 30 μA +INC2 pin = 3 V to VCC pin, ΔVin = − 100 mV ⎯ 30 45 μA − INC1 pin = − INC2 pin = 3 V to VCC pin, ΔVin = − 100 mV ⎯ 0.1 0.2 μA − 240 − 160 ⎯ μA − 270 − 180 ⎯ μA 3 4 mV 1 3 5 mV 0 ⎯ VVCC V 25.0 25.5 V/V ⎯ 2* ⎯ MHz +INC1 pin = +INC2 pin = 3 V 24.5 to VCC pin, ΔVin = − 100 mV VOUTCH 10,11 ⎯ 4.7 4.9 ⎯ V VOUTCL 10,11 +INC1 pin = +INC2 pin = 3 V to VCC pin 50 75 100 mV ISOURCE 10,11 OUTC1 pin = OUTC2 pin = 2 V ⎯ −2 −1 mA Output sink current ISINK 10,11 OUTC1 pin = OUTC2 pin = 2 V 25 50 ⎯ μA OUTC1 pin Output voltage VOUTC1 10 VIN pin = 0 V ⎯ 0 ⎯ V VTL 30 Duty cycle = 0 % 1.4 1.5 ⎯ V VTH 30 Duty cycle = 100 % ⎯ 2.5 2.6 V ROH 27,30 OUT1,OUT2 pin = − 45 mA ⎯ 4 7 Ω ROL 27,30 OUT1,OUT2 pin = + 45 mA ⎯ 1 3.5 Ω Output voltage Output source current PWM Comparator Block [PWM Comp.] Threshold voltage Output Block [OUT] Output ON resistance (Continued) DS04–27265–3E 11 MB39A132 (Ta = + 25 °C, VCC pin = 19 V, VB pin = 0 mA, VREF pin = 0 mA) Parameter Pin No. 23,32 23,32 23,32 23,32 28 Condition Max 25 0.8 40 1 5.1 ⎯ 10 50 mV 2.55 2.5 2.60 2.55 2.65 2.60 V V ⎯ 0.05* ⎯ V Unit Bias Voltage Block [VB] Output voltage Load stability Load 28 Synchronous Rectification Control Block [Synchronous Cnt.] CS threshold voltage VTLH VTHL 19 19 Hysteresis width VH 19 Threshold voltage VTLH VTHL 1 1 VCC pin VCC pin ⎯ 7.0 7.5 7.4 7.9 ⎯ V V Hysteresis width VH 1 VCC pin ⎯ 0.1 ⎯ V Threshold voltage VTLH VTHL 28 28 VB pin VB pin 3.8 3.1 4.0 3.3 4.2 3.5 V V Hysteresis width VH 28 VB pin ⎯ 0.7 ⎯ V Threshold voltage VTLH VTHL 21 21 VREF pin VREF pin 2.6 2.4 2.8 2.6 3.0 2.8 V V Hysteresis width VH 21 VREF pin ⎯ 0.2 ⎯ V Output voltage VH 12 -INC2 pin = 12.6 V 12.75 12.80 12.85 V Threshold voltage VTLH VTHL 1 1 BATT pin = 12.6 V BATT pin = 12.6 V 12.6 12.5 12.8 12.7 13.0 12.9 V V Hysteresis width VH 1 BATT pin = 12.6 V ⎯ 0.1 ⎯ V Threshold voltage VTLH VTHL 4 4 ⎯ ⎯ VH 4 ⎯ ⎯ 10 ⎯ mV I-INCL 4 ⎯ ⎯ ⎯ 200 nA ILEAK 5 ACOK pin = 25 V ⎯ 0 1 μA VACOKL 5 ACOK pin = 1 mA ⎯ 0.9 1.1 V Under Voltage Lockout Protection Circuit Block [UVLO] Over Current Detection Block [Over Current Det.] Under Input Voltage Detection Block [UV Comp.] AC Adapter Voltage Detection Block [AC Comp.] Input current Hysteresis width Input current ACOK pin output leak current ACOK pin output “L” Level voltage IC operation mode IC standby mode CTL1, CTL2 pin = 5 V CTL1, CTL2 pin = 0 V ⎯ VB pin = 0 mA to − 10 mA ⎯ ⎯ Min 2 0 ⎯ ⎯ 4.9 Value Typ ⎯ ⎯ 25 0 5.0 VON VOFF ICTLH ICTLL VB Control Block [CTL1,CTL2] ON condition OFF condition Symbol ⎯ 1.237 1.250 1.263 1.227 1.240 1.253 V V μA μA V V V (Continued) 12 DS04–27265–3E MB39A132 (Continued) (Ta = + 25 °C, VCC pin = 19 V, VB pin = 0 mA, VREF pin = 0 mA) Parameter Threshold voltage Charge Voltage Input current Control Block [VO REFIN Input voltage Control] Input current Charge Current Threshold voltage Control Block [Charge Current Input current Control] Soft-start Block Charge [SOFT] current Standby current Symbol Pin No. VTHH 18 VTHM Unit Typ Max At 4.2 V/Cell 3.91 4.00 4.09 V 18 At 4.35 V/Cell 2.21 2.30 2.39 V VTHL 18 At 4.0 V/Cell 0.91 1.00 1.09 V IIN 18 ADJ3 pin ⎯ 0 1 μA VH 25 At 4Cells VVREF − 0.4 ⎯ VVREF V VM 25 At 3Cells 2.4 ⎯ 2.6 V VL 25 At 2Cells 0 ⎯ 0.3 V IINL 25 CELLS pin = 0 V − 8.3 −5 ⎯ μA IINH 25 CELLS pin = VREF pin ⎯ 5 8.3 μA VTH 14 4.41 4.5 4.59 V IIN 14 ⎯ 0 1 μA ICS 19 ⎯ − 14 − 10 −6 μA IVINL 24 VIN pin = 19 V, ACIN pin = 0 V ⎯ 0 1 μA 24 VCC pin = 0 V, CTL1, CTL2 pin = 0 V, ACIN pin = 5 V, VIN pin = 19 V ⎯ 6 10 μA 1 VIN pin = 0 V, CTL1, CTL2 pin = 0 V, ACIN pin = 0 V, VCC pin = 19 V ⎯ 0 1 μA 24 VIN pin = 19 V, VCC pin = 0 V, ACIN pin = 5 V, CTL1 pin = 0 V, CTL2 pin = 5 V ⎯ 300 450 μA 1 VIN pin = 0 V, VCC pin = 19 V, ACIN pin = 0 V, CTL1 pin = 5 V, CTL2 pin = 0 V ⎯ 2.4 3.6 mA VIN pin = 19 V, VCC pin = 19 V, 1,24 ACIN pin = 5 V, CTL1 pin = 5 V, CTL2 pin = 5 V ⎯ 2.7 4.1 mA IINS IIN Power supply current Value Min ICCS General Condition ICC IINCC ⎯ ADJ2 pin *: This value is not be specified. This should be used as a reference to support designing the circuits. DS04–27265–3E 13 MB39A132 ■ TYPICAL CHARACTERISTICS Reference voltage vs. Power supply voltage 4 3 2 Ta = + 25°C VCTL1 = 5 V 1 0 10 5 0 15 20 25 4 3 Ta = +25°C VCTL1 = 5 V IVREF = 0 mA 2 1 0 10 5 0 15 20 25 Power supply voltage VVCC (V) Reference voltage vs. Load current CTL1 pin input current, Reference voltage vs. CTL1 pin input voltage CTL1 pin input current ICTL1 (μA) 500 5 4 3 2 Ta = + 25°C VVCC = 19 V VCTL1 = 5 V 1 5 10 15 20 25 30 35 10 400 300 8 Ta = + 25°C VVCC = 19 V IVREF = 0 mA VVREF 6 4 200 100 0 0 2 ICTL1 0 10 5 15 20 25 Load current IREF (mA) CTL1 pin input voltage VCTL1 (V) Error amplifier threshold voltage vs. Operating ambient temperature Error amplifier threshold voltage vs. Operating ambient temperature 8.500 8.475 8.450 8.425 8.400 VVCC = 19 V VCTL1 = 5 V 8.375 8.325 VCELLS = GND 8.350 8.300 -40 -20 0 +20 +40 +60 +80 +100 Operating ambient temperature Ta( °C) Error amplifier threshold voltage VTH (V) Reference voltage VVREF (V) Error amplifier threshold voltage VTH (V) 5 Power supply voltage VVCC (V) 6 0 6 0 Reference voltage VVREF (V) 5 Reference voltage VVREF (V) Power supply current Icc (mA) Power supply current vs. Power supply voltage 12.700 12.675 12.650 12.625 12.600 12.575 VVCC = 19 V VCTL1 = 5 V VCELLS = OPEN 12.550 12.525 12.500 -40 -20 0 +20 +40 +60 +80 +100 Operating ambient temperature Ta( °C) (Continued) 14 DS04–27265–3E MB39A132 (Continued) 16.900 16.875 16.850 16.825 16.800 VVCC = 19 V VCTL1 = 5 V VCELLS = 5 V 16.775 16.750 16.725 16.700 -40 -20 0 +20 +40 +60 +80 +100 Reference voltage VVREF (V) Reference voltage vs. Operating ambient temperature 5.08 VVCC = 19 V VCTL1 = 5 V IVREF =0 mA 5.06 5.04 5.02 5.00 4.98 4.96 4.94 4.92 -40 -20 0 +20 +40 +60 +80 +100 Operating Ambient temperature Ta ( °C) Triangular wave oscillation frequency vs. Operating ambient temperature Triangular wave oscillation frequency vs. Timing resistor 550 540 530 520 510 500 490 480 470 460 450 -40 VVCC = 19 V VCTL1 = 5 V RT = 33 kΩ -20 0 +20 +40 +60 +80 +100 Triangular wave oscillation frequency fosc (kHz) Operating ambient temperature Ta( °C) 10000 Ta = + 25°C VVCC = 19 V VCTL1 = 5 V 1000 100 10 1 10 100 Operating ambient temperature Ta ( °C) Timing resistor RRT(kΩ) Triangular wave oscillation frequency vs. Power supply voltage Power dissipation vs. Operating ambient temperature 550 540 530 520 510 500 490 480 470 460 450 Ta = + 25°C VCTL = 5 V RT = 47 kΩ 0 5 10 15 20 Power supply voltage VVCC (V) DS04–27265–3E 25 Power dissipation PD (mW) Triangular wave oscillation frequency fosc (kHz) Triangular wave oscillation frequency fosc (kHz) Error amplifier threshold voltage VTH (V) Error amplifier threshold voltage vs. Operating ambient temperature 5000 4400 4000 1000 With thermal vias 3000 2000 1900 Without thermal vias 1000 0 -40 -20 0 +20 +40 +60 +80 +100 Operating ambient temperature Ta( °C) 15 MB39A132 ■ FUNCTIONAL DESCRIPTION MB39A132 is an N-ch MOS driver-supported DC/DC converter which uses pulse width modulation (PWM) for charging Li-ion battery and controls the charge voltage and current when charging the battery. To stabilize the power supplied from a battery or an adapter to a system, this DC/DC converter has a battery charging control function and an AC adapter voltage detection function. When MB39A132 controls charge voltage (constant voltage mode), it can freely set the charge voltage with the voltage input to the ADJ3 pin (pin 18) and the CELLS pin (pin 25). It compares the BATT pin (pin 17) voltage and the internal reference voltage with the error amplifier (Error Amp3), outputs PWM control signals and then outputs the charge voltage freely set by the IC. When MB39A132 controls charge current (constant current mode), it amplifies the voltage drop occurring on both ends of the charge current sense resistor (Rs) by 25 times with the current detection amplifier (Current Amp2), and then outputs the amplified voltage to the OUTC2 pin (pin 11). It compares the output voltage of the current detection amplifier (Current Amp2) and the voltage set in the ADJ2 pin (pin 14) with the error amplifier (Error Amp2), and then outputs PWM control signals for executing constant-current charge. When MB95A132 controls AC adapter power, in the case of an output voltage drop in the AC adapter, the converter amplifies the voltage difference between the voltage applied to the -INC1 pin (pin 2) that has dropped and the +INC1 pin (pin 3) voltage (VVREF) by 25 times with the current detection amplifier (Error Amp1), and then outputs the amplified voltage value to the OUTC1 pin (pin 10). It compares the output voltage of the current detection amplifier (Current Amp1) to the ADJ1 pin (pin 7) voltage using the error amplifier (Error Amp1) to output PWM control signals for controlling the charge current so that the AC adapter power can be kept constant. The triangular wave voltage generated by the triangular wave oscillator is compared with the output voltage of one of the three error amplifiers (Error Amp1, Error Amp2 and Error Amp3) that has the lowest potential. The main FET is turned on during the period when the triangular wave voltage is lower than the error amplifier output voltage. In addition, the AC Comp. detects installation/removal of the AC adapter and its information is output through the ACOK pin (pin 5). 16 DS04–27265–3E MB39A132 1. Blocks of DC/DC Converter (1) Reference voltage block (REF) The reference voltage circuit uses the voltage supplied from the VCC pin (pin 1) to generate stable voltage (Typ. 5.0 V) that has undergone temperature compensation. The generated voltage is used as the reference power supply for the internal circuitry of the IC. This block can output load current of up to 1 mA from the reference voltage VREF pin (pin 21). (2) Triangular wave oscillator block (OSC) The triangular wave oscillator builds the capacitor for frequency setting into, and generates the triangular wave oscillation waveform by connecting the frequency setting resistor with the RT pin (pin 20). The triangular wave is input to the PWM comparator on the IC. Triangular wave oscillation frequency: fosc fosc (kHz) =: 17000/RT (kΩ) (3) Error amplifier block (Error Amp1) This amplifier detects the output signal from the current detection amplifier (Current Amp1) and outputs a PWM control signal. In addition, a stable phase compensation can be made available to the system by connecting the resistor and the capacitor to the COMP1 pin (pin 8). (4) Error amplifier block (Error Amp2) This amplifier detects the output signal from the current detection amplifier (Current Amp2), compares this to the output signal from the charge current control circuit, and outputs a PWM control signal to be used in controlling the charge current. In addition, a stable phase compensation can be made available to the system by connecting the resistor and the capacitor to the COMP2 pin (pin 15). (5) Error amplifier block (Error Amp3) This error amplifier (Error Amp3) detects the output voltage from the DC/DC converter, compares this to the output signal from the VO REFIN controller circuit, and outputs the PWM control signal. Arbitrary output voltage from 2 Cell to 4 Cell can be set by connecting an external resistor of charging voltage to ADJ3 pin (pin 18). In addition, a stable phase compensation can be made available to the system by connecting the resistor and the capacitor to the COMP3 pin (pin 16). (6) Current detection amplifier block (Current Amp1) The current detection amplifier (Current Amp1) amplifies the voltage difference between the +INC1 pin (pin 3) and the -INC1 pin (pin 2) by 25 times and outputs the amplified signal to the OUTC1 pin (pin 10). (7) Current detection amplifier block (Current Amp2) The current detection amplifier (Current Amp2) detects a voltage drop occurring at both ends of the charge current sense resistor (Rs) with the +INC2 pin (pin 12) and the -INC2 pin (pin 13). It outputs the signal amplified by 25 times to the inverted input pin of the following error amplifier (Error Amp2) and to the OUTC2 pin (pin 11). (8) PWM comparator block (PWM Comp.) The PWM comparator circuit is a voltage-pulse width converter for controlling the output duty according to the output voltage of the error amplifiers (Error Amp1 to Error Amp3). The triangular wave voltage generated by the triangular wave oscillator is compared with the output voltage of one of the three error amplifiers (Error Amp1, Error Amp2 and Error Amp3) that has the lowest potential. The main FET is turned on during the period when the triangular wave voltage is lower than the error amplifier output voltage. (9) Output block (OUT) The output block uses a CMOS configuration on both the high-side and the low-side, and can drive the external N-ch MOS FET. DS04–27265–3E 17 MB39A132 (10) Power supply control block (CTL1) The power supply control block controls the DC/DC converter operation. When the CTL1 pin (pin 23) is set to "L" level, the DC/DC converter enters standby mode. In the standby mode, only the AC adapter detection function is operable. (The typical supply current value is 6 μA in the standby mode.) CTL1 function table DC/DC converter CTL1 control AC adapter detection L OFF (Standby) ON (Active) H ON (Active) ON (Active) (11) Current Amp1 control block (CTL2) The Current Amp1 controller controls the Current Amp1 operation. When the CTL2 pin is set to "H" level, the Current Amp1 becomes operable. When the CTL1 pin (pin 23) is set to the "L" level and the CTL2 pin (pin32) is set to the "H" level after fullcharge, only Current Amp1 and the AC adapter detection function becomes operable. CTL2 function table CTL2 Current Amp1 AC adapter detection L OFF (Standby) ON (Active) H ON (Active) ON (Active) (12) Bias voltage block (VB) The bias voltage block outputs 5 V (Typ) for the power supply of the output circuit and for setting the bootstrap voltage. (13) Off time control block (Off Time Control) When this IC operates by high on-duty, voltage of both ends of bootstrap capacitor CB is decreasing gradually. In such the case, off time control block charges with CB by compulsorily generating off time (0.3 μs Typ). 18 DS04–27265–3E MB39A132 2. Protection Functions (1) Under voltage lockout protection circuit (VREF-UVLO) A momentary decrease in internal reference voltage (VREF) may cause malfunctions in the control IC, resulting in breakdown or degradation of the system. To prevent such malfunction, the under voltage lockout protection circuit detects internal reference voltage drop and fixes the OUT1 pin (pin 30) and the OUT2 pin (pin 27) at the “L” level. UVLO will be released when the internal reference voltage reaches the threshold voltage of the under voltage lockout protection circuit. Protection circuit (VREF-UVLO) operation function table When UVLO is operating (VREF voltage is lower than UVLO threshold voltage.), the logic value of the following pin is fixed. OUT1 OUT2 CS VB L L L L (2) Under voltage lockout protection circuit (VCC-UVLO, VB-UVLO) The transient state or the momentary decrease in power supply voltage, which occurs when the bias voltage (VB) for output circuit is turned on, may cause malfunctions in the control IC, resulting in breakdown or degradation of the system. To prevent such malfunction, the under voltage lockout protection circuit detects a bias voltage drop and fixes the OUT1 pin (pin 30) and the OUT2 pin (pin 27) at the “L” level. UVLO will be released when the power supply voltage or internal reference voltage reaches the threshold voltage of the under voltage lockout protection circuit. Protection circuit (VCC-UVLO, VB-UVLO) operation function table When UVLO is operating (VCC voltage or VB voltage is lower than UVLO threshold voltage.), the logical value of the following pin is fixed. OUT1 OUT2 CS L L L (3) Under input voltage detection block (UV Comp.) It compares the VCC pin (pin 1) voltage with the BATT pin (pin 17) voltage. If the VCC voltage is lower than the BATT pin voltage plus 0.1 V (Typ), the comparator fixes the OUT1 pin (pin 30) and the OUT2 pin (pin 27) at "L" level. The system resumes operation when the input voltage is higher than the threshold voltage of the under input voltage detection comparator. Protection circuit (UV Comp.) operation function table When under input voltage is detected (Input voltage is lower than UV Comp. threshold voltage), the logical value of the following pin is fixed. OUT1 OUT2 CS L DS04–27265–3E L L 19 MB39A132 (4) Overcurrent detection block (Over Current Det.) When this block detects that the potential difference between the +INC2 pin (pin 12) and the -INC2 pin (pin 13) exceeds 0.2 V (Typ), and excessive current flows in the charging direction due to a sudden change of load, this block will determine that overcurrent occurs, and sets the CS pin (pin 19) to "L" level and the ON duty to 0%. Afterward, when the overcurrent ceases to exist, the soft-start operation is started. Overcurrent detection value : Ioc det(A) = 0.2(V) RS(Ω) Charge current and overcurrent detection value by RS value (example) RS ADJ2 Io OCDet 20 mΩ 0.5 V to 4.4 V 0.85 A to 8.65 A 10 A 15 mΩ 0.5 V to 4.4 V 1.13 A to 11.5 A 13 A (5) Overtemperature detection The circuit protects an IC from heat destruction. If the temperature at the joint reaches +150 °C, the circuit set OUT1 (pin 30) and OUT2 (pin 27) pins to "L", and stops voltage output. In addition, if the temperature at the joint drops to +125 °C, the voltage output restarts again. When designing a DC/DC power supply system, do not exceed the absolute maximum ratings of this IC in order to prevent overtemperature protection from being activated. 20 DS04–27265–3E MB39A132 3. Detection Function AC adapter voltage detection block (AC Comp.) When the AC adapter voltage detection block (AC Comp.) detects that ACIN pin (pin 4) voltage is below 1.25 V (Typ), it and sets ACOK pin (pin 5) in the AC adapter voltage detection block to Hi-Z. In addition, power is supplied from the VCC pin (pin 1) or the VIN pin (pin 24), whichever has higher voltage. This function operates regardless of the input level of the CTL1 pin (pin 23) and CTL2 pin (pin 32). ACIN ACOK H L L Hi-Z R1 Microcontroller AC adapter ACIN R2 4 ACOK 5 <AC Comp.> AC adapter detection voltage setting VIN = Low to High Vth = (R1 + R2) / R2 × 1.25 V VIN = High to Low Vth = (R1 + R2) / R2 × 1.24 V DS04–27265–3E 21 MB39A132 ■ SETTING THE CHARGE VOLTAGE The charge voltage (DC/DC converter output voltage) can be set by the input voltage to ADJ3 pin (pin 18) and CELLS pin (pin 25). The ADJ3 pin can set charge voltage per cell. The value of charge voltage can be freely set when the ADJ3 pin is connected to an external resistor. When the VREF level voltage or the GND level voltage is input to the ADJ3 pin, the internal high-precision reference voltage set in advance can be used. When the VREF level voltage or the GND level voltage is input to the CELLS pin, or the CELLS pin is left unconnected, the number of series batteries can be set. The correspondence between the ADJ3 pin, the CELLS pin and charge voltage (DC/DC converter output voltage) is shown below. ADJ3 pin Input Voltage VREF pin (ADJ3 ≥ 4.1V) 2.4 V ≤ ADJ3 pin ≤ 3.9 V GND pin (0 V ≤ ADJ3 pin ≤ 0.9 V) External voltage setting (1.1 V ≤ ADJ3 pin ≤ 2.2 V) CELLS pin Charge Voltage Remarks GND 8.4 V 2 Cells × 4.20 V/Cell OPEN 12.6 V 3 Cells × 4.20 V/Cell VREF 16.8 V 4 Cells × 4.20 V/Cell GND 8.7 V 2 Cells × 4.35 V/Cell OPEN 13.05 V 3 Cells × 4.35 V/Cell VREF 17.4 V 4 Cells × 4.35 V/Cell GND 8.0 V 2 Cells × 4.00 V/Cell OPEN 12.0 V 3 Cells × 4.00 V/Cell VREF 16.0 V 4 Cells × 4.00 V/Cell GND 4 × ADJ3 pin voltage 2 Cells × 2 × ADJ3 pin voltage/Cell OPEN 6 × ADJ3 pin voltage 3 Cells × 2 × ADJ3 pin voltage/Cell VREF 8 × ADJ3 pin voltage 4 Cells × 2 × ADJ3 pin voltage/Cell • ADJ3 pin internal circuit VA ADJ3 VA 18 Comparator_A 2.175 V 2.1 V 2.0 V To Error Amp3 Selector 4.0 V Comparator_B Logic circuit 2.3 V Comparator_C 1.0 V 22 DS04–27265–3E MB39A132 ■ SETTING THE CHARGE CURRENT The error amplifier (Error Amp2) compares the output voltage of charge current control block set by the ADJ2 pin (pin 14) with the output signal from the charge current detection amplifier (Current Amp2), and outputs a the PWM control signal. The maximum charge current for battery can be set according to the ADJ2 pin voltage. When a current exceeding the setting current value is going to flow, constant current charge will be executed at that setting current value, and the charge voltage will drop. Battery charge current setting voltage: ADJ2 Charge current upper limit Io = Output voltage in the charge current control block − 0.075 Current detection amplifier gain (25 V/V Typ) × sense resistor RS(Ω) ADJ2 pin input voltage Charge current control block output voltage Charge current RS = 20 mΩ RS = 15 mΩ VREF pin (ADJ2 pin ≥ 4.6 V) 1.5 V 2.85 A 3.8 A External Voltage Setting (ADJ2 pin = GND pin to 4.4 V) VADJ2(V) 2 × (ADJ2 pin − 0.075)(A) 2.66 × (ADJ2 pin − 0.075) (A) • ADJ2 pin internal circuit ADJ2 To Error Amp2 14 1.5 V Selector Comparator_D + − 4.5 V • Example of the charge current setting (at RS = 20 mΩ) Io 4.4 V 0V 4.41 V 8.65 A 2.85 A External setting when ADJ2 = 0 V to 4.4 V 4.59 V ADJ2 VREF Internal reference voltage setting when ADJ2 = 4.6 V to VREF DS04–27265–3E 23 MB39A132 Io (mA) 1200 1000 800 At RS = 20 mΩ, +INC2 = 3 V to VVCC 600 400 Error < ±50 mA 200 VADJ2 (mV) 100 200 300 400 500 Max VADJ2 = 100 mV at Io=0 mA Typ VADJ2=75 mV at Io=0 mA Min VADJ2 = 50 mV at Io=0 mA Io=0 mA at VADJ2=0 V 24 600 DS04–27265–3E MB39A132 ■ SETTING DYNAMICALLY-CONTROLLED CHARGING With the connection shown below, when the voltage of the AC adapter (VIN) drops and reaches Vth, the result of the equation shown below, the converter becomes dynamically-controlled charging mode and then controls charge current to maintain a constant power level of the AC adapter. AC adapter voltage in dynamically-controlled-charging mode: Vth 1 Av Vth = [(1 − × R4 R1 + R2 )VREF + 3 mV] × R3 + R4 R2 VREF = Reference voltage(5.0 V Typ), AV = Current detection amplifier block voltage gain (25.0 Typ) -INE1 VIN VREF(5 V) 9 OUTC1 10 <Current Amp1> +INC1 3 R1 <Error Amp1> -INC1 2 R2 R3 ADJ1 7 R4 DS04–27265–3E 25 MB39A132 ■ SETTING THE SOFT-START TIME To prevent rush current at start-up of IC, the soft-start time can be set by connecting a soft-start capacitor (CS) to the CS pin (pin 19). When the CTL1 pin (pin 23) and the CTL2 pin (pin 32) are set to “H” level and the IC is started (Vcc 3 ≥ UVLO threshold voltage), the external capacitor (Cs) for soft-start (CS) connected to the CS pin is charged at 10 μA. The output ON duty depends on the result of comparison done by the PWM comparator among the COMP1 pin (pin 8) voltage, the COMP2 pin (pin15) voltage, the COMP3 pin (pin16) voltage and the triangular wave oscillator output voltage (CT). During soft-start, the COMP1 pin, the COMP2 pin, and the COMP3 pin voltages are clamped so that the voltages of those three pins will not exceed the CS pin voltage. Therefore, the output voltage of the DC/DC converter and current increase can be set by the output ON duty in proportion to rise of the CS pin voltage. The ON duty is affected by the ramp voltage of the COMP1 pin, the COMP2 pin, and the COMP3 pin until the output voltage of one of the three Error Amp reaches the DC/DC converter loop control voltage. Soft-start time is obtained from the following formula. Soft-start time (time for the output ON duty to reach 80%): ts(s) =: 0.23 × Cs (μF) CT COMP1 to COMP3 CS CS COMP1 to COMP3 CT 0V OUT1 OUT1 0V Error Amp3 threshold voltage Vo Vo 0V Io Io 0A 26 DS04–27265–3E MB39A132 ■ TRANSIT RESPONSE AT STEP LOAD CHANGE The constant voltage control loop and the constant current control loop are independent of each other . When a load changes suddenly, a control loop is replaced by the other. Overshoot of the battery voltage and current is generated by the delay occurring in a control loop at a mode change. The delay time is determined by the phase compensation components values. When the constant current control changes to the constant voltage control after the battery is removed, the control period with higher duty than the setting charge voltage occurs, resulting in a voltage overshoot. However, since the battery is removed, no excessive voltage is to be applied to the battery. When the constant voltage control changes to the constant current control after the battery is inserted, the control period with higher duty than the rated charge current occurs, resulting in current overshoot. In MB39A132, a current overshoot lasting less than 10 ms is not deemed to be a current overshoot. Error Amp3 output Error Amp2 output Error Amp2 output Error Amp3 output Constant current Battery voltage Battery current Constant voltage Constant current When the charge control switches from the constant current control to the constant voltage control, the control period with higher duty than the rated charge voltage occurs, resulting in a voltage overshoot. In MB39A132, a current overshoot lasting less than 10 ms is not deemed to be a current overshoot. 10 ms DS04–27265–3E 27 MB39A132 ■ CONNECTION WITHOUT USING THE CURRENT AMP1,CURRENT AMP2 AND THE ERROR AMP1, ERROR AMP2 When Current Amp1, 2 and Error Amp1, 2 are not used, connect the +INC1 pin (pin 3) and -INC1 pin (pin 2) to VREF pin (pin 21), the +INC2 pin (pin 12) to the -INC2 pin (pin 13), leave the OUTC1 pin (pin 10), OUTC2 pin (pin11), COMP1 pin (pin 8), and COMP2 pin (pin 15) open and connect the ADJ1 pin (pin 7) and ADJ2 pin (pin 14) to VREF pin. 28 3 +INC1 +INC2 12 2 -INC1 -INC2 13 “OPEN” 10 OUTC1 “OPEN” 11 OUTC2 21 VREF 7 ADJ1 14 ADJ2 “OPEN” 8 COMP1 “OPEN” 15 COMP2 Battery DS04–27265–3E MB39A132 ■ I/O EQUIVALENT CIRCUIT <Reference voltage block> <Control block> VCC 1 1.22 V CTL1 23 21 VREF ESD protection element CTL2 32 140 kΩ 37 kΩ 172 kΩ 172 kΩ 216 kΩ 12 kΩ GND 22 GND 22 GND 22 <Triangular wave oscillator block> <Error amplifier block (Error Amp1)> VIN 24 VREF 21 VREF 21 COMP1 -INE1 20 RT 8 9 GND 22 GND 22 7 <Error amplifier block (Error Amp2)> ADJ1 <Error amplifier block (Error Amp3)> VREF 21 VREF 21 COMP2 15 +INE2 COMP3 16 -INE3 6 GND 22 GND 22 +INE3 <Current detection amplifier block (Current Amp1)> VIN 24 VCC <Current detection amplifier block (Current Amp2)> 1 VREF +INC1 3 21 OUTC1 +INC2 12 10 OUTC2 11 40 kΩ 160 kΩ 90 kΩ 40 kΩ GND 22 GND 2 -INC1 22 13 -INC2 (Continued) DS04–27265–3E 29 MB39A132 (Continued) <PWM comparator block > <Soft-start block> VREF 21 VREF 21 COMP1 8 COMP2 15 19 CS COMP3 16 GND 22 GND 22 <AC adapter detection block > <Output block > CB VCC 31 1 VIN 24 ACIN 30 OUT1 5 4 ACOK LX 29 VB 28 27 OUT2 GND 22 GND <Bias voltage block > VCC 26 PGND <Charge voltage setting block> SELECTER VREF 21 1 28 VB +INE3 ADJ3 18 200 kΩ 2.5 V 4V 2.3 V 200 kΩ GND 22 1V 22 GND 22 <Charge current setting block> <Cell switch block > VREF 21 BATT 17 VREF 21 CELLS 25 SELECTER ADJ2 14 +INE2 6 4.5 V GND GND 22 GND 30 -INE3 22 DS04–27265–3E DS04–27265–3E SGND R14 30 kΩ R28 0 Ω R27 *2 R42 22 kΩ 11 10 9 OUTC1 -INE1 R26 *2 +INC2 OUTC2 OUTC2 14 R7 10 kΩ C13 0.001 μF 13 M1 MB39A132 12 27 C8 0.1 μF 28 ADJ2 OUTC1 8 7 6 5 4 29 C7 1 μF R4 *1 25 16 26 15 COMP2 C22 *2 C21 820 pF C14 2200 pF R8 4.7 kΩ COMP1 ADJ1 -INE3 ACOK ACIN 3 30 CTL2 31 CB 32 OUT1 +INC1 C6 0.1 μF R3 10 Ω LX 2 1 D2 BAT54HT1 *2 C2 Q1 μPA2755 VB -INC1 VCC 10 μF C1 R39 0Ω OUT2 R13 20 kΩ C15 *2 R1 20 mΩ PGND ACOK R18 130 kΩ R10 91 kΩ C18 0.22 μF R17 15 kΩ R19 30 kΩ R16 100 kΩ R15 200 kΩ TPCA8102 Q4 R9 6.8 kΩ TPCA8102 Q3 CELLS R11 10 kΩ CTL2 GND VIN R38 *2 VSYS R6 *2 C12 *2 17 18 19 20 21 22 23 24 BATT ADJ3 CS RT R41 1 kΩ C20 120 pF C11 0.1 μF R5 33 kΩ C10 0.1 μF GND VREF C9 0.1 μF R32 *2 SW1-1 C17 *2 R31 *1 R2 20 mΩ CTL1 VIN Q8 DTA144EET1G D1 *2 C16 *2 R30 *1 L1 CDRH104RNP-100NC VSYS2 R40 2.4 kΩ R21 *2 R20 0Ω R29 *1 D4 *2 C3 10 μF Q7 *2 R33 47 kΩ C5 *2 R37 *2 R23 0Ω R22 51 kΩ R35 *2 SW1-2 R34 10 kΩ R25 *2 R24 0Ω Q6 DTC144EET1G Q5 TPCA8102 C4 10 μF C19 *2 GND VO ADJ2 ADJ3 VREF CTL1 CELLS R43 *2 ACOFF R36 *2 D3 *2 MB39A132 ■ TYPICAL APPLICATION CIRCUIT COMP3 -INC2 To Microcontroller *1 : Pattern Short *2 : Not mounted 31 MB39A132 • Parts list Component Item Specification Vendor Package Part Number M1 IC ⎯ FML QFN-32 MB39A132 Q1 Dual N-ch FET VDS = − 30 V, ID = 8 A (Max) NEC SOP-8 μPA2755 Q3 P-ch FET SOP VDS = − 30 V, TOSHIBA Advance ID = 40 A (Max) TPCA8102 Q4 P-ch FET SOP VDS = − 30 V, TOSHIBA Advance ID = 40 A (Max) TPCA8102 Q5 P-ch FET SOP VDS = − 30 V, TOSHIBA Advance ID = 40 A (Max) TPCA8102 Q6 Transistor Q7 Transistor Q8 Transistor D1 Diode D2 Diode D3 Diode Not mounted D4 Diode Not mounted L1 Inductor C1 Ceramic capacitor C2 Ceramic capacitor C3 Ceramic capacitor 10 μF(25 V) TDK 3216 C3216JB1E106K C4 Ceramic capacitor 10 μF(25 V) TDK 3216 C3216JB1E106K C5 Ceramic capacitor C6 Ceramic capacitor 0.1 μF(50 V) TDK 1608 C1608JB1H104K C7 Ceramic capacitor 1 μF(16 V) TDK 1608 C1608JB1C105K C9 Ceramic capacitor 0.1 μF(50 V) TDK 1608 C1608JB1H104K C10 Ceramic capacitor 0.1 μF(50 V) TDK 1608 C1608JB1H104K C11 Ceramic capacitor 0.1 μF(50 V) TDK 1608 C1608JB1H104K C12 Ceramic capacitor C13 Ceramic capacitor 0.001 μF(50 V) TDK 1608 C1608JB1H102K C14 Ceramic capacitor 2200 pF(50 V) TDK 1608 C1608CH1H222J C15 Ceramic capacitor Not mounted C16 Ceramic capacitor Not mounted C17 Ceramic capacitor Not mounted C18 Ceramic capacitor C19 Ceramic capacitor C20 Ceramic capacitor 120 pF(50 V) TDK 1608 C1608CH1H121J C21 Ceramic capacitor 820 pF(50 V) TDK 1608 C1608CH1H821J VCEO = 50 V ON Semi SC-75 Remarks DTC144EET1G Not mounted VCEO = 50 V ON Semi SC-75 DTA144EET1G Not mounted VF = 0.4 V (Max) at IF = 10 mA ON Semi SOD-323 10 μH 35 mΩ SUMIDA Max Irms = 4.4 A 10 μF(25 V) TDK BAT54HT1 SMD CDRH104RNP-100NC 3216 C3216JB1E106K Not mounted Not mounted Not mounted 0.22 μF(25 V) TDK 1608 C1608JB1E224K Not mounted (Continued) 32 DS04–27265–3E MB39A132 Component Item C22 Ceramic capacitor R1 Resistor 20 mΩ KOA SL1 SL1TTE20L0D R2 Resistor 20 mΩ KOA SL1 SL1TTE20L0D R3 Resistor 10 Ω SSM 1608 RR0816Q-100-D R4 Resistor R5 Resistor R6 Resistor R7 Resistor 10 kΩ SSM 1608 RR0816P103D R8 Resistor 4.7 kΩ SSM 1608 RR0816P472D R9 Resistor 6.8 kΩ SSM 1608 RR0816P682D R10 Resistor 91 kΩ SSM 1608 RR0816P913D R11 Resistor 10 kΩ SSM 1608 RR0816P103D R13 Resistor 20 kΩ SSM 1608 RR0816P203D R14 Resistor 30 kΩ SSM 1608 RR0816P303D R15 Resistor 200 kΩ SSM 1608 RR0816P204D R16 Resistor 100 kΩ SSM 1608 RR0816P104D R17 Resistor 15 kΩ SSM 1608 RR0816P153D R18 Resistor 130 kΩ SSM 1608 RR0816P134D R19 Resistor 30 kΩ SSM 1608 RR0816P303D R20 Resistor 0Ω KOA 1608 RK73Z1J R21 Resistor R22 Resistor 51 kΩ SSM 1608 RR0816P513D R23 Resistor 0Ω KOA 1608 RK73Z1J R24 Resistor 0Ω KOA 1608 RK73Z1J R25 Resistor Not mounted R26 Resistor Not mounted R27 Resistor Not mounted R28 Resistor R29 Resistor 1608 Pattern short R30 Resistor 1608 Pattern short R31 Resistor 1608 Pattern short R32 Resistor R33 Resistor 47 kΩ SSM 1608 RR0816P473D R34 Resistor 10 kΩ SSM 1608 RR0816P103D R35 Resistor Not mounted R36 Resistor Not mounted R37 Resistor Not mounted Specification Vendor Package Parts No. Remarks Not mounted 1608 33 kΩ SSM 1608 Pattern cut Pattern short RR0816P333D Not mounted Not mounted 0Ω KOA 1608 RK73Z1J Not mounted (Continued) DS04–27265–3E 33 MB39A132 (Continued) Component 34 Item Specification Vendor Package Parts No. R38 Resistor R39 Resistor 0Ω KOA 1608 RK73Z1J R40 Resistor 2.4 kΩ SSM 1608 RR0816P242D R41 Resistor 1 kΩ SSM 1608 RR0816P102D R42 Resistor 22 kΩ SSM 1608 RR0816P223D R43 Resistor Remarks Not mounted FML : Fujitsu Microelectronics Limited NEC : NEC Electronics Corporation TOSHIBA : TOSHIBA Corporation ON Semi : ON Semiconductor Corporation SUMIDA : SUMIDA Corporation TDK : TDK Corporation KOA : KOA Corporation SSM : SUSUMU Co.,Ltd Not mounted DS04–27265–3E MB39A132 ■ APPLICATION NOTE • Inductor selection As a rough guide, the inductance of an inductor should keep the peak-to-peak value of inductor ripple current below 50% of the maximum charge current. The inductance fulfilling the above condition can be found by the following formula. L≥ L VIN − VO × LOR × IOMAX VO VIN × fOSC : Inductance [H] IOMAX : Maximum charge current [A] LOR : Inductor ripple current peak to peak value - Maximum charge current ratio (0.5) VIN : Switching power-supply voltage [V] VO : Charge voltage [V] fOSC : Switching frequency [Hz] The minimum charge current (critical current) in the condition that inductor current does not flow in reverse can be found by the following formula. IOC = VO 2×L VIN − VO × VIN × fOSC IOC : Critical current [A] L : Inductance [H] VIN : Switching power-supply voltage [V] VO : Charge voltage [V] fOSC : Switching frequency [Hz] The maximum value of the current flowing through the inductor needs to be found in order to determine whether the current flowing through the inductor is within the rated value. The maximum current flowing through the inductor can be found by the following formula. ILMAX ≥ IoMAX + ΔIL 2 ILMAX : Maximum inductor current [A] IOMAX : Maximum charge current [A] ΔIL ΔIL ≥ : Inductor ripple current peak to peak value [A] VIN − VO L × VO VIN × fOSC Inductor current ILMAX IoMAX The current is shifting according to the charge current. IOC ΔIL Time 0 DS04–27265–3E 35 MB39A132 • SWFET selection If MB39A132 is used for the charger for a notebook PC, since the output voltage of an AC adapter, which is the input voltage of an SWFET, is 25 V or less, in general, a 30 V class MOS FET can be used as the SWFET. Obtain the maximum value of the current flowing through the SWFET in order to determine whether the current flowing through the SWFET is within the rated value. The maximum current flowing through the SWFET can be found by the following formula. IDMAX ≥ IoMAX + ΔIL 2 IDMAX : Maximum SWFET drain current [A] IOMAX : Maximum charge current [A] ΔIL : Inductor ripple current peak to peak value [A] In addition, find the loss of the SWFET in order to determine whether the allowable loss of the SWFET is within the rated value. The allowable loss of the high-side of FET can be found by the following formula. PHisideFET = PRON_Hiside + PSW_Hiside PHisideFET : FET loss of high-side [W] PRON_Hiside: FET continuity loss of high-side [W] PSW_Hiside : FET switching loss of high-side [W] FET continuity loss of high-side PRON_Hiside = IOMAX2 × VO VIN × RON_Hiside PRON_Hiside : FET continuity loss of high-side [W] IOMAX : Maximum charge current [A] VIN : Switching power supply voltage [V] VO : Output voltage [V] RON_Hiside : FET ON resistance of high-side [Ω] FET switching loss of high-side PSW_Hiside = VIN × fOSC × (Ibtm × Tr + Itop × Tf) 2 PSW_Hiside : FET switching loss of high-side [W] 36 VIN : Switching power supply voltage [V] fOSC : Switching frequency (Hz) Ibtm : Bottom value of ripple current of inductor [A] DS04–27265–3E MB39A132 Ibtm = IOMAX − ΔIL 2 Itop : Top value of ripple current of inductor [A] Itop = IOMAX − ΔIL 2 ΔIL : Inductor ripple current peak to peak value [A] Tr : FET turn-on time of high-side [s] Tf : FET turn-off time of high-side [s] Tr and Tf can be easily found by the following formula. Tr = Qgd Qgd × 4 5 − Vgs(on) Tf = Qgd × 1 Vgs(on) : Gate-Drain charge of high-side FET [C] Vgs(on) : Gate-Source voltage of high-side FET with Qgd [V] The FET loss of the low-side can be found by the following formula. PLosideFET = PRON_Loside = IOMAX2 × (1 − VO VIN ) × Ron_Loside PLosideFET : FET loss of low-side [W] PRON_Loside : FET continuity loss of low-side [W] IOMAX : Maximum charge current [A] VIN : Switching power supply voltage [V] VO : Output voltage [V] Ron_Loside : FET ON resistance of synchronous rectification [Ω] The FET voltage transiting between drain-source of the low-side is generally small. The SWFET loss is omitted in this document as it is negligible. Since the power for driving gate of SWFET is supplied by LDO in IC, the SWFET allowable maximum total gate charge (QgTotalMax) is determined by the following formula. QgTotalMax ≤ 0.03 fOSC QgTotalMax : High-side FET allowable maximum total charge [C] fOSC DS04–27265–3E : Oscillation frequency [Hz] 37 MB39A132 • Fly-back diode selection In general, the fly-back diode is not necessary. However, if conversion efficiency becomes a major concern, it can be improved by adding a fly-back diode. Select a Schottky barrier diode (SBD) that has a small forward voltage drop. Since this DC/DC converter control IC adopts synchronous rectification, the length of the time in which current flows through a fly-back diode is limited by the synchronous rectification period. Therefore, select a fly-back diode whose current does not exceed the rated peak forward surge current (IFSM). The peak forward surge current value of the fly-back diode can be found by the following formula. IFSM ≥ IOMAX + ΔIL 2 IFSM : Rated value of fly-back diode peak forward surge current [A] IOMAX : Maximum charge current [A] ΔIL : Inductor ripple current peak to peak value [A] The rating of a fly-back diode can be found by the following formula. VR_Fly > VIN VR_Fly : DC reverse voltage of fly-back diode [V] VIN 38 : Switching power supply voltage [V] DS04–27265–3E MB39A132 • Output capacitor selection Since a high ESR causes the output ripple voltage to increase, a low-ESR capacitor is needs to be used in order to reduce the output ripple voltage. Use a capacitor that has sufficient ratings to surge current generated when the battery is inserted or removed. Generally, the ceramic capacitor is used as the output capacitor. With the switching ripple voltage taken into consideration, the minimum capacitance required can be found by the following formula. Co ≥ Co 1 2π × fosc × (ΔVO/ΔIL − ESR) : Output capacitance [F] ESR : Series resistance element of output capacitance [Ω] ΔVO : Switching ripple voltage [V] ΔIL : Inductor ripple current peak to peak value [A] fosc : Switching frequency [Hz] Since an overshoot occurs in the DC/DC converter output voltage when a battery being charged is removed, use a capacitor having sufficient withstand voltage. Generally, the capacitor having a rated withstand voltage higher than the maximum input voltage is sued. Moreover, use a capacitor having sufficient tolerance for allowable ripple current. The allowable ripple current required can be found by the following formula. Irms ≥ ΔIL 2√3 Irms : Allowable ripple current (Root-mean-square value) [A] ΔIL : Inductor ripple current peak-to-peak value [A] DS04–27265–3E 39 MB39A132 • Input capacitor selection Select an input capacitor that has an ESR as small as possible. A ceramic capacitor is ideal. If a highcapacitance capacitor is needed for which there is no suitable ceramic capacitor use a polymer capacitor or a tantalum capacitor having a low ESR. The ripple voltage by the switching operation of the DC/DC converter is generated in the power supply voltage. Please consider the lower limit value of the input capacitor according to the allowable ripple voltage. The ripple voltage of the power supply can be easily found by the following formula. ΔVIN = IOMAX CIN × VO VIN × fOSC + ESR × (IOMAX + ΔIL 2 ) ΔVIN : Switching power supply ripple voltage peak-to-peak value [V] IOMAX : Maximum charge current [A] CIN : Input capacitance [F] VIN : Switching power supply voltage [V] VO : Charge voltage [V] fOSC : Switching frequency [Hz] ESR : Series resistance element of input capacitance [Ω] ΔIL : Inductor ripple current peak-to-peak value [A] The ripple voltage of the power supply can be decreased by raising the switching frequency besides using the capacitor. The capacitor has its own frequency, temperature and bias voltage, therefore its effective capacitance can be extremely small depending on the application conditions. Select a capacitor whose rating has a sufficient margin against input voltage. In addition, when using a capacitor having an allowable ripple current rating, select a capacitor that has a sufficient margin against ripple current. The allowable ripple current can be found by the following formula. Irms ≥ IOMAX × √VO × (VIN − VO) VIN Irms : Allowable ripple current (Root-mean-square value) [A] IOMAX : Maximum charge current [A] 40 VIN : Switching power supply voltage [V] VO : Charge voltage [V] DS04–27265–3E MB39A132 • Bootstrap diode selection Select a Schottky barrier diode (SBD) that has a small forward voltage drop. The current to drive the gate of High-side FET flows to the SBD of the bootstrap circuit. The average current can be found by the following formula. Select a bootstrap diode that keep the average current below the current rating. ID ≥ Qg × fOSC ID : Forward current [A] Qg : FET total gate electric charge of high-side [C] fOSC : Oscillation frequency [Hz] The rating of the bootstrap diode can be found by the following formula. VR_BOOT > VIN VR_BOOT : Bootstrap diode DC reverse voltage [V] VIN : Switching power supply voltage [V] • Bootstrap capacitor selection The bootstrap capacitor needs to be sufficiently charged to drive the gate of the high-side FET. Therefore, select a capacitor that can store charge at least 10 times Qg of the high-side FET as the bootstrap capacitor. CBOOT ≥ 10 × Qg VB CBOOT : Bootstrap capacitance [F] Qg : Withstand voltage FET gate charge [C] VB : VB voltage [V] The rating of bootstrap capacitor can be found by the following formula. VCBOOT > VIN VCBOOT : Rating of bootstrap capacitor [V] VIN : Switching power supply voltage [V] DS04–27265–3E 41 MB39A132 • VB capacitor Although the typical capacitance value for a VB capacitor is 1 μF, it has to be adjusted if the switching FET used has a large Qg. The bootstrap capacitor needs to be sufficiently charged to drive the gate of the highside FET. Therefore, select a capacitor that can store charge at least 100 times the total of Qg of the highside FET and Qg of the low-side switching FET as the VB capacitor. CVB ≥ 100 × Qg VB CVB : VB pin capacitance [F] Qg : Total gate charge of high-side FET and low-side switching FET [C] VB : VB voltage [V] The rating of VB capacitor can be found by the formula. VCVB > VB VCVB : Withstand voltage of VB capacitor [V] VB 42 :VB voltage [V] DS04–27265–3E MB39A132 • Design of phase compensation circuit (1) Constant voltage (CV) mode phase compensation circuit When a low-ESR capacitor, such as a ceramic capacitor, is used as the output capacitor, it is easier for the DC/DC converter to oscillate as the phase delay approaches 180 degrees due to the resonance frequency of LC. In this situation, perform phase compensation by connecting a RC phase lead compensator between the -INE3 pin (pin 6) and the COMP3 pin (pin 16), and between the -INE3 pin (pin 6) and the BATT pin (pin 17) . 2pole-2zero phase compensation circuit VO BATT CZ2 CZ1 RZ2 6 17 -INE3 R1 16 + R2 To PWM Comp. COMP3 Error Amp3 Vrefint1 The constant for the phase lead compensation circuit can be found by the following formula. CZ1 =: 5.1 × 10 − 6 (2 × CELLS − 1) fLC RZ2 =: 8.9 × 104 × CZ2 =: fCO VIN × fLC + 3600 1 2π × RZ2 × fLC CELLS : Number of battery series cells fLC : Resonance frequency of inductor and output capacitor [Hz] VIN : Switching power supply voltage [V] fCO : Crossover frequency [Hz] As for the crossover frequency (fco) indicating the bandwidth of the control loop of the DC/DC converter, while a high crossover frequency is good for quick response, it increases the risk of oscillation due to an insufficient phase margin. Though this crossover frequency can be freely set, keep the frequency in the range of 1/10-1/5 of the switching frequency (fosc) whenever possible. DS04–27265–3E 43 MB39A132 (2) Constant current (CC) mode phase compensation circuit In constant current mode, since the output capacitor impedance has little effects on the loop response characteristic, connect the 1pole-1zero phase compensation circuit with the output pin (COMP2) of the error amplifier 2 (gm amplifier). 1pole-1zero phase compensation circuit BATT Current Amp2 17 - 12 + Rs - COMP2 To PWM Comp. 15 + +INC2 Error Amp2 Vrefint2 Rc Cc RC and Cc of the phase lead circuit can be found by the following formula. RC =: 1.2 × 104 × CC =: 44 fCO × L Rs × VIN √L × Co Rc Rs : Charge current detection resistance [Ω] VIN : Switching power supply voltage [V] L : Inductor value [H] Co : Output capacitance [F] fCO : Crossover frequency [Hz] DS04–27265–3E MB39A132 • Allowable loss, and thermal design In general, the allowable loss and thermal design of this IC can be ignored because this IC is highly effective. However, when this IC is used with high power supply voltage, high switching frequency, high load, or high temperature, it is necessary to take account of the allowable loss and thermal design while using this IC. The IC internal loss (PIC) can be found by the following formula. PIC = VCC × (ICC + Qg × fOSC ) PIC : IC internal loss [W] VCC : Power supply voltage (VIN) [V] ICC : Power supply current [A] (3.6 mA Max) Qg : Total charge of all switching FET [C] (Total charge at Vgs = 5 V) fOSC : Switching frequency [Hz] The junction temperature (Tj) can be found by the following formula. Tj = Ta + θja × PIC Tj : Junction temperature [ °C] Ta : Ambient temperature [ °C] θja : QFN-32 package heat resistance (22.7 °C/W) PIC : IC internal loss [W] DS04–27265–3E 45 MB39A132 • Board layout When designing the layout, consider the points listed below. Take account of the following points when designing the board layout. - Place a GND plane on the IC mounting surface whenever possible. Connect bypass capacitors connected to switching components to the switching GND (PGND pin), and controller components to GND (GND pin). Separate different GND so that no large current path passes through the controller GND (GND pins). When designing the connection of the controller GND and the switching GND, make their connection underneath the IC. Connect PGND to the controller GND at only one point to prevent large current from flowing to the controller GND. Connect the controller GND to PGND only at one point of PGND in order to prevent a large current path from passing the controller GND. - Connect to the input capacitor (CIN), SWFET, SBD, inductor (L), sense resistor (Rs), output capacitor (Co) on the surface layer. Do not connect to them via any through-hole. - For a loop composed of input capacitors (CIN), switching FET and SBD, minimize its current loop. When minimizing routing and loops, give priority to this loop over others. - Create through-holes directly next to the GND pins of the input capacitor (CIN), SBD, output capacitor (Co), and connect these pins to the GND of the inner layer. - Place the boot strap capacitor (CBOOT) as close to the CB, LX pins as possible. - Place the input capacitor (CIN) and high-side FET as close together as possible. Bring out the net of the LX pin from a point close to the source pin of the high-side FET. Large currents momentarily flow through the net of the LX pin. Use a wiring width of about 0.8 mm, and minimize the length of routing. - Large currents momentarily flow through the nets of the OUT1, OUT2 pins, which are connected to the switching FET gate. Use a wiring width of about 0.8 mm and minimize the length of routing. - Place the bypass capacitor connected to VCC, VIN, VREF, and VB pins, and the resistance connected to the RT pin as close to the respective pins as possible. Moreover, connect the bypass capacitor and the GND pin of the fOSC:setting resistance in close proximity to the GND pin of the IC. (Strengthen the connection to the internal layer GND by making through-holes in close proximity to each of the GND pin of the IC, terminals of bypass capacitors, terminals of the fosc setting resistors.) - -INCx,+INCx, BATT,COMPx,RT pins is sensitive to noise. Therefore, minimize the routing of these pins and keep them as far away from switching components as possible. - The remote sensing (Kelvin connection) of the routing of the -INC2 and +INC2 pins are very sensitive to noise. Therefore, make their routing close to each other and keep the routing as far away from switching components as possible. GND routing example Example of switching components High-side FET VIN PGND VCC Cin To LX pin VIN PGND Low-side FET SBD VREF RT GND Co L Connect the PGND to the GND at a single point directly under the IC. Surface layer VO RS To BATT pin To +INC2 pin To -INC2 pin To feedback line Inner layer 46 DS04–27265–3E MB39A132 ■ REFERENCE DATA Unless otherwise specified, the measurement conditions are VIN = 19 V, Io = 2.85 A, Li+ battery 4 Cells, and Ta = + 25 °C. Conversion efficiency - Charge current (Constant voltage mode) Charge voltage - Charge current 20 4 Cells 98 96 18 Charge voltage Vo(V) Conversion efficiency η(%) 100 3 Cells 94 2 Cells 92 90 88 86 84 4 Cells 16 14 3 Cells 12 10 2 Cells 8 6 4 82 2 80 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 0.0 0.5 Charge current Io(A) 1.0 1.5 2.0 2.5 3.0 3.5 Charge current Io(A) Conversion efficiency - Charge voltage (Constant current mode) Conversion efficiency η(%) 100 95 90 85 80 75 70 65 60 55 50 0 2 4 6 8 10 12 14 16 18 Charge voltage Vo(V) Switching waveform (Constant voltage mode) Switching waveform (Constant current mode) OUT1 (V) 20 OUT1 (V) OUT1 20 OUT2 (V) 0 Io = 1.5 A SW1-2 = OFF OUT2 (V) OUT1 OUT2 5 OUT2 LX ( V ) 20 0 VO = 12 V SW1-2 = OFF 5 0 0 LX ( V ) 20 LX 10 10 0 0 400 ns/div LX 400 ns/div (Continued) DS04–27265–3E 47 MB39A132 Start and stop (Constant voltage mode) Start and stop (Constant voltage mode) Vo (V) Vo (V) 18 18 VO VO 16 16 14 14 SW1-2 = OFF Io(A) Io(A) VCTL (V) 10 SW1-2 = OFF 12 12 Io 1 0 VCTL VCTL (V) 10 Start and stop (Constant current mode) VO (V) VO (V) 18 18 16 16 VO VO 14 14 Io(A) Io 3 SW1-2 = OFF VCTL (V) 10 12 20 ms/div Io(A) Io 3 2 2 SW1-2 = OFF 1 VCTL (V) 0 10 VCTL 0 0 20 ms/div Start and stop (Constant current mode) 12 1 VCTL 0 20 ms/div 0 Io 0 1 0 VCTL 20 ms/div (Continued) 48 DS04–27265–3E MB39A132 (Continued) Load-step response (Constant voltage mode) Battery removal Load-step response (Constant voltage mode) Battery insertion VO (V) VO (V) 18 18 VO VO 16 VOUT1 14 10 0 VOUT2 (V) 16 VOUT1 (V) 20 14 0 10 0 VOUT2 (V) VOUT2 SW1-2 = OFF CV to CV Io 2 ms/div VOUT2 SW1-2 = OFF CV to CV 2 Io 2 ms/div 0 Io(A) 2 0 Load-step response (Constant current mode) Battery removal VO (V) VO (V) 18 VO SW1-2 = OFF CV to CC 16 VOUT1 10 0 VOUT2 (V) 0 Io(A) Load-step response (Constant current mode) Battery insertion 14 VOUT1 (V) 20 VOUT1 18 16 VOUT1 (V) 20 14 0 10 Io(A) VOUT2 4 VO 0 VOUT2 (V) VOUT1 (V) 20 VOUT1 0 VOUT2 SW1-2 = OFF CC to CV 2 2 Io DS04–27265–3E 2 ms/div 0 Io(A) 4 Io 2 ms/div 0 49 MB39A132 ■ USAGE PRECAUTION 1. Do not configure the IC over the maximum ratings If the lC is used over the maximum ratings, the LSl may be permanently damaged. It is preferable for the device to be normally operated within the recommended usage conditions. Usage outside of these conditions can have a bad effect on the reliability of the LSI. 2. Use the devices within recommended operating conditions The recommended operating conditions are the recommended values that guarantee the normal operations of LSI. The electrical ratings are guaranteed when the device is used within the recommended operating conditions and under the conditions stated for each item. 3. Printed circuit board ground lines should be set up with consideration for common impedance 4. Take appropriate measures against static electricity • Containers for semiconductor materials should have anti-static protection or be made of conductive material. • After mounting, printed circuit boards should be stored and shipped in conductive bags or containers. • Work platforms, tools, and instruments should be properly grounded. • Working personnel should be grounded with resistance of 250 kΩ to 1 MΩ in series between body and ground. 5. Do not apply negative voltages The use of negative voltages below −0.3 V may cause the parasitic transistor to be activated on LSI lines, which can cause malfunctions. ■ ORDERING INFORMATION Part number MB39A132QN Package Remarks 32-pin plastic QFN (LCC-32P-M17) ■ EV BOARD ORDERING INFORMATION EV board part No. MB39A132EVB-02 EV board version No. Remarks Board rev.2.0 QFN-32 ■ RoHS COMPLIANCE INFORMATION OF LEAD (Pb) FREE VERSION The LSI products of Fujitsu Microelectronics with “E1” are compliant with RoHS Directive, and has observed the standard of lead, cadmium, mercury, hexavalent chromium, polybrominated biphenyls (PBB) , and polybrominated diphenyl ethers (PBDE) . A products whose part number has trailing characters “E1” is RoHS compliant. 50 DS04–27265–3E MB39A132 ■ MARKING FORMAT (LEAD-FREE VERSION) Lead-free version INDEX ■ LABELING SAMPLE (LEAD-FREE VERSION) Lead-free mark JEITA logo MB123456P - 789 - GE1 (3N) 1MB123456P-789-GE1 1000 (3N)2 1561190005 107210 JEDEC logo G Pb QC PASS PCS 1,000 MB123456P - 789 - GE1 2006/03/01 ASSEMBLED IN JAPAN MB123456P - 789 - GE1 1/1 0605 - Z01A 1000 1561190005 The part number of a lead-free product has the trailing characters “E1”. DS04–27265–3E “ASSEMBLED IN CHINA” is printed on the label of a product assembled in China. 51 MB39A132 ■ MB39A132QN RECOMMENDED CONDITIONS OF MOISTURE SENSITIVITY LEVEL [Fujitsu Microelectronics Recommended Mounting Conditions] Item Condition Mounting Method IR (infrared reflow) , Manual soldering (partial heating method) Mounting times 2 times Storage period Before opening Please use it within two years after Manufacture. From opening to the 2nd reflow Less than 8 days When the storage period after opening was exceeded Please process within 8 days after baking (125 °C, 24H) Storage conditions 5 °C to 30 °C, 70%RH or less (the lowest possible humidity) [Mounting Conditions] (1) IR (infrared reflow) 260°C 255°C Main heating 170 °C to 190 °C (b) RT (a) “H” level : 260 °C Max (a) Temperature increase gradient (b) Preliminary heating (c) Temperature increase gradient (d) Peak temperature (d’) Main heating (e) Cooling (c) (d) (e) (d') : Average 1 °C/s to 4 °C/s : Temperature 170 °C to 190 °C, 60 s to 180 s : Average 1 °C/s to 4 °C/s : Temperature 260 °C Max; 255 °C or more, 10 s or less : Temperature 230 °C or more, 40 s or less or Temperature 225 °C or more, 60 s or less or Temperature 220 °C or more, 80 s or less : Natural cooling or forced cooling (Note)Temperature : on the top of the package body (2) Manual soldering (partial heating method) Temperature at the tip of an soldering iron: 400 °C max Time: Five seconds or below per pin 52 DS04–27265–3E MB39A132 ■ PACKAGE DIMENSIONS 32-pin plastic QFN Lead pitch 0.50 mm Sealing method Plastic mold (LCC-32P-M17) 32-pin plastic QFN (LCC-32P-M17) 3.50±0.10 (.138±.004) 5.00±0.10 (.197±.004) 5.00±0.10 (.197±.004) 3.50±0.10 (.138±.004) INDEX AREA +0.05 0.25 –0.03 (.010 –+.002 .001 ) (3-R0.20) ((3-R.008)) 0.50(.020) 0.40±0.10 (.016±.004) 1PIN CORNER (C0.30(C.012)) (TYP) 0.08(.003) 0.00 (.000 C 2007-2008 FUJITSU MICROELECTRONICS LIMITED C32069S-c-2-3 DS04–27265–3E +0.05 –0.00 +.002 –.000 0.85(.033) MAX 0.20(.008) ) Dimensions in mm (inches). Note: The values in parentheses are reference values. 53 MB39A132 ■ CONTENTS - 54 page DESCRIPTION .................................................................................................................................................... 1 FEATURES .......................................................................................................................................................... 1 APPLICATIONS .................................................................................................................................................. 1 PIN ASSIGNMENT ............................................................................................................................................. 2 PIN DESCRIPTIONS .......................................................................................................................................... 3 BLOCK DIAGRAM .............................................................................................................................................. 5 ABSOLUTE MAXIMUM RATINGS ................................................................................................................... 6 RECOMMENDED OPERATING CONDITIONS ............................................................................................ 7 ELECTRICAL CHARACTERISTICS ................................................................................................................ 9 TYPICAL CHARACTERISTICS ........................................................................................................................ 14 FUNCTIONAL DESCRIPTION ......................................................................................................................... 16 SETTING THE CHARGE VOLTAGE ............................................................................................................... 22 SETTING THE CHARGE CURRENT .............................................................................................................. 23 SETTING DYNAMICALLY-CONTROLLED CHARGING ............................................................................. 25 SETTING THE SOFT-START TIME ................................................................................................................ 26 TRANSIT RESPONSE AT STEP LOAD CHANGE ....................................................................................... 27 CONNECTION WITHOUT USING THE CURRENT AMP1,CURRENT AMP2 AND THE ERROR AMP1, ERROR AMP2 ............................................................................................................... 28 I/O EQUIVALENT CIRCUIT .............................................................................................................................. 29 TYPICAL APPLICATION CIRCUIT .................................................................................................................. 31 APPLICATION NOTE ......................................................................................................................................... 35 REFERENCE DATA ........................................................................................................................................... 47 USAGE PRECAUTION ...................................................................................................................................... 50 ORDERING INFORMATION ............................................................................................................................. 50 EV BOARD ORDERING INFORMATION ....................................................................................................... 50 RoHS COMPLIANCE INFORMATION OF LEAD (Pb) FREE VERSION .................................................. 50 MARKING FORMAT (LEAD-FREE VERSION) .............................................................................................. 51 LABELING SAMPLE (LEAD-FREE VERSION) ............................................................................................. 51 MB39A132QN RECOMMENDED CONDITIONS OF MOISTURE SENSITIVITY LEVEL ...................... 52 PACKAGE DIMENSIONS .................................................................................................................................. 53 DS04–27265–3E MB39A132 MEMO DS04–27265–3E 55 MB39A132 FUJITSU MICROELECTRONICS LIMITED Shinjuku Dai-Ichi Seimei Bldg., 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0722, Japan Tel: +81-3-5322-3347 Fax: +81-3-5322-3387 http://jp.fujitsu.com/fml/en/ For further information please contact: North and South America FUJITSU MICROELECTRONICS AMERICA, INC. 1250 E. Arques Avenue, M/S 333 Sunnyvale, CA 94085-5401, U.S.A. Tel: +1-408-737-5600 Fax: +1-408-737-5999 http://www.fma.fujitsu.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LTD. 151 Lorong Chuan, #05-08 New Tech Park 556741 Singapore Tel : +65-6281-0770 Fax : +65-6281-0220 http://www.fmal.fujitsu.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Pittlerstrasse 47, 63225 Langen, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://emea.fujitsu.com/microelectronics/ FUJITSU MICROELECTRONICS SHANGHAI CO., LTD. Rm. 3102, Bund Center, No.222 Yan An Road (E), Shanghai 200002, China Tel : +86-21-6146-3688 Fax : +86-21-6335-1605 http://cn.fujitsu.com/fmc/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 206 Kosmo Tower Building, 1002 Daechi-Dong, Gangnam-Gu, Seoul 135-280, Republic of Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 http://kr.fujitsu.com/fmk/ FUJITSU MICROELECTRONICS PACIFIC ASIA LTD. 10/F., World Commerce Centre, 11 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel : +852-2377-0226 Fax : +852-2376-3269 http://cn.fujitsu.com/fmc/en/ Specifications are subject to change without notice. For further information please contact each office. All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU MICROELECTRONICS or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third-party's intellectual property right or other right by using such information. FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of overcurrent levels and other abnormal operating conditions. Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. Edited: Sales Promotion Department