STK30NHS3LL N-channel 30 V - 0.0028 Ω - 30 A - PolarPAK® STripFET™ Power MOSFET plus monolithic Schottky Preliminary Data Features VDSS Type RDS(on) RDS(on)*Qg PTOT STK30NHS3LL 30V <0.0035Ω 87.5nC*mΩ 5.2W ■ Ultra low top and bottom junction to case thermal resistance ■ Reduced switching losses ■ Reduced conduction losses ■ Fully encapsulated die ■ 100% Matte tin finish (in compliance with the 2002/95/EC european directive) ■ PolarPAK® is a trademark of VISHAY PolarPAK® Application ■ Figure 1. Internal schematic diagram Switching applications Description This product utilizes the latest advanced design rules of ST’s proprietary STripFET™ technology and a proprietary process for integrating a monolithic Schottky diode. The new Power MOSFET is optimized for the most important demanding synchronous switch function in DCDC converter for computer and telecom.” Table 1. Bottom View Top View Device summary Order code Marking Package Packaging STK30NHS3LL K30NKS PolarPAK® Tape & reel February 2008 Rev 1 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1/13 www.st.com 13 Contents STK30NHS3LL Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Test circuits 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2/13 .............................................. 6 STK30NHS3LL 1 Electrical ratings Electrical ratings Table 2. Absolute maximum ratings Symbol VDS Parameter Drain-source voltage (VGS = 0) Value Unit 30 V VGS (1) Gate-source voltage ± 16 V VGS(2) Gate-source voltage ± 18 V ID (4) Drain current (continuous) at TC = 25°C 30 A ID Drain current (continuous) at TC = 100°C 18.75 A Drain current (pulsed) 120 A Total dissipation at TC = 25°C 5.2 W 0.0416 W/°C Single pulse avalanche energy TBD J Operating junction temperature Storage temperature -55 to 150 °C IDM (3) PTOT (4) Derating factor EAS (5) TJ Tstg 1. Continuous mode 2. Guaranteed for test time < 15ms 3. Pulse width limited by package 4. When mounted on FR-4 board of 1inch2, 2 oz. Cu. and ≤10sec 5. Starting TJ = 25°C, ID = 15A, VDD = 25V Table 3. Thermal data Symbol Parameter Rthj-amb(1) Thermal resistance junction-amb Typ. Max. Unit 20 24 °C/W Rthj-c(2) Thermal resistance junction-case (top drain) 0.8 1 °C/W Rthj-c(3) Thermal resistance junction-case (source) 2.2 2.7 °C/W 1. When mounted on FR-4 board of 1inch2, 2 oz. Cu. and ≤10sec 2. Steady state 3. Measured at Source pin when the device is mounted on FR-4 board in steady state 3/13 Electrical characteristics 2 STK30NHS3LL Electrical characteristics (TCASE=25°C unless otherwise specified) Table 4. Symbol Parameter Test conditions Drain-source breakdown voltage ID = 250 µA, VGS= 0 IDSS Zero gate voltage drain current (VGS = 0) VDS = Max rating, IGSS Gate body leakage current (VDS = 0) VGS = ±16 V VGS(th) Gate threshold voltage VDS= VGS, ID = 250 µA RDS(on) Static drain-source on resistance VGS= 10 V, ID= 15 A V(BR)DSS Table 5. Symbol Ciss Coss Crss Qg Qgs Qgd Qgs1 Qgs2 RG 4/13 On/off Min. Typ. Max. 30 V VDS = Max rating,Tc=125°C 1 1 10 µA µA ±100 nA 2.5 V 0.0028 0.0035 0.0033 0.004 VGS= 4.5 V, ID= 1 5A Unit Ω Ω Dynamic Parameter Input capacitance Output capacitance Reverse transfer capacitance Test conditions VDS =25 V, f=1 MHz, VGS=0 Total gate charge Gate-source charge Gate-drain charge VDD=15 V, ID = 30 A Pre Vth gate-to-source charge Post Vth gate-to-source charge VDD=15 V, ID = 12 A VGS =4.5 V (see Figure 8) Gate input resistance f=1 MHz Gate DC Bias = 0 Test signal level = 20 mV open drain VGS =4.5 V (see Figure 3) Min. Typ. Max. Unit 3200 760 46 pF pF pF 25 TBD TBD nC nC nC TBD nC TBD nC TBD Ω STK30NHS3LL Electrical characteristics Table 6. Switching times Symbol Parameter td(on) tr td(off) tf Table 7. Symbol Turn-on delay time Rise time Turn-off delay time Fall time Test conditions VDD= 15 V, ID= 15 A, RG=4.7 Ω, VGS=4.5 V (see Figure 2) VDD=15 V, ID= 15 A, RG=4.7 Ω, VGS=4.5 V (see Figure 2) Parameter Test conditions ISDM (1) VSD (2) Forward on voltage ISD= 3 A, VGS=0 Reverse recovery time Reverse recovery charge Reverse recovery current ISD= 30 A, di/dt = 100 A/µs, VDD=20 V, TJ=150°C trr Qrr IRRM Typ. Max. Unit TBD TBD ns ns TBD TBD ns ns Source drain diode Source-drain current Source-drain current (pulsed) ISD Min. (see Figure 7) Min. Typ. TBD 30 TBD Max. Unit 30 120 A A 0.7 V ns nC A 1. Pulse width limited by package 2. Pulsed: pulse duration = 300µs, duty cycle 1.5% 5/13 Test circuits STK30NHS3LL 3 Test circuits Figure 2. Switching times test circuit for resistive load Figure 4. Test circuit for inductive load Figure 5. switching and diode recovery times Unclamped inductive load test circuit Figure 6. Unclamped inductive waveform Switching time waveform 6/13 Figure 3. Figure 7. Gate charge test circuit STK30NHS3LL Figure 8. Test circuits Gate charge waveform Id Vds Vgs Vgs(th) Qgs1 Qgs2 Qgd 7/13 Package mechanical data 4 STK30NHS3LL Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com 8/13 STK30NHS3LL Package mechanical data Table 8. PolarPAK® (option “L”) mechanical data mm inch Ref. A Min. Typ. Max. Min. Typ. Max. 0.75 0.80 0.85 0.030 0.031 0.033 A1 0.05 0.002 b1 0.48 0.58 0.68 0.019 0.023 0.027 b2 0.41 0.51 0.61 0.016 0.020 0.024 b3 2.19 2.29 2.39 0.086 0.090 0.094 b4 0.89 1.04 1.19 0.035 0.041 0.047 b5 0.23 0.33 0.43 0.009 0.013 0.017 c 0.20 0.25 0.30 0.008 0.010 0.012 D 6 6.15 6.30 0.236 0.242 0.248 D1 5.74 5.89 6.04 0.226 0.232 0.238 E 5.01 5.16 5.31 0.197 0.203 0.209 E1 4.75 4.90 5.05 0.187 0.193 0.199 H1 0.23 H2 0.45 H3 0.31 H4 0.45 K1 4.22 K2 1.08 K3 1.37 0.054 K4 0.24 0.009 M1 4.30 4.50 4.70 M2 3.43 3.58 3.73 M3 0.22 0.009 M4 0.05 0.002 P1 0.15 0.20 0.25 T1 3.48 3.64 T2 0.56 0.76 T3 1.20 0.047 T4 3.90 0.154 T5 < 0° 0.009 0.56 0.018 0.51 0.012 0.56 0.018 4.37 4.52 0.166 0.172 0.178 1.13 1.18 0.043 0.044 0.046 0.169 0.177 0.185 0.135 0.141 0.147 0.006 0.008 0.010 4.10 0.137 0.143 0.161 0.95 0.022 0.030 0.037 0.007 0.014 10° 12° 0.41 0.18 0.36 10° 12° 0° 0.022 0.016 0.020 0.022 9/13 Package mechanical data Figure 9. 10/13 PolarPAK® (option “L”) drawings STK30NHS3LL STK30NHS3LL Package mechanical data Figure 10. Recommended PAD layout 11/13 Revision history 5 STK30NHS3LL Revision history Document Table 9. 12/13 Document revision history Date Revision 19-Feb-2008 1 Changes Initial release STK30NHS3LL Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. 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