STL21N65M5 N-channel 650 V, 0.175 Ω, 17 A PowerFLAT™ (8x8) HV ultra low gate charge MDmesh™ V Power MOSFET Features Type VDSS @ TJmax RDS(on) max ID STL21N65M5 710 V < 0.190 Ω 17 A (1) 3 3 3 "OTTOMVIEW ' $ 1. The value is rated according to Rthj-case ■ 100% avalanche tested ■ Low input capacitance and gate charge ■ Low gate input resistance 0OWER&,!4X(6 Application Switching applications Description Figure 1. The device is a N-channel MDmesh™ V Power MOSFET based on an innovative proprietary vertical process technology, which is combined with STMicroelectronics’ well-known PowerMESH™ horizontal layout structure. The resulting product has extremely low onresistance, which is unmatched among siliconbased Power MOSFETs, making it especially suitable for applications which require superior power density and outstanding efficiency. Internal schematic diagram $ ' 3 !-V Table 1. Device summary Order code Marking Package Packaging STL21N65M5 21N65M5 PowerFLAT™ (8x8) HV Tape and reel May 2011 Doc ID 17438 Rev 4 1/14 www.st.com 14 Contents STL21N65M5 Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) ............................ 6 3 Test circuits 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2/14 .............................................. 9 Doc ID 17438 Rev 4 STL21N65M5 1 Electrical ratings Electrical ratings Table 2. Symbol Absolute maximum ratings Parameter Value Unit VDS Drain-source voltage (VGS = 0) 650 V VGS Gate-source voltage ± 25 V Drain current (continuous) at TC = 25 °C 17 A ID (1) ID (1) Drain current (continuous) at TC = 100 °C 11 A (1),(2) Drain current (pulsed) 68 A ID (3) Drain current (continuous) at TC = 25 °C 2.7 A ID (3) Drain current (continuous) at TC = 100 °C 1.7 A 10.8 A IDM IDM(2),(3) Drain current (pulsed) (3) Total dissipation at TC = 25 °C (steady state) 3 W PTOT(1) Total dissipation at TC = 25 °C (steady state) 125 W PTOT IAR Avalanche current, repetitive or notrepetitive (pulse width limited by Tj max) 5 A EAS Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) 400 mJ Peak diode recovery voltage slope 15 V/ns - 55 to 150 °C 150 °C Value Unit Thermal resistance junction-case max 1 °C/W Rthj-amb(1) Thermal resistance junction-amb max 45 °C/W dv/dt (4) Tstg Tj Storage temperature Max. operating junction temperature 1. The value is rated according to Rthj-case. 2. Pulse width limited by safe operating area. 3. When mounted on FR-4 board of inch², 2oz Cu. 4. ISD ≤ 17 A, di/dt ≤ 400 A/µs, VPeak < V(BR)DSS, VDD = 400 V. Table 3. Symbol Rthj-case Thermal data Parameter 1. When mounted on 1inch² FR-4 board, 2 oz Cu Doc ID 17438 Rev 4 3/14 Electrical characteristics 2 STL21N65M5 Electrical characteristics (TC = 25 °C unless otherwise specified) Table 4. Symbol V(BR)DSS On /off states Parameter Test conditions Drain-source breakdown voltage ID = 1 mA, VGS = 0 Min. Typ. Max. Unit 650 V IDSS VDS = Max rating Zero gate voltage drain current (VGS = 0) VDS = Max rating, TC=125 °C 1 100 µA µA IGSS Gate-body leakage current (VDS = 0) 100 nA 4 5 V 0.175 0.190 Ω Min. Typ. Max. Unit - 1950 46 3 - pF pF pF - 133 - pF - 44 - pF - 2.5 - Ω - 44 12 17 - nC nC nC VGS = ± 25 V VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA RDS(on) Static drain-source on resistance Table 5. Symbol Ciss Coss Crss 3 VGS = 10 V, ID = 8.5 A Dynamic Parameter Input capacitance Output capacitance Reverse transfer capacitance Co(tr)(1) Equivalent capacitance time related Co(er)(2) Equivalent capacitance energy related Test conditions VDS = 100 V, f = 1 MHz, VGS = 0 VDS = 0 to 520 V, VGS = 0 RG Intrinsic gate resistance f = 1 MHz open drain Qg Qgs Qgd Total gate charge Gate-source charge Gate-drain charge VDD = 520 V, ID = 8.5 A, VGS = 10 V (see Figure 16) 1. Coss eq. time related is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS 2. Coss eq. energy related is defined as a constant equivalent capacitance giving the same stored energy as Coss when VDS increases from 0 to 80% VDSS 4/14 Doc ID 17438 Rev 4 STL21N65M5 Electrical characteristics Table 6. Symbol td(off) tr tc tf Table 7. Switching times Parameter Test conditions Turn-off delay time Rise time Cross time Fall time VDD = 400 V, ID = 11 A, RG = 4.7 Ω, VGS = 10 V (see Figure 17), (see Figure 20) Parameter ISD ISDM (1) Source-drain current Source-drain current (pulsed) VSD (2) Forward on voltage IRRM trr Qrr IRRM Typ. - 37 10 24 12 Min. Typ. Max Unit - ns ns ns ns Source drain diode Symbol trr Qrr Min. Test conditions Max. Unit - 17 68 A A ISD = 17 A, VGS = 0 - 1.5 V Reverse recovery time Reverse recovery charge Reverse recovery current ISD = 17 A, di/dt = 100 A/µs VDD = 100 V (see Figure 17) - 294 4 28 ns µC A Reverse recovery time Reverse recovery charge Reverse recovery current ISD = 17 A, di/dt = 100 A/µs VDD = 100 V, Tj = 150 °C (see Figure 17) - 340 5 29 ns µC A 1. Pulse width limited by safe operating area 2. Pulsed: pulse duration = 300 µs, duty cycle 1.5% Doc ID 17438 Rev 4 5/14 Electrical characteristics STL21N65M5 2.1 Electrical characteristics (curves) Figure 2. Safe operating area Figure 3. Thermal impedance AM07068v2 ID (A) Zth PowerFLAT 8x8 HV K δ=0.5 is 0.2 S( o n) Op Lim era ite tion d by in t m his ax ar RD ea 10 10µs 0.1 -1 100µs 10 0.05 0.02 1 0.01 1ms Single pulse Tj=150°C Tc=25°C Single pulse -2 0.1 0.1 Figure 4. 10ms 10 1 100 10 -5 10 VDS(V) Output characteristics Figure 5. AM05493v1 ID (A) VGS=10V 35 -4 -2 -3 10 tp (s) 10 10 Transfer characteristics AM05494v1 ID (A) VDS=15V 35 30 30 7V 25 25 20 20 15 15 10 10 6V 5 5 5V 0 0 Figure 6. 5 10 20 15 25 30 0 0 VDS(V) Gate charge vs gate-source voltage Figure 7. AM05496v1 VGS (V) VDD=520V 12 2 ID=8.5A 400 0.16 300 0.14 200 0.12 100 0.10 10 VGS(V) AM05495v1 VGS= 10 V VGS 0.18 8 6 Static drain-source on resistance RDS(on) (Ω) 500 4 10 8 6 4 2 0 0 6/14 10 20 30 40 50 0 Qg(nC) 0.08 0 Doc ID 17438 Rev 4 2 4 6 8 10 12 14 16 ID(A) STL21N65M5 Figure 8. Electrical characteristics Output capacitance stored energy AM05498v1 Eoss (µJ) 9 8 Figure 9. Capacitance variations AM05497v1 C (pF) 10000 7 Ciss 6 1000 5 4 100 3 Coss 10 2 1 Crss 0 0 100 400 500 600 200 300 1 0.1 VDS(V) Figure 10. Normalized gate threshold voltage vs temperature AM05500v1 VGS(th) (norm) 1.10 1 10 100 VDS(V) Figure 11. Normalized on resistance vs temperature AM05501v1 RDS(on) (norm) 2.1 ID =250 µA ID= 8.5 A 1.9 VGS= 10 V 1.7 1.00 1.5 0.90 1.3 1.1 0.9 0.80 0.7 0.70 -50 -25 25 0 50 TJ(°C) 75 100 125 Figure 12. Source-drain diode forward characteristics 0 25 50 75 100 125 TJ(°C) Figure 13. Normalized BVDSS vs temperature AM05502v1 VSD (V) 0.5 -50 -25 1.0 BVDSS (norm) 1.07 0.9 1.05 TJ=-50°C AM05499v1 ID= 1 mA 1.03 0.8 TJ=25°C 1.01 0.7 0.99 TJ=150°C 0.6 0.97 0.5 0.95 0.4 0 10 20 30 40 50 ISD(A) 0.93 -50 -25 Doc ID 17438 Rev 4 0 25 50 75 100 TJ(°C) 7/14 Electrical characteristics STL21N65M5 Figure 14. Switching losses vs gate resistance (1) AM05541v1 E (μJ) 160 140 Eon ID=11A VDD=400V VGS=10V 120 Eoff 100 80 60 40 20 0 0 10 20 30 40 RG(Ω) 1. Eon including reverse recovery of a SiC diode 8/14 Doc ID 17438 Rev 4 STL21N65M5 3 Test circuits Test circuits Figure 15. Switching times test circuit for resistive load Figure 16. Gate charge test circuit VDD 12V 47kΩ 1kΩ 100nF 3.3 μF 2200 RL μF VGS IG=CONST VDD 100Ω Vi=20V=VGMAX VD RG 2200 μF D.U.T. D.U.T. VG 2.7kΩ PW 47kΩ 1kΩ PW AM01468v1 AM01469v1 Figure 17. Test circuit for inductive load Figure 18. Unclamped inductive load test switching and diode recovery times circuit A A D.U.T. FAST DIODE B B L A D G VD L=100μH S 3.3 μF B 25 Ω 1000 μF D VDD 2200 μF 3.3 μF VDD ID G RG S Vi D.U.T. Pw AM01470v1 Figure 19. Unclamped inductive waveform V(BR)DSS AM01471v1 Figure 20. Switching time waveform Concept waveform for Inductive Load Turn-off Id VD 90%Vds 90%Id Tdelay-off -off IDM Vgs 90%Vgs on ID Vgs(I(t)) )) VDD VDD 10%Id 10%Vds Vds Trise AM01472v1 Doc ID 17438 Rev 4 Tfall Tcross --over AM05540v2 9/14 Package mechanical data 4 STL21N65M5 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 10/14 Doc ID 17438 Rev 4 STL21N65M5 Package mechanical data Table 8. PowerFLAT™ 8x8 HV mechanical data mm Dim. A Min. Typ. Max. 0.80 0.90 1.00 0.02 0.05 1.00 1.05 A1 b 0.95 c 0.10 D 8.00 E 8.00 D2 7.05 7.20 7.30 E2 4.15 4.30 4.40 e 2.00 L 0.40 0.50 0.60 Figure 21. PowerFLAT™ 8x8 HV drawing mechanical data BOTTOM VIEW b L e E2 PIN#1 ID 0.40 D D2 E INDEX AREA SIDE VIEW A A1 TOP VIEW SEATING PLANE 0.08 C AM05542v1 Doc ID 17438 Rev 4 11/14 Package mechanical data STL21N65M5 Figure 22. PowerFLAT™ 8x8 HV recommended footprint 2.00 1.05 0.60 4.40 7.30 AM05543v1 12/14 Doc ID 17438 Rev 4 STL21N65M5 5 Revision history Revision history Table 9. Document revision history Date Revision Changes 28-Apr-2010 1 First release. 14-Jun-2010 2 RDS(on) typical value has been corrected. 14-Mar-2011 3 Figure 2: Safe operating area, Figure 3: Thermal impedance and Figure 7: Static drain-source on resistance have been updated. 18-May-2011 4 RDS(on) limits in Table 4 have been updated. Doc ID 17438 Rev 4 13/14 STL21N65M5 Please Read Carefully: Information in this document is provided solely in connection with ST products. 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