STL6NM60N N-channel 600 V - 0.85 Ω - 5.75 A - PowerFLAT™ (5x5) ultra low gate charge MDmesh™ II Power MOSFET Features Type VDSS @ TJMAX RDS(on) Max ID STL6NM60N 650 V < 0.92 Ω 5.75 A(1) 1. The value is rated according Rthj-case ■ 100% avalanche tested ■ Low input capacitance and gate charge ■ Low gate input resistance PowerFLAT (5x5) Application ■ Switching applications Description Figure 1. Internal schematic diagram This series of devices implements the second generation of MDmesh™ Technology. This revolutionary Power MOSFET associates a new vertical structure to the Company’s strip layout to yield one of the world’s lowest on-resistance and gate charge. It is therefore suitable for the most demanding high efficiency converters. Table 1. Device summary Order code Marking Package Packaging STL6NM60N L6NM60N PowerFLAT™ (5x5) Tape & reel November 2007 Rev 3 1/12 www.st.com 12 Contents STL6NM60N Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) ............................. 6 3 Test circuit 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2/12 ................................................ 8 STL6NM60N 1 Electrical ratings Electrical ratings Table 2. Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage (VGS = 0) 600 V VGS Gate-source voltage ± 25 V ID(1) Drain current (continuous) at TC = 25 °C (steady state) 5.75 A ID (1) Drain current (continuous) at TC=100 °C 3.62 A (1),(2) Drain current (pulsed) 23 A ID (3) Drain current (continuous) at TC = 25 °C 1 A ID (3) Drain current (continuous) at TC=100 °C 0.65 A 4 A IDM IDM(2), (3) Drain current (pulsed) (3) Total dissipation at TC = 25 °C (steady state) 2.1 W PTOT(1) Total dissipation at TC = 25 °C (steady state) 70 W 0.02 W/°C 5 V/ns -55 to 150 °C PTOT Derating factor dv/dt (4) TJ (3) Peak diode recovery voltage slope Operating junction temperature storage temperature Tstg 1. The value is rated according Rthj-case 2. Pulse width limited by safe operating area. 3. When mounted on FR-4 board of 1inch², 2oz Cu 4. ISD ≤ 4.6A, dv/dt ≤ 400A/µs, VDD = 80%V(BR)DSS Table 3. Thermal resistance Symbol Parameter Rthj-case Rthj-pcb (1) Typ Max Unit Thermal resistance junction-case -- 1.8 °C/W Thermal resistance junction-pcb 31.2 58.5 °C/W 1. When mounted on FR-4 board of 1inch², 2oz Cu, t < 10 sec Table 4. Avalanche characteristics Symbol Parameter IAS Avalanche current, repetitive or not-repetitive EAS Single pulse avalanche energy (2) (1) Typ Unit 2 A 65 mJ 1. Pulse width limited by Tjmax 2. Starting Tj = 25 °C, ID= IAS, VDD = 50 V 3/12 Electrical characteristics 2 STL6NM60N Electrical characteristics (TCASE=25°C unless otherwise specified) Table 5. Symbol On/off states Parameter V(BR)DSS Drain-source breakdown voltage dv/dt (1) Drain-source voltage slope 1. Test conditions ID = 1 mA, VGS= 0 Min. Typ. Max. 600 VDD= 480 V, VGS = 10 V, V 40 ID = 4.6 A Unit VDS = Max rating, V/ns VDS = Max rating @125 °C 1 100 µA µA Gate body leakage current (VDS = 0) VGS = ±20 V ±100 nA VGS(th) Gate threshold voltage VDS= VGS, ID = 250 µA 3 4 V RDS(on) Static drain-source on resistance VGS= 10 V, ID= 2.3 A 0.85 0.92 Ω Typ. Max. Unit IDSS Zero gate voltage drain current (VGS = 0) IGSS 2 Characteristics value at turn off on inductive load Table 6. Dynamic Symbol Parameter Test conditions gfs (1) Forward transconductance VDS =15 V, ID = 2.3 A Input capacitance Output capacitance Reverse transfer capacitance (2) Min. 4 S VDS =50V, f=1 MHz, VGS=0 420 30 4 pF pF pF Output equivalent capacitance VGS =0, VDS =0 to 480 V 70 pF Rg Gate input resistance f=1 MHz Gate DC Bias=0 test signal level = 20 mV open drain 6 Ω Qg Total gate charge Gate-source charge Gate-drain charge VGS =10 V 13 2 7 nC nC nC Ciss Coss Crss Coss eq. Qgs Qgd VDD= 480 V, ID = 4.6 A (see Figure 15) 1. Pulsed: pulse duration= 300 µs, duty cycle 1.5% 2. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS 4/12 STL6NM60N Electrical characteristics Table 7. Symbol td(on) tr td(off) tf Table 8. Symbol ISD Switching times Parameter Turn-on delay time Rise time Turn-off delay time Fall time Test conditions Min. Typ. 10 8 40 9 VDD= 300 V, ID = 2.3 A, RG= 4.7 Ω, VGS = 10 V (see Figure 14) trr Qrr IRRM trr Qrr IRRM Unit ns ns ns ns Source drain diode Parameter Test conditions Min Typ. Source-drain current ISDM (1),(2) Source-drain current (pulsed) VSD(3) Max. Forward on voltage Reverse recovery time Reverse recovery charge Reverse recovery current Reverse recovery time Reverse recovery charge Reverse recovery current ISD= 4.6 A, VGS=0 ISD= 4.6 A, di/dt = 100 A/µs, VDD=20 V (see Figure 16) ISD= 4.6 A, di/dt = 100 A/µs, VDD=20 V, Tj= 150 °C (see Figure 16) Max Unit 1 A 4 A 1.3 V 300 2 12 ns nC A 470 3 12 ns nC A 1. Pulse width limited by safe operating area 2. When mounted on FR-4 board of 1inch², 2oz Cu 3. Pulsed: pulse duration=300µs, duty cycle 1.5% 5/12 Electrical characteristics STL6NM60N 2.1 Electrical characteristics (curves) Figure 2. Safe operating area Figure 3. Thermal impedance Figure 4. Output characteristics Figure 5. Transfer characteristics Figure 6. Transconductance Figure 7. Static drain-source on resistance 6/12 STL6NM60N Figure 8. Electrical characteristics Gate charge vs gate-source voltage Figure 9. Capacitance variations Figure 10. Normalized gate threshold voltage vs temperature Figure 11. Normalized on resistance vs temperature Figure 12. Source-drain diode forward characteristics Figure 13. Normalized BVDSS vs temperature 7/12 Test circuit 3 STL6NM60N Test circuit Figure 14. Switching times test circuit for resistive load Figure 15. Gate charge test circuit Figure 16. Test circuit for inductive load Figure 17. Unclamped inductive load test switching and diode recovery times circuit Figure 18. Unclamped inductive waveform 8/12 Figure 19. Switching time waveform STL6NM60N 4 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com 9/12 Package mechanical data STL6NM60N PowerFLAT™(5x5) MECHANICAL DATA mm. inch DIM. MIN. TYP MAX. MIN. TYP. MAX. 0.80 0.90 1.00 0.031 0.035 0.039 A1 0.02 0.05 0.0007 0.002 A3 0.24 A b 0.43 0.51 0.58 0.016 0.020 0.022 c 0.64 0.71 0.79 0.025 0.027 0.031 D 5.00 E E2 e 10/12 0.009 0.19 5.00 2.49 2.57 1.27 0.19 2.64 0.01 0.10 0.05 0.103 STL6NM60N 5 Revision history Revision history Table 9. Document revision history Date Revision Changes 04-May-2007 1 First release 23-May-2007 2 Update test conditions on Table 7 27-Nov-2007 3 Mechanical data has been updated 11/12 STL6NM60N Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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