SD1731 (TH562) RF POWER BIPOLAR TRANSISTORS HF SSB APPLICATIONS FEATURES SUMMARY ■ OPTIMIZED FOR SSB Figure 1. Package ■ 30 MHz ■ 50 VOLTS ■ EFFICIENCY 40% ■ COMMON EMITTER ■ GOLD METALLIZATION ■ POUT = 220 W PEP WITH 13 dB GAIN DESCRIPTION The SD1731 is a 50 V epitaxial silicon NPN planar transistor designed primarily for SSB communications. This device utilizes emitter ballasting for improved ruggedness and reliability. ) s ( ct c u d .500 4L FL (M174) epoxy sealed e t le o r P Figure 2. Pin Connection o s b O - u d o r P e 1. Collector 2. Emitter t e l o s b O ) s t( 3. Base 4. Emitter Table 1. Order Codes Order Codes Marking Package Packaging SD1731 (TH562) SD1731 M174 PLASTIC TRAYS REV. 2 June 2004 1/9 SD1731 (TH562) Table 2. Absolute Maximum Ratings (Tcase = 25°C) Symbol Parameter Value Unit VCBO Collector-Base Voltage 110 V VCEO Collector-Emitter Voltage 55 V VEBO Emitter-Base Voltage 4.0 V Device Current 20 A Power Dissipation (Theatsink ≤ 25°C) 233 W TJ Junction Temperature +200 °C TSTG Storage Temperature – 65 to +150 °C Value Unit IC PDISS Table 3. Thermal Data Symbol Parameter RTH(j-c) Junction-Case Thermal Resistance 0.55 RTH(c-s) Case-Heatsink Thermal Resistance 0.2 ELECTRICAL SPECIFICATIONS e t le Table 4. Static (Tcase = 25°C) Symbol Test Conditions BVCBO IC = 200 mA; IE = 0 mA BVCEO IC = 200 mA; IB = 0 mA BVEBO IE = 20 mA; IC = 0 mA ICEO VCE = 30 V; IE = 0 mA ICES VCE = 55 V; IE = 0 mA hFE VCE = 6 V; IC = 10 A o r P e (s) o s b O - ct du ) s t( °C/W c u d °C/W o r P Value Unit Min. Typ. Max. 110 — — V 55 — — V 4.0 — — V — — 5 mA — — 10 mA 15 — 80 — Table 5. Dynamic (Theatsink = 25°C) t e l o Symbol s b O Unit Min. Typ. Max. POUT f = 30 MHz; VCE = 50 V; ICQ = 150 mA 220 — — W GP(1) POUT = 220 W PEP; VCE = 50 V; ICQ = 150 mA 13 — — dB IMD(1) POUT = 220 W PEP; VCE = 50 V; ICQ = 150 mA — — –30 dBc ηc(1) POUT = 220 W PEP; VCE = 50 V; ICQ = 150 mA 40 — — % COB f = 1 MHz; VCB = 50 V — 330 — pF Note: 1. f1 = 30.00 MHz, f2 = 30.001 MHz 2/9 Value Test Conditions SD1731 (TH562) TYPICAL PERFORMANCE Figure 3. Power Output PEP vs Power Input Figure 4. Collector Efficiency vs Power Output PEP c u d e t le ) s ( ct ) s t( o r P o s b O - Figure 5. Intermodulation Distortion vs Power Output PEP u d o r P e t e l o s b O 3/9 SD1731 (TH562) Figure 6. Power Gain vs Power Output PEP c u d e t le Figure 7. Collector Base Capacitance vs Collector Emitter Voltage ) s ( ct u d o r P e t e l o s b O 4/9 o s b O - o r P ) s t( SD1731 (TH562) TEST CIRCUIT Figure 8. Test Circuit c u d e t le Table 6. Test Circuit o r P o s b O - C1 Arco 426 + 220pF + 330pF Chips C2 2 x 10nF Chips C3 Arco 4615 + 2.2nF + 2 x 1nF LCC + 4.7nF + 560pf Chps C4 Arco 4213 + 330pF Chip ) s ( ct u d o C5 10nF Chip r P e C6 C7, C8, C9, C10, C11 t e l o L1 L2, L3 bs L4 O ) s t( 3 x 10nF Chips 1nF + 10nF + 100nF + 4.7µF, 63V + 100µF, 63V 3 Turns of 1.2mm Unenameled Wire Diameter, 7.1mm, Length 13mm 8 Turns of 0.55mm Enameled Wire on Ferrite Core Phillips 4C6 97170 (9 x 6 x 3) 10 Turns of 1.2mm Enameled Wire, Diameter 8.1mm, Length 20mm L5 7 Turns of 1.2mm Enameled Wire on Ferrite Core Phillips 4C6 97180 T1 6:3.5 Impedance Transformer on toriod Phillips 4C6 97180 T2 Twisted Pair 4:1 Transformer, 4 Turns Made with 1.0mm Enameled on toriod Phillips 4C6 97180 T3 Feedback Transformer Primary: 2 Turns of 1mm Enameled Wire Secondary: 8 Turns of 1mm Enameled Wire T4 Twisted Pair 4:1 Transformer, 4 Turns of bifilar Twisted 1.2mm Wires on Ferrite Core Phillips 4C6 97200 5/9 SD1731 (TH562) Figure 9. Mounting Circuit c u d e t le BIAS CIRCUIT Figure 10. Bias Circuit ) s ( ct u d o r P e t e l o s b O 6/9 o s b O - o r P ) s t( SD1731 (TH562) PACKAGE MECHANICAL Table 7. M174 Mechanical Data millimeters Symbol A Min Typ 5.59 B inches Max Min 5.84 0.220 Typ Max 0.230 3.18 0.125 C 6.22 6.48 0.245 0.255 D 18.28 18.54 0.720 0.730 E 3.18 0.125 F 24.64 24.89 0.970 0.980 G 12.57 12.83 0.495 0.505 H 0.08 0.18 0.003 0.007 I 2.29 2.79 0.090 0.110 J 4.06 4.45 0.160 K 7.11 L 26.67 uc Figure 11. M174 Package Dimensions ) s ( ct ) s t( 0.175 d o r 0.280 1.050 P e let o s b O - u d o r P e t e l o s b O Note: Drawing is not to scale. 7/9 SD1731 (TH562) REVISION HISTORY Table 8. Revision History Date Revision Description of Changes July-1995 1 First Issue 8-June-2004 2 Stylesheet update. No content change. c u d e t le ) s ( ct u d o r P e t e l o s b O 8/9 o s b O - o r P ) s t( SD1731 (TH562) c u d e t le ) s ( ct ) s t( o r P o s b O - u d o r P e t e l o Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. s b O The ST logo is a registered trademark of STMicroelectronics. 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