TESDF5V0AU ESD Protection Array Small Signal Diode SOT-23 A Features F B E Meet IEC61000-4-2 (ESD) ±15kV (air), ±8kV (contact) Meet IEC61000-4-4 (EFT) rating. 40A (5/50ήs) C Meet IEC61000-4-5 (Lightning) rating. 12A (8/20μs) D Protects two directional I/O lines Working Voltage : 5V Pb free version, RoHS compliant, and Halogen free Unit (mm) Dimensions Mechanical Data Unit (inch) Min Max Min Max Case :SOT-23 standard package, molded plastic A 2.80 3.00 0.110 0.118 Terminal: Matte tin plated, lead free., solderable per MIL-STD-202, Method 202 guaranteed B 1.20 1.40 0.047 0.055 C 0.30 0.50 0.012 0.020 High temperature soldering guaranteed: 260°C/10s D 1.80 2.00 0.071 0.079 Weight : 0.008gram (approximately) E 2.25 2.55 0.089 0.100 Marking Code : M05 F 0.90 1.20 0.035 0.043 Applications Pin Configutation Cell Phone Handsets and Accessories Microprocessor based equipment Industrial Controls Notebooks, Desktops, and Servers Set-Top Box Ordering Information Part No. Packing Packing Code Marking 3K / 7" Reel RFG M05 Package TESDF5V0AU SOT-23 Maximum Ratings and Electrical Characteristics Rating at 25°C ambient temperature unless otherwise specified. Maximum Ratings Type Number Symbol Value Units Peak Pulse Power (tp=8/20μs waveform) PPP 300 W Peak Pulse Current (tp = 8/20μs) IPP 5 A ESD per IEC 61000-4-2 (Air) ESD per IEC 61000-4-2 (Contact) VESD ±15 ± 8 KV TJ, TSTG Junction and Storage Temperature Range . -55 to + 150 °C . Electrical Characteristics Type Number Reverse Stand-Off Voltage Reverse Breakdown Voltag Reverse Leakage Current Clamping Voltage Junction Capacitance I R= V R= IPP= IPP= 1mA 5V 1A 5A VR=0V, f=1.0MHz Max 5 Symbol VRWM Min - V(BR) 6 - V IR - 10 9.8 15 uA Vc CJ 350(Typ.) Units V V pF Version : A11 TESDF5V0AU ESD Protection Array Small Signal Diode Rating and Characteristic Curves FIG 1 Non-Repetitive Peak Pulse Power vs. Pulse Time FIG 2 Pulse Waveform 10 110 Waveform Parameters: tr = 8μs, td = 20μs 90 Percent of IPP Peak Pulse Power Ppp (KW) 100 80 1 70 60 50 e 40 0.1 30 -1 td=Ipp/2 20 10 0 0.01 0.1 1 10 100 0 1000 5 10 FIG 3 Admissible Power Dissipation Curve 20 25 30 FIG 4 Typical Junction Capacitance 400 120 Normalized Capacitance 100 Power Rating (%) 15 Time (us) Pulse Duration (us) 80 60 40 20 320 240 160 80 f = 1.0MHz 0 0 0 20 40 60 80 100 120 140 160 180 0 1 2 3 4 5 Reverse Voltage (V) o Ambient Tempeatature ( C) FIG 5 Clamping Voltage vs. Peak Pulse Current Clamping Voltage (V) 15 10 5 Waveform Parameters: tr = 8μs, td = 20μs 0 0 1 2 3 4 5 Peak Pulse Current (A) Version : A11 TESDF5V0AU ESD Protection Array Small Signal Diode Applications Information Designed for the Uni-directional protection of 2 lines from the damage caused by Electro Static Discharge (ESD) and surge pulses Be used on lines where the signal polarities are above and below ground Provides a surge capability of 300 Watts peak Ppp per line for an 8/20 ms waveform. Circuit Board Layout Recommendations Place the ESD protection array as close to the input terminal or connector as possible Keep parallel signal paths to a minimum Minimize all printed-circuit board conductive loops including power and group loops Avoid using shared transient return paths to a common ground point Ground planes should be used. For multilayer printed-circuit boards, use ground vias Below picture is the typical application for bi-directional protection of two lines To Protected Device IO#1 IO#2 TESDF5V0A Version : A11 TESDF5V0AU ESD Protection Array Small Signal Diode Tape & Reel specification TSC label Item Carrier depth Sprocket hole Reel outside diameter Reel inner diameter Feed hole width Sprocke hole position Sprocke hole pitch Embossment center Overall tape thickness Tape width Reel width Top Cover Tape Carieer Tape Any Additional Label (If Required) P0 D P1 T 10 Pitches Cumulative Tolerance on Tape ±2.0mm ( ±0.008") Symbol K D A D1 D2 E P0 P1 T W W1 Dimension (mm) 1.22 Max. 1.50 +0.10 180 ± 1 50 Min. 13.0 ± 0.5 1.75 ±0.10 4.00 ±0.10 2.00 ±0.10 0.6 Max. 8.30 Max. 14.4 Max. E F K0 W BB0 0 B1 D' Top Cover Tape See Note1 For Components 2.0mm X 1.2mm and Larger K A0 Center Lines of Cavity Embossment For Machine Reference Only Including Draft and RADLL Concentric Around B0 W1 Direction of Feed A D2 D1 Suggested PAD Layout B A C Dimensions A B C D Unit (inch) 0.079 0.037 0.035 0.031 Unit (mm) 2.00 0.95 0.90 0.80 D Note 1: A0, B0, and K0 are determined by component size. The clearance between the components and the cavity must be within 0.05 mm min. to 0.5 mm max. The component cannot rote more than 10 o within the determined cavity. Note 2: If B 1 exceeds 4.2 mm(0.165'') for 8 mm embossed tape, the tape may not feed through all tape feeders. Note 3: The suggested land pattern dimensions have been provided for reference only, as actual pad layouts may vary despending on application. Version : A11