TESDV5V0A Steering Diode Structure ESD Protection Array Small Signal Diode SOT-363 Features Meet IEC61000-4-2 (ESD) ±15kV (air), ±8kV (contact) Meet IEC61000-4-4 (EFT) rating. 40A (5/50ήs) Protects four high speed I/O lines Working Voltage : 5V Pb free version, RoHS compliant, and Halogen free Unit (mm) Dimensions Mechanical Data Unit (inch) Min Max Min Max A 1.80 2.00 0.071 0.079 1.35 0.045 0.053 Case : SOT-363 standard package, molded plastic B 1.15 Terminal: Matte tin plated, lead free, solderable per MIL-STD-202, Method 202 guaranteed C D 0.15 0.30 1.30 BSC 0.006 0.012 0.051 BSC High temperature soldering guaranteed: 260°C/10s E 2.10 BSC 0.083 BSC Molding Compound Flammability Rating : UL 94V-O F - Weight :8 mg (approximately) G 1.10 0.42 - 0.043 0.017 Marking Code : B54 Applications Pin Configutation USB Power & Data Line Protection Notebooks, Desktops, Servers and Video Graphics Cards Monitors and Flat Panel Displays 6 IO#4 5 VDD 4 IO#3 1 IO#1 2 GND 3 IO#2 Portable Instrumentation Set Top Box Ordering Information Part No. TESDV5V0A Package Packing Packing Code Marking SOT-363 3K / 7" Reel RFG B54 Maximum Ratings and Electrical Characteristics Rating at 25°C ambient temperature unless otherwise specified. Maximum Ratings Symbol Value Units Peak Pulse Power (tp=8/20μs waveform) PPP 150 W Peak Pulse Current (tp = 8/20μs) IPP 3 A VESD ±16 ±8 KV Type Number ESD per IEC 61000-4-2 (Air) ESD per IEC 61000-4-2 (Contact) TJ, TSTG Junction and Storage Temperature Range . -55 to + 150 °C . Electrical Characteristics Type Number Reverse Stand-Off Voltage Reverse Breakdown Voltag Reverse Leakage Current Clamping Voltage Junction Capacitance IR= VR= IPP= IPP= 1mA 5V 1A 3A VR=0V, f=1.0MHz Symbol VRWM Min - V(BR) 6 - V IR - 1 15 25 uA Vc CJ Max 5 2 (Typ.) Units V V pF Version : A11 TESDV5V0A Steering Diode Structure ESD Protection Array Small Signal Diode Rating and Characteristic Curves FIG 1 Non-Repetitive Peak Pulse Power vs. Pulse Time FIG 2 Pulse Waveform 10 110 Waveform Parameters: tr = 8μs, td = 20μs 90 Percent of IPP Peak Pulse Power Ppp (KW) 100 80 1 70 60 50 e-1 40 0.1 30 td=Ipp/2 20 10 0 0.01 0.1 1 10 100 0 1000 5 10 FIG 3 Admissible Power Dissipation Curve 20 25 30 FIG 4 Typical Junction Capacitance 200 2 160 1.6 Normalized Capacitance Power Rating (%) 15 Time (us) Pulse Duration (us) 120 80 40 1.2 0.8 0.4 f = 1.0MHz 0 0 0 20 40 60 80 100 120 140 160 180 0 1 2 3 4 5 Reverse Voltage (V) o Ambient Tempeatature ( C) FIG 5 Clamping Voltage vs. Peak Pulse Current Clamping Voltage (V) 30 25 20 15 10 5 Waveform Parameters: tr = 8μs, td = 20μs 0 0 1 2 3 4 5 Peak Pulse Current (A) Version : A11 TESDV5V0A Steering Diode Structure ESD Protection Array Small Signal Diode Applications Information Designed to protect protect high speed data interfaces Designed to protect four data lines from transient over-voltages by clamping them to a fixed reference Designed to protect protect sensitive components which are connected to data and transmission lines from overvoltage caused by electrostatic discharge (ESD), electrical fast transients (EFT), and lightning. TESDS5V0ALC incorporates eight surge rated, low capacitance steering diodes and a TVS diode in a single package During transient conditions, the steering diodes direct the transient to either the positive side of the power supply line or to ground The internal TVS diode prevents over-voltage on the power line, protecting any downstream components Circuit Board Layout Recommendations To protect data lines and the power line, connect pin 5 directly to the VDD. In this configuration the data lines are referenced to the supply voltage. The internal TVS diode prevents over-voltage on the supply rail. The TESDS5V0ALC can be isolated from the power supply by adding a series resistor between pin 5 and VDD. A value of 100kΩ is recommended. The internal TVS and steering diodes remain biased, providing the advantage of lower capacitance. ²In applications where no positive supply reference is available, or complete supply isolation is desired, the internal TVS may be used as the reference. In this case, pin 5 is not connected. The steering diodes will begin to conduct when the voltage I/O#1 I/O#2 To Protected Device To Protected Device I/O#1 I/O#2 VDD VDD I/O#3 I/O#4 To Protected Device 100K Ω I/O#3 I/O#4 Data Line and Power Supply Protection Using Vcc as reference I/O#1 I/O#2 I/O#3 I/O#4 To Protected Device Data Line Protection with Bias and Power Supply Isolation To Protected Device To Protected Device Data Line Protection Using Internal TVS Diode as Reference Version : A11 TESDV5V0A Steering Diode Structure ESD Protection Array Small Signal Diode Tape & Reel specification TSC label Item Top Cover Tape Symbol Carrier depth K 1.22 Max. Sprocket hole D 1.50 +0.10 A 180 ± 1 Reel outside diameter Carieer Tape Any Additional Label (If Required) 10 Pitches Cumulative Tolerance on Tape ±2.0mm ( ±0.008") P0 D P1 T Dimension ( mm ) Reel inner diameter D1 50 Min. Feed hole width D2 13.0 ± 0.5 Sprocke hole position E 1.75 ±0.10 Sprocke hole pitch P0 4.00 ±0.10 Embossment center P1 2.00 ±0.10 Overall tape thickness T 0.6 Max. Tape width W 8.30 Max. Reel width W1 14.4 Max. E F K0 W BB0 0 B1 D' Top Cover Tape See Note1 For Components 2.0mm X 1.2mm and Larger K A0 Center Lines of Cavity Embossment For Machine Reference Only Including Draft and RADLL Concentric Around B 0 W1 Direction of Feed A D2 D1 Suggested PAD Layout C A B F E D Dimensions Unit (inch) A 0.073 Unit (mm) 1.85 B 0.039 1.00 C 0.026 0.65 D 0.016 0.40 E 0.033 0.85 F 0.106 2.70 Note 1: A0, B0, and K0 are determined by component size. The clearance between the components and the cavity must be o within 0.05 mm min. to 0.5 mm max. The component cannot rote more than 10 within the determined cavity. Note 2: If B1 exceeds 4.2 mm(0.165'') for 8 mm embossed tape, the tape may not feed through all tape feeders. Note 3: The suggested land pattern dimensions have been provided for reference only, as actual pad layouts may vary despending on application. Version : A11