SSN1N45B N-Channel B-FET 450 V, 0.5 A, 4.25 Ω Description Features These N-Channel enhancement mode power field effect transistors are produced using Fairchild’s proprietary, planar, DMOS technology. This advanced technology has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and commutation mode. These devices are well suited for electronic ballasts based on half bridge configuration. • • • • • • 0.5 A, 450 V, RDS(on) = 4.25 Ω @ VGS = 10 V Low Gate Charge (typical 6.5 nC) Low Crss (typical 6.5 pF) 100% Avalanche Tested Improved dv/dt Capability Gate-Source Voltage ± 50V Guaranteed D G G D TO-92 S S Absolute Maximum Ratings T Symbol VDSS ID o C = 25 C unless otherwise noted. Parameter Drain-Source Voltage - Continuous (TC = 25°C) Drain Current - Continuous (TC = 100°C) SSN1N45BTA 450 Unit V 0.5 A 0.32 A 4.0 A IDM Drain Current VGSS Gate-Source Voltage ± 50 V EAS Single Pulsed Avalanche Energy (Note 2) 108 mJ IAR Avalanche Current (Note 1) 0.5 A EAR Repetitive Avalanche Energy Peak Diode Recovery dv/dt Power Dissipation (TA = 25°C) (Note 1) 0.25 5.5 0.9 mJ V/ns W 2.5 0.02 -55 to +150 W W/°C °C 300 °C dv/dt PD - Pulsed (Note 1) (Note 3) Power Dissipation (TL = 25°C) TJ, Tstg TL - Derate above 25°C Operating and Storage Temperature Range Maximum Lead Temperature for Soldering, 1/8" from Case for 5 Seconds Thermal Characteristics Symbol RθJL Thermal Resistance, Junction-to-Lead, Max. Parameter (Note 5a) SSN1N45BTA 50 Unit °C/W RθJA Thermal Resistance, Junction-to-Ambient, Max. (Note 5b) 140 °C/W ©2002 Fairchild Semiconductor Corporation SSN1N45B Rev. C0 1 www.fairchildsemi.com SSN1N45B — N-Channel B-FET November 2013 Part Number SSN1N45BTA Electrical Characteristics T Symbol Package TO-92 Top Mark 1N45B Packing Method AMMO Reel Size N/A Tape Width N/A Quantity 2000 units o C = 25 C unless otherwise noted. Parameter Test Conditions Min Typ Max Unit 450 -- -- V -- V/°C Off Characteristics BVDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA ∆BVDSS / ∆TJ Breakdown Voltage Temperature Coefficient ID = 250 µA, Referenced to 25°C -- 0.5 VDS = 450 V, VGS = 0 V -- -- 10 µA VDS = 360 V, TC = 125°C -- -- 100 µA IDSS Zero Gate Voltage Drain Current IGSSF Gate-Body Leakage Current, Forward VGS = 50 V, VDS = 0 V -- -- 100 nA IGSSR Gate-Body Leakage Current, Reverse VGS = -50 V, VDS = 0 V -- -- -100 nA On Characteristics VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250 µA 2.3 3.0 3.7 V VDS = VGS, ID = 250 mA 3.5 4.2 4.9 V RDS(on) Static Drain-Source On-Resistance VGS = 10 V, ID = 0.25 A -- 3.4 4.25 Ω gFS Forward Transconductance VDS = 50 V, ID = 0.25 A -- 0.7 -- S VDS = 25 V, VGS = 0 V, f = 1.0 MHz -- 185 240 pF -- 29 40 pF -- 6.5 8.5 pF -- 7.5 25 ns -- 21 50 ns -- 23 55 ns Dynamic Characteristics Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance Switching Characteristics td(on) Turn-On Delay Time tr Turn-On Rise Time td(off) Turn-Off Delay Time tf Turn-Off Fall Time Qg Total Gate Charge Qgs Gate-Source Charge Qgd Gate-Drain Charge VDD = 225 V, ID = 0.5 A, RG = 25 Ω (Note 4) VDS = 360 V, ID = 0.5 A, VGS = 10 V (Note 4) -- 36 80 ns -- 6.5 8.5 nC -- 0.9 -- nC -- 3.2 -- nC A Drain-Source Diode Characteristics and Maximum Ratings IS Maximum Continuous Drain-Source Diode Forward Current -- -- 0.5 ISM -- -- 4.0 A VSD Maximum Pulsed Drain-Source Diode Forward Current VGS = 0 V, IS = 0.5 A Drain-Source Diode Forward Voltage -- -- 1.4 V trr Reverse Recovery Time Qrr Reverse Recovery Charge VGS = 0 V, IS = 0.5 A, dIF / dt = 100 A/µs -- 102 -- ns -- 0.26 -- µC 1. Repetitive Rating : Pulse width limited by maximum junction temperature. 2. L = 75 mH, IAS = 1.6 A, VDD = 50 V, RG = 25 Ω, starting TJ = 25oC. 3. ISD ≤ 0.5 A, di/dt ≤ 300 A/μs, VDD ≤ BVDSS, starting TJ = 25oC. 4. Essentially independent of operating temperature. 5. a) Reference point of the RθJL is the drain lead. b) When mounted on 3”x4.5” FR-4 PCB without any pad copper in a still air environment. (RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance. RθCA is determined by the user’s board design) ©2002 Fairchild Semiconductor Corporation SSN1N45B Rev. C0 2 www.fairchildsemi.com SSN1N45B — N-Channel B-FET Package Marking and Ordering Information SSN1N45B — N-Channel B-FET ! VGS 15.0 V 10.0 V 8.0 V 6.0 V 5.5 V 5.0 V Bottom : 4.5 V 0 ID, Drain Current [A] 10 ID , Drain Current [A] Top : -1 10 0 150℃ 10 25℃ -55℃ ※ Notes : 1. 250μ s Pulse Test 2. TC = 25℃ ※ Notes : 1. VDS = 50V 2. 250μ s Pulse Test -1 -1 0 10 10 1 10 10 2 6 4 8 10 VGS , Gate-Source Voltage [V] VDS, Drain-Source Voltage [V] Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics 12 IDR, Reverse Drain Current [A] RDS(ON) [Ω ], Drain-Source On-Resistance 10 VGS = 10V 8 VGS = 20V 6 4 2 0 10 150℃ 25℃ ※ Notes : 1. VGS = 0V 2. 250μ s Pulse Test ※ Note : TJ = 25℃ -1 0 0 1 2 3 4 10 5 0.2 0.4 0.6 1.0 1.2 1.4 VSD, Source-Drain voltage [V] Figure 3. On-Resistance Variation vs. Drain Current and Gate Voltage Figure 4. Body Diode Forward Voltage Variation with Source Current and Temperature 400 12 Ciss = Cgs + Cgd (Cds = shorted) Coss = Cds + Cgd Crss = Cgd VDS = 90V 10 VDS = 225V VGS, Gate-Source Voltage [V] 300 Ciss Capacitance [pF] 0.8 ID, Drain Current [A] 200 Coss 100 Crss ※ Note ; 1. VGS = 0 V 2. f = 1 MHz VDS = 360V 8 6 4 2 ※ Note : ID = 0.5 A 0 -1 10 0 10 0 1 10 VDS, Drain-Source Voltage [V] 1 2 3 4 5 6 7 QG, Total Gate Charge [nC] Figure 5. Capacitance Characteristics ©2002 Fairchild Semiconductor Corporation SSN1N45B Rev. C0 0 Figure 6. Gate Charge Characteristics 3 www.fairchildsemi.com (continued) 3.0 1.2 RDS(ON) , (Normalized) Drain-Source On-Resistance BV DSS , (Normalized) Drain-Source Breakdown Voltage 2.5 1.1 1.0 ※ Notes : 1. VGS = 0 V 2. ID = 250 μ A 0.9 0.8 -100 -50 0 50 100 150 2.0 1.5 1.0 ※ Notes : 1. VGS = 10 V 2. ID = 0.25 A 0.5 0.0 -100 200 -50 0 o 50 100 150 200 o TJ, Junction Temperature [ C] TJ, Junction Temperature [ C] Figure 7. Breakdown Voltage Variation vs. Temperature Figure 8. On-Resistance Variation vs. Temperature 0.6 Operation in This Area is Limited by R DS(on) 1 0.5 100 µs 1 ms 10 ms 100 ms 1s 0 10 0.4 ID, Drain Current [A] ID, Drain Current [A] 10 0.3 -1 10 DC 0.2 ※ Notes : o -2 1. TC = 25 C 10 o 2. TJ = 150 C 3. Single Pulse 0.1 -3 10 0 1 10 2 10 0.0 25 3 10 10 50 75 Figure 9. Maximum Safe Operating Area ZθJL(t), Thermal Response [oC/W] 10 100 125 150 TC, Case Temperature [℃] VDS, Drain-Source Voltage [V] Figure 10. Maximum Drain Current vs. Case Temperature 2 D = 0 .5 10 0 .2 1 0 .1 PDM 0 .0 5 10 t1 0 .0 2 0 t2 0 .0 1 10 ※ N o te s : 1 . Z θ J L (t) = 5 0 ℃ / W M a x . 2 . D u ty F a c to r, D = t 1 /t 2 3 . T J M - T L = P D M * Z θ J L (t) s i n g l e p u ls e -1 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 10 2 10 3 t1 , R e c t a n g u l a r P u l s e D u r a t i o n [ s e c ] Figure 11. Transient Thermal Response Curve ©2002 Fairchild Semiconductor Corporation SSN1N45B Rev. C0 4 www.fairchildsemi.com SSN1N45B — N-Channel B-FET ! SSN1N45B — N-Channel B-FET 50KΩ 200nF 12V VGS Same Type as DUT Qg 10V 300nF VDS VGS Qgs Qgd DUT IG = const. 3mA Charge Figure 12. Gate Charge Test Circuit & Waveform VDS RG RL VDS 90% VDD VGS VGS DUT V 10V GS 10% td(on) tr td(off) t on t off tf Figure 13. Resistive Switching Test Circuit & Waveforms VDS BVDSS 1 EAS = ---- L IAS2 -------------------2 BVDSS - VDD L BVDSS IAS ID RG V 10V GS GS VDD ID (t) VDS (t) VDD DUT tp Time tp Figure 14. Unclamped Inductive Switching Test Circuit & Waveforms ©2002 Fairchild Semiconductor Corporation SSN1N45B Rev. C0 5 www.fairchildsemi.com SSN1N45B — N-Channel B-FET DUT + VDS _ I SD L Driver RG VGS VGS ( Driver ) I SD ( DUT ) Same Type as DUT VDD • dv/dt controlled by RG • ISD controlled by pulse period Gate Pulse Width D = -------------------------Gate Pulse Period 10V IFM , Body Diode Forward Current di/dt IRM Body Diode Reverse Current VDS ( DUT ) Body Diode Recovery dv/dt VSD VDD Body Diode Forward Voltage Drop Figure 15. Peak Diode Recovery dv/dt Test Circuit & Waveforms ©2002 Fairchild Semiconductor Corporation SSN1N45B Rev. C0 6 www.fairchildsemi.com SSN1N45B — N-Channel B-FET Mechanical Dimensions Figure 16. TO92, Molded, 3-Lead, 0.200 In Line Spacing LD Form ( J61Z Option) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/package/packageDetails.html?id=PN_TO92-F03 ©2002 Fairchild Semiconductor Corporation SSN1N45B Rev. C0 7 www.fairchildsemi.com tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. 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Obsolete Not In Production Datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor. The datasheet is for reference information only. Rev. I66 ©2002 Fairchild Semiconductor Corporation SSN1N45B Rev. C0 8 www.fairchildsemi.com SSN1N45B — N-Channel B-FET TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks. 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