WE512K8, WE256K8, WE128K8-XCX White Electronic Designs 512Kx8 CMOS EEPROM, WE512K8-XCX, SMD 5962-93091 512Kx8 BIT CMOS EEPROM MODULE FIGURE 1 FEATURES Read Access Times of 150, 200, 250, 300ns JEDEC Standard 32 Pin, Hermetic Ceramic DIP (Package 300) Commercial, Industrial and Military Temperature Ranges MIL-STD-883 Compliant Devices Available Write Endurance 10,000 Cycles Data Retention at 25°C, 10 Years Low Power CMOS Operation: Pin Configuration Top View 3mA Standby Typical/100mA Operating Maximum 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A18 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS Automatic Page Write Operation Internal Address and Data Latches for VCC WE# A17 A14 A13 A8 A9 A11 OE# A10 CS# I/O7 I/O6 I/O5 I/O4 I/O3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 512 Bytes, 1 to 128 Bytes/Row, Four Pages Page Write Cycle Time 10mS Max. Data Polling for End of Write Detection Hardware and Software Data Protection TTL Compatible Inputs and Outputs Pin Description A0-18 I/O0-7 CS# OE# WE# VCC VSS Address Inputs Data Input/Output Chip Select Output Enable Write Enable +5.0V Power Ground Block Diagram A0-16 I/O0-7 WE# OE# 128K x 8 A17 A18 128K x 8 128K x 8 128K x 8 Decoder CS# White Electronic Designs Corp. reserves the right to change products or specifications without notice. May 2000 Rev. 1 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com WE512K8, WE256K8, WE128K8-XCX White Electronic Designs 256Kx8 CMOS EEPROM, WE256K8-XCX, SMD 5962-93155 256Kx8 BIT CMOS EEPROM MODULE FIGURE 2 FEATURES Read Access Times of 150, 200ns JEDEC Standard 32 Pin, Hermetic Ceramic DIP (Package 302) Commercial, Industrial and Military Temperature Ranges MIL-STD-883 Compliant Devices Available Write Endurance 10,000 Cycles Data Retention at 25°C, 10 Years Low Power CMOS Operation: Pin Configuration Top View 2mA Standby Typical/90mA Operating Maximum 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 NC A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS Automatic Page Write Operation Internal Address and Data Latches for 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC WE# A17 A14 A13 A8 A9 A11 OE# A10 CS# I/O7 I/O6 I/O5 I/O4 I/O3 512 Bytes, 1 to 64 Bytes/Row, Eight Pages Page Write Cycle Time 10mS Max. Data Polling for End of Write Detection Hardware and Software Data Protection TTL Compatible Inputs and Outputs Pin Description A0-18 I/O0-7 CS# OE# WE# VCC VSS Address Inputs Data Input/Output Chip Select Output Enable Write Enable +5.0V Power Ground Block Diagram A0-14 I/O0-7 WE# OE# A15 A16 A17 1 2 8 32K x 8 32K x 8 32K x 8 Decoder CS# White Electronic Designs Corp. reserves the right to change products or specifications without notice. May 2000 Rev. 1 2 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com WE512K8, WE256K8, WE128K8-XCX White Electronic Designs 128Kx8 CMOS EEPROM, WE128K8-XCX, SMD 5962-93154 128Kx8 BIT CMOS EEPROM MODULE FIGURE 3 FEATURES Read Access Times of 150, 200ns JEDEC Standard 32 Pin, Hermetic Ceramic DIP (Package 300) Commercial, Industrial and Military Temperature Ranges MIL-STD-883 Compliant Devices Available Write Endurance 10,000 Cycles Data Retention at 25°C, 10 Years Low Power CMOS Operation: Pin Configuration Top View NC A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1mA Standby Typical/70mA Operating Automatic Page Write Operation Internal Address and Data Latches for 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC WE# NC A14 A13 A8 A9 A11 OE# A10 CS# I/O7 I/O6 I/O5 I/O4 I/O3 256 Bytes, 1 to 64 Bytes/Row, Four Pages Page Write Cycle Time 10mS Max. Data Polling for End of Write Detection Hardware and Software Data Protection TTL Compatible Inputs and Outputs Pin Description A0-18 I/O0-7 CS# OE# WE# VCC VSS Address Inputs Data Input/Output Chip Select Output Enable Write Enable +5.0V Power Ground Block Diagram A0-14 I/O0-7 WE# OE# 32K x 8 A15 A16 32K x 8 32K x 8 32K x 8 Decoder CS# White Electronic Designs Corp. reserves the right to change products or specifications without notice. May 2000 Rev. 1 3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com WE512K8, WE256K8, WE128K8-XCX White Electronic Designs ABSOLUTE MAXIMUM RATINGS Parameter Operating Temperature Storage Temperature Signal Voltage Any Pin Voltage on OE# and A9 Thermal Resistance junction to case Lead Temperature (soldering -10 secs) Symbol TA TSTG VG θJC TRUTH TABLE -55 to +125 -65 to +150 -0.6 to + 6.25 -0.6 to +13.5 28 Unit °C °C V V °C/W +300 °C CS# H L L X X X Min 4.5 2.0 -0.3 -55 -40 Max 5.5 VCC + 0.3 +0.8 +125 +85 Mode Standby Read Write Out Disable Write Inhibit Data I/O High Z Data Out Data In High Z/Data Out TA = +25°C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIH VIL TA TA WE# X H L X H X CAPACITANCE NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameter Supply Voltage Input High Voltage Input Low Voltage Operating Temp. (Mil.) Operating Temp. (Ind.) OE# X L H H X L Unit V V V °C °C Parameter Sym Condition 512Kx8 256Kx8 128Kx8 Unit Max Max Max Input Capacitance CIN VIN = 0V, f = 1MHz 45 80 45 pF Output COUT VI/O = 0V, f = 1MHz Capacitance 60 80 60 pF This parameter is guaranteed by design but not tested. DC CHARACTERISTICS VCC = 5.0V, VSS = 0V, -55°C ≤ TA ≤ +125°C Parameter Input Leakage Current Output Leakage Current Dynamic Supply Current Standby Current Output Low Voltage Output High Voltage 512K x 8 Symbol Conditions ILI ILO ICC ISB VOL VOH Min VCC = 5.5, VIN = GND to VCC CS# = VIH, OE# = VIH, Vout = GND to VCC CS# = VIL, OE# = VIH, f = 5MHz, VCC = 5.5 CS# = VIL, OE# = VIH, f = 5MHz, VCC = 5.5 IOL = 2.1mA, VCC = 4.5V IOH = -400µA, VCC = 4.5V Typ 80 3 2.4 256K x 8 Max 10 10 100 8 0.45 Min Typ 60 2 2.4 128K x 8 Max 10 10 90 6 0.45 Min Typ 50 1 Max 10 10 70 4 0.45 2.4 Unit µA µA mA mA V V NOTE: DC test conditions: Vih = Vcc -0.3V, Vil = 0.3V FIGURE 4 AC Test Circuit AC TEST CONDITIONS Parameter Input Pulse Levels Input Rise and Fall Input and Output Reference Level Output Timing Reference Level Typ VIL = 0, VIH = 3.0 5 1.5 1.5 Unit V ns V V Notes: VZ is programmable from -2V to +7V. IOL & IOH programmable from 0 to 16mA. Tester Impedance Z0 = 75Ω. VZ is typically the midpoint of VOH and VOL. IOL & IOH are adjusted to simulate a typical resistive load circuit. ATE tester includes jig capacitance. White Electronic Designs Corp. reserves the right to change products or specifications without notice. May 2000 Rev. 1 4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com WE512K8, WE256K8, WE128K8-XCX White Electronic Designs READ places the selected data byte on I/O0 through I/O7 after the access time. The output of the memory is placed in a high impedance state shortly after either the OE# line or CS# line is returned to a high level. Figure 5 shows Read cycle waveforms. A read cycle begins with selection address, chip select and output enable. Chip select is accomplished by placing the CS# line low. Output enable is done by placing the OE# line low. The memory FIGURE 5 – READ WAVEFORMS ADDRESS CS# OE# OUTPUT NOTE: OE# may be delayed up to tACS-tOE after the falling edge of CS# without impact on tOE or by tACC-tOE after an address change without impact on tACC. AC READ CHARACTERISTICS (See Figure 5) FOR WE512K8-XCX VCC = 5.0V, VSS = 0V, -55°C ≤ TA ≤ +125°C Parameter Symbol Read Cycle Time Address Access Time Chip Select Access Time Output Hold from Address Change, OE# or CS# Output Enable to Output Valid Chip Select or Output Enable to High Z Output trc tacc tacs toh toe tdf -150 Min 150 -200 Max Min 200 -250 Max 150 150 Min 250 Max 200 200 0 0 -300 Min 300 250 250 300 300 0 85 70 Max 0 85 70 100 70 125 70 Unit ns ns ns ns ns ns FOR WE256K8-XCX and WE128K8-XCX Parameter Read Cycle Time Address Access Time Chip Select Access Time Output Hold from Address Change, OE# or CS# Output Enable to Output Valid Chip Select or Output Enable to High Z Output -150 Symbol Min 150 trc tacc tacs toh toe tdf -200 Max Min 200 150 150 0 Max 200 200 0 85 70 85 70 Unit ns ns ns ns ns ns White Electronic Designs Corp. reserves the right to change products or specifications without notice. May 2000 Rev. 1 5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com WE512K8, WE256K8, WE128K8-XCX White Electronic Designs WRITE WRITE CYCLE TIMING Write operations are initiated when both CS# and WE# are low and OE# is high. The EEPROM devices support both a CS# and WE# controlled write cycle. The address is latched by the falling edge of either CS# or WE#, whichever occurs last. Figures 6 and 7 show the write cycle timing relationships. A write cycle begins with address application, write enable and chip select. Chip select is accomplished by placing the CS# line low. Write enable consists of setting the WE line low. The write cycle begins when the last of either CS# or WE# goes low. The data is latched internally by the rising edge of either CS# or WE#, whichever occurs first. A byte write operation will automatically continue to completion. The WE# line transition from high to low also initiates an internal 150µsec delay timer to permit page mode operation. Each subsequent WE# transition from high to low that occurs before the completion of the 150µsec time out will restart the timer from zero. The operation of the timer is the same as a retriggerable one-shot. AC WRITE CHARACTERISTICS VCC = 5.0V, VSS = 0V, -55°C ≤ TA ≤ +125°C Parameter Write Cycle Time, TYP = 6mS Address Set-up Time Write Pulse Width (WE# or CS#) Chip Select Set-up Time Address Hold Time (1) Data Hold Time Chip Select Hold Time Data Set-up Time Output Enable Set-up Time Output Enable Hold Time Write Pulse Width High Symbol tWC tAS tWP tCS tAH tDH tCH tDS tOES tOEH tWPH 512K x 8 Min 256K x 8 Max 10 10 150 0 125 10 0 100 10 10 50 Min 30 150 0 50 0 0 100 30 0 50 Max 10 128K x 8 Min 30 150 0 50 0 0 100 30 0 50 Max 10 Unit ms ns ns ns ns ns ns ns ns ns ns NOTES: 1. A17 and A18 must remain valid through WE# and CS# low pulse, for 512K x 8. A15, A16, and A17 must remain valid through WE# and CS# low pulse, for 256K x 8. A15 and A16 must remain valid through WE# and CS# low pulse, for 128K x 8. White Electronic Designs Corp. reserves the right to change products or specifications without notice. May 2000 Rev. 1 6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com WE512K8, WE256K8, WE128K8-XCX White Electronic Designs FIGURE 6 – WRITE WAVEFORMS WE# CONTROLLED OE# ADDRESS (1) CS# WE# DATA IN NOTE: 1. Decoded Address Lines must be valid for the duration of the write. FIGURE 7 – WRITE WAVEFORMS CS# CONTROLLED OE# ADDRESS (1) CS# WE# DATA IN NOTE: 1. Decoded Address Lines must be valid for the duration of the write. White Electronic Designs Corp. reserves the right to change products or specifications without notice. May 2000 Rev. 1 7 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com WE512K8, WE256K8, WE128K8-XCX White Electronic Designs Data polling allows a simple bit test operation to determine the status of the EEPROM. During the internal programming cycle, a read of the last byte written will produce the complement of the data on I/O7. For example, if the data written consisted of I/O7 = HIGH, then the data read back would consist of I/O7 = LOW. DATA POLLING Operation with data polling permits a faster method of writing to the EEPROM. The actual time to complete the memory programming cycle is faster than the guaranteed maximum. The EEPROM features a method to determine when the internal programming cycle is completed. After a write cycle is initiated, the EEPROM will respond to read cycles to provide the microprocessor with the status of the programming cycle. The status consists of the last data byte written being returned with data bit I/O7 complemented during the programming cycle, and I/O7 true after completion. A polled byte write sequence would consist of the following steps: 1. write byte to EEPROM 2. store last byte and last address written 3. release a time slice to other tasks 4. read byte from EEPROM - last address 5. compare I/O7 to stored value a) If different, write cycle is not completed, go to step 3. b) If same, write cycle is completed, go to step 1 or step 3. DATA POLLING AC CHARACTERISTICS VCC = 5.0V, VSS = 0V, -55°C ≤ TA ≤ +125°C Parameter Data Hold Time Output Enable Hold Time Output Enable To Output Delay Write Recovery Time Symbol tDH tOEH tOE tWR 512Kx8 Min 10 10 256Kx8 Max Min 0 0 128Kx8 Max 100 Min 0 0 100 0 0 Unit Max 100 0 ns ns ns ns FIGURE 8 – DATA POLLING WAVEFORMS WE1-4# CS1-4# OE# I/O7 ADDRESS White Electronic Designs Corp. reserves the right to change products or specifications without notice. May 2000 Rev. 1 8 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com WE512K8, WE256K8, WE128K8-XCX White Electronic Designs The page address must be the same for each byte load and must be valid during each high to low transition of WE# (or CS#). The block address also must be the same for each byte load and must remain valid throughout the WE# (or CS#) low pulse. The page and block address lines are summarized below: PAGE WRITE OPERATION These devices have a page write operation that allows one to 64 bytes of data (one to 128 bytes for the WE512K8) to be written into the device and then simultaneously written during the internal programming period. Successive bytes may be loaded in the same manner after the first data byte has been loaded. An internal timer begins a time out operation at each write cycle. If another write cycle is completed within 150µs or less, a new time out period begins. Each write cycle restarts the delay period. The write cycles can be continued as long as the interval is less than the time out period. PAGE MODE CHARACTERISTICS VCC = 5.0V, VSS = 0V, -55°C ≤ TA ≤ +125°C Parameter Write Cycle Time, TYP = 6mS Data Set-up Time Data Hold Time Write Pulse Width Byte Load Cycle Time Write Pulse Width High The usual procedure is to increment the least significant address lines from A0 through A5 (A0 through A6 for the WE512K8) at each write cycle. In this manner a page of up to 64 bytes (128 bytes for the WE512K8) can be loaded into the EEPROM in a burst mode before beginning the relatively long interval programming cycle. Device WE512K8-XCX WE256K8-XCX WE128K8-XCX After the 150µs time out is completed, the EEPROM begins an internal write cycle. During this cycle the entire page of bytes will be written at the same time. The internal programming cycle is the same regardless of the number of bytes accessed. Symbol tWC tDS tDH tWP tBLC tWPH Block Address A17-A18 A15-A17 A15-A16 Min Max 10 100 10 150 150 50 Unit ms ns ns ns µs ns Page Address A7-A16 A6-A14 A6-A14 FIGURE 9 – PAGE WRITE WAVEFORMS OE# CS# WE# ADDRESS (1) DATA NOTE: 1. Decoded Address Lines must be valid for the duration of the write. White Electronic Designs Corp. reserves the right to change products or specifications without notice. May 2000 Rev. 1 9 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com WE512K8, WE256K8, WE128K8-XCX White Electronic Designs FIGURE 10 – SOFTWARE BLOCK DATA PROTECTION ENABLE ALGORITHM LOAD DATA AA TO ADDRESS 5555 (1) LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA A0 TO ADDRESS 5555 WRITES ENABLED(2) LOAD DATA XX TO ANY ADDRESS(4) LOAD LAST BYTE TO LAST ADDRESS ENTER DATA PROTECT STATE NOTES: 1. Data Format: I/O7-0 (Hex); Address Format: A14 -A0 (Hex). A17 and A18 control selection of one of four blocks in the 512Kx8. A15, A16, and A17 control selection of one of 8 pages in the 256Kx8. A15 and A16 control one of the four blocks in the 128Kx8. 2. Write Protect state will be activated at end of write even if no other data is loaded. 3. Write Protect state will be deactivated at end of write period even if no other data is loaded. 4. 1 to 128 bytes of data at each of 4 blocks may be loaded in the 512Kx8. 1 to 64 bytes of data at each of 8 blocks may be loaded in the 256Kx8 and 1 to 64 bytes on 4 blocks in the 128Kx8. White Electronic Designs Corp. reserves the right to change products or specifications without notice. May 2000 Rev. 1 10 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com WE512K8, WE256K8, WE128K8-XCX White Electronic Designs FIGURE 11 – SOFTWARE BLOCK DATA PROTECTION DISABLE ALGORITHM LOAD DATA AA TO ADDRESS 5555 SOFTWARE DATA PROTECTION A software write protection feature may be enabled or disabled by the user. When shipped by White Microelectronics, the devices have the feature disabled. Write access to the device is unrestricted. To enable software write protection, the user writes three access code bytes to three special internal locations. Once write protection has been enabled, each write to the EEPROM must use the same three byte write sequence to permit writing. After setting software data protection, any attempt to write to the device without the three-byte command sequence will start the internal write timers. No data will be written to the device, however, for the duration of tWC. The write protection feature can be disabled by a six byte write sequence of specific data to specific locations. Power transitions will not reset the software write protection. (1) LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 80 TO ADDRESS 5555 LOAD DATA AA TO ADDRESS 5555 Each 32K byte block (128K bytes for the WE512K8) of EEPROM has independent write protection. One or more blocks may be enabled and the rest disabled in any combination. The software write protection guards against inadvertent writes during power transitions or unauthorized modification using a PROM programmer. The block selection is controlled by the upper most address lines (A17 through A18 for the WE512K8, A15 through A17 for the WE256K8, or A15 and A16 for the WE128K8). LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 20 TO ADDRESS 5555 LOAD DATA XX TO ANY ADDRESS(4) EXIT DATA PROTECT STATE(3) HARDWARE DATA PROTECTION LOAD LAST BYTE TO LAST ADDRESS Several methods of hardware data protection have been implemented in the White Microelectronics EEPROM. These are included to improve reliability during normal operations. NOTES: 1. Data Format: I/O7-0 (Hex); Address Format: A14 -A0 (Hex). A17 and A18 control selection of one of four blocks in the 512Kx8. A15, A16, and A17 control selection of one of 8 pages in the 256Kx8. A15 and A16 control one of the four blocks in the 128Kx8. 2. Write Protect state will be activated at end of write even if no other data is loaded. 3. Write Protect state will be deactivated at end of write period even if no other data is loaded. 4. 1 to 128 bytes of data at each of 4 blocks may be loaded in the 512Kx8. 1 to 64 bytes of data at each of 8 blocks may be loaded in the 256Kx8 and 1 to 64 bytes on 4 blocks in the 128Kx8. a) VCC power on delay As VCC climbs past 3.8V typical the device will wait 5mSec typical before allowing write cycles. b) VCC sense c) Write inhibiting While below 3.8V typical write cycles are inhibited. Holding OE# low and either CS# or WE# high inhibits write cycles. d) Noise filter Pulses of <8ns (typ) on WE# or CS# will not initiate a write cycle. White Electronic Designs Corp. reserves the right to change products or specifications without notice. May 2000 Rev. 1 11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com WE512K8, WE256K8, WE128K8-XCX White Electronic Designs PACKAGE 300: 32 PIN, CERAMIC DIP, SINGLE CAVITY SIDE BRAZED ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES PACKAGE 302: 32 PIN, CERAMIC DIP, DUAL CAVITY BOTTOM BRAZED ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES White Electronic Designs Corp. reserves the right to change products or specifications without notice. May 2000 Rev. 1 12 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com WE512K8, WE256K8, WE128K8-XCX White Electronic Designs ORDERING INFORMATION W E XXXK8 - XXX C X X LEAD FINISH: Blank = Gold plated leads A = Solder dip leads PROCESSING: Q = MIL-STD-883 Compliant M = Military Screened -55°C to +125°C I = Industrial -40°C to +85°C C = Commercial 0°C to +70°C PACKAGE: C = Ceramic DIP (Package 300 for 128Kx8) (Package 302 for 256Kx8) (Package 300 for 512Kx8) ACCESS TIME (ns) ORGANIZATION, 512Kx8, 256Kx8 or 128Kx8 EEPROM WHITE ELECTRONIC DESIGNS Device Type Speed Package WM Part No. SMD No. 512K x 8 EEPROM 150ns 32 pin DIP (C) WE512K8-150CQ 5962-93091 01HYX 512K x 8 EEPROM 300ns 32 pin DIP (C) WE512K8-300CQ 5962-93091 02HYX 512K x 8 EEPROM 250ns 32 pin DIP (C) WE512K8-250CQ 5962-93091 03HYX 512K x 8 EEPROM 200ns 32 pin DIP (C) WE512K8-200CQ 5962-93091 04HYX 256K x 8 EEPROM 200ns 32 pin DIP (C) WE256K8-200CQ 5962-93155 01HYX 256K x 8 EEPROM 150ns 32 pin DIP (C) WE256K8-150CQ 5962-93155 02HYX 128K x 8 EEPROM 200ns 32 pin DIP (C) WE128K8-200CQ 5962-93154 01HXX 128K x 8 EEPROM 150ns 32 pin DIP (C) WE128K8-150CQ 5962-93154 02HXX White Electronic Designs Corp. reserves the right to change products or specifications without notice. May 2000 Rev. 1 13 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com