ETC WSE128K16

WSE128K16-XXX
128KX16 SRAM/EEPROM MODULE
PRELIMINARY*
FEATURES
■ TTL Compatible Inputs and Outputs
■ Access Times of 35ns (SRAM) and 150ns (EEPROM)
■ Built-in Decoupling Caps and Multiple Ground Pins for
Low Noise Operation
■ Access Times of 45ns (SRAM) and 120ns (EEPROM)
■ Weight - 13 grams typical
■ Access Times of 70ns (SRAM) and 300ns (EEPROM)
■ Packaging
EEPROM MEMORY FEATURES
• 66 pin, PGA Type, 1.075" square HIP, Hermetic Ceramic
HIP (H1) (Package 400)
■ Write Endurance 10,000 Cycles
• 68 lead, Hermetic CQFP (G2T), 22mm (0.880") square
(Package 509). Designed to fit JEDEC 68 lead 0.990" CQFJ
footprint (Fig. 2)
■ Low Power CMOS Operation
■ Data Retention at 25°C, 10 Years
■ Automatic Page Write Operation
■ 128Kx16 SRAM
■ Page Write Cycle Time 10ms Max.
■ 128Kx16 EEPROM
■ Data Polling for End of Write Detection
■ Organized as 128Kx16 of SRAM and 128Kx16 of EEPROM
Memory with separate Data Buses
■ Hardware and Software Data Protection
■ TTL Compatible Inputs and Outputs
■ Both blocks of memory are User Configurable as 256Kx8
* This data sheet describes a product under development, not fully
characterized, and is subject to change without notice.
■ Low Power CMOS
■ Commercial, Industrial and Military Temperature Ranges
FIG.1
PIN CONFIGURATION FOR WSE128K16-XH1X
PIN DESCRIPTION
TOP VIEW
1
12
23
34
45
56
ED0-15
EEPROM Data Inputs/Outputs
SD0-15
SRAM Data Inputs/Outputs
SD8
SWE2
SD15
ED8
VCC
ED15
A0-16
Address Inputs
SD9
SCS2
SD14
ED9
ECS2
ED14
SWE1-2
SRAM Write Enable
SCS1-2
SRAM Chip Selects
OE
Output Enable
VCC
Power Supply
GND
SD10
SD13
EWE2
ED10
ED13
A13
SD11
SD12
A6
ED11
ED12
A14
A10
OE
A7
A3
A0
GND
Ground
A15
A11
NC
NC
A4
A1
NC
Not Connected
A16
A12
SWE1
A8
A5
A2
EWE1-2
EEPROM Write Enable
ECS1-2
EEPROM Chip Select
NC
VCC
SD7
A9
EWE1
ED7
SD0
SCS1
SD6
ED0
ECS1
ED6
SD1
NC
SD5
ED1
GND
ED5
SD2
SD3
SD4
ED2
ED3
ED4
BLOCK DIAGRAM
S W E1 S CS1
11
22
33
44
55
E W E1 E CS1
E W E2 E CS2
128K x 8
SRAM
128K x 8
SRAM
128K x 8
EEPROM
128K x 8
EEPROM
66
8
SD0-7
May 2001, Rev. 4
S W E2 S CS2
OE
A0-16
1
8
SD8-15
8
ED0-7
8
ED8-15
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WSE128K16-XXX
FIG. 2
PIN CONFIGURATION FOR WSE128K16-XG2TX
PIN DESCRIPTION
NC
A0
A1
A2
A3
A4
A5
ECS1
GND
ECS2
SWE1
A6
A7
A8
A9
A10
VCC
TOP VIEW
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7
GND
SD8
SD9
SD10
SD11
SD12
SD13
SD14
SD15
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
ED0
ED1
ED2
ED3
ED4
ED5
ED6
ED7
GND
ED8
ED9
ED10
ED11
ED12
ED13
ED14
ED15
The WEDC 68 lead G2T CQFP
fills the same fit and function as
the JEDEC 68 lead CQFJ or 68
PLCC. But the G2T has the TCE
and lead inspection advantage
of the CQFP form.
SRAM Data Inputs/Outputs
A0-16
Address Inputs
SWE1-2
SRAM Write Enable
SCS1-2
SRAM Chip Selects
OE
Output Enable
VCC
Power Supply
GND
Ground
NC
Not Connected
EWE1-2
EEPROM Write Enable
ECS1-2
EEPROM Chip Select
BLOCK DIAGRAM
NC
NC
NC
EWE2
EWE1
SWE2
A16
SCS1
OE
SCS2
NC
A15
A14
A13
A12
A11
VCC
EEPROM Data Inputs/Outputs
0.940"
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
S W E1 S CS1
S W E2 S CS2
E W E1 E CS1
E W E2 E CS2
OE
A0-16
128K x 8
SRAM
8
SD0-7
White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520
ED0-15
SD0-15
2
128K x 8
SRAM
8
SD8-15
128K x 8
EEPROM
8
ED0-7
128K x 8
EEPROM
8
ED8-15
WSE128K16-XXX
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Operating Temperature
Storage Temperature
VG
Junction Temperature
TJ
Supply Voltage
Min
Max
Unit
°C
V CC
4.5
5.5
V
°C
Input High Voltage
V IH
2.0
V CC + 0.3
V
Vcc+0.5
V
Input Low Voltage
V IL
-0.3
+0.8
V
150
°C
Operating Temp. (Mil.)
TA
-55
+125
°C
7.0
V
-55
-65
TSTG
Signal Voltage Relative to GND
Symbol
Supply Voltage
Min
TA
-0.5
-0.5
VCC
RECOMMENDED OPERATING CONDITIONS
Max
Unit
+125
+150
Parameter
EEPROM TRUTH TABLE
CS
H
L
L
X
X
X
OE
X
L
H
H
X
L
SCS
H
L
L
L
OE
X
L
H
X
CAPACITANCE
(TA = +25°C)
Parameter
Symbol
Conditions
OE capacitance
COE
VIN = 0 V, f = 1.0 MHz
WE1-4 capacitance
HIP (PGA)
CQFP G2T
CWE
VIN = 0 V, f = 1.0 MHz
Max
50
Unit
pF
pF
20
20
CS1-4 capacitance
CCS
VIN = 0 V, f = 1.0 MHz
20
pF
Data I/O capacitance
CI/O
VI/O = 0 V, f = 1.0 MHz
20
pF
Address input capacitance
CAD
VIN = 0 V, f = 1.0 MHz
50
pF
WE
X
H
L
X
H
X
Mode
Standby
Read
Write
Out Disable
Write
Inhibit
Data I/O
High Z
Data Out
Data In
High Z/Data Out
SRAM TRUTH TABLE
This parameter is guaranteed by design but not tested.
SWE
X
H
H
L
Mode
Standby
Read
Read
Write
Data I/O
High Z
Data Out
High Z
Data In
Power
Standby
Active
Active
Active
DC CHARACTERISTICS
(VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C)
Parameter
Max
Unit
Input Leakage Current
Symbol
I LI
V CC = 5.5, V IN = GND to VCC
10
µA
Output Leakage Current
I LO
SCS = VIH, OE = VIH, VOUT = GND to VCC
10
µA
ICCx16
SCS = VIL, OE = ECS = VIH, f = 5MHz, V CC = 5.5
360
mA
SRAM Operating Supply Current x 16 Mode
Standby Current
Conditions
Min
I SB
ECS = SCS = VIH, OE = VIH, f = 5MHz, V CC = 5.5
31.2
mA
(35 to 45ns)
V OL
I OL = 8.0mA, V CC = 4.5
0.4
V
(70ns)
V OL
I OL = 2.1mA, V CC = 4.5
0.4
V
(35 to 45ns)
V OH
I OH = -4.0mA, V CC = 4.5
2.4
V
(70ns)
V OH
I OH = -1mA, V CC = 4.5
2.4
V
EEPROM Operating Supply Current x 16 Mode
I CC1
ECS = VIL, OE = SCS = VIH
155
EEPROM Output Low Voltage
V OL
I OL = 2.1 mA, V CC = 4.5V
0.45
EEPROM Output High Voltage
V OH1
I OH = 400 µA, V CC = 4.5V
SRAM Output Low Voltage
SRAM Output High Voltage
2.4
mA
V
V
NOTES:
1. The I CC current listed includes both the DC operating current and the frequency dependent component (@ 5 MHz).
The frequency component typically is less than 2 mA/MHz, with OE at VIH.
2. DC test conditions: V IL = 0.3V, VIH = V CC - 0.3V
3
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WSE128K16-XXX
SRAM AC CHARACTERISTICS
(VCC = 5.0V, GND = 0V, TA = -55°C to +125°C)
Parameter
Symbol
Read Cycle
-35
Min
Read Cycle Time
t RC
Address Access Time
t AA
Output Hold from Address Change
t OH
Chip Select Access Time
t ACS
-45
Max
35
Min
-70
Max
45
Max
70
35
0
Units
Min
ns
45
0
70
ns
70
ns
35
ns
3
35
ns
45
Output Enable to Output Valid
t OE
Chip Select to Output in Low Z
t CLZ 1
3
20
3
25
3
Output Enable to Output in Low Z
t OLZ 1
0
0
0
Chip Disable to Output in High Z
t CHZ 1
20
20
25
ns
Output Disable to Output in High Z
t OHZ 1
20
20
25
ns
ns
ns
1. This parameter is guaranteed by design but not tested.
SRAM AC CHARACTERISTICS
(VCC = 5.0V, GND = 0V, TA = -55°C to +125°C)
Parameter
Symbol
Write Cycle
-35
Min
-45
Max
Min
-70
Max
Units
Min
Max
Write Cycle Time
t WC
35
45
70
ns
Chip Select to End of Write
t CW
25
30
60
ns
Address Valid to End of Write
t AW
25
30
60
ns
Data Valid to End of Write
t DW
20
25
30
ns
Write Pulse Width
t WP
25
30
50
ns
Address Setup Time
t AS
0
0
5
ns
Address Hold Time
t AH
0
0
5
ns
Output Active from End of Write
t OW 1
4
4
5
Write Enable to Output in High Z
t WHZ 1
Data Hold Time
t DH
20
0
ns
25
0
25
ns
0
ns
1. This parameter is guaranteed by design but not tested.
FIG. 3
AC TEST CIRCUIT
AC TEST CONDITIONS
Parameter
I OL
Current Source
VZ
D.U.T.
≈ 1.5V
(Bipolar Supply)
C eff = 50 pf
I OH
Current Source
White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520
4
Typ
Unit
Input Pulse Levels
VIL = 0, VIH = 3.0
V
Input Rise and Fall
5
ns
Input and Output Reference Level
1.5
V
Output Timing Reference Level
1.5
V
NOTES:
V Z is programmable from -2V to +7V.
I OL & IOH programmable from 0 to 16mA.
Tester Impedance Z0 = 75 Ω.
V Z is typically the midpoint of VOH and V OL.
I OL & IOH are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
WSE128K16-XXX
FIG. 4
SRAM READ CYCLE
tRC
ADDRESS
tAA
SCS
tRC
tCHZ
tACS
ADDRESS
tCLZ
tAA
SOE
tOE
tOLZ
tOH
SRAM
SRAM
DATA I/O
DATA I/O
PREVIOUS DATA VALID
DATA VALID
tOHZ
DATA VALID
HIGH IMPEDANCE
READ CYCLE 2, (SWE = VIH)
READ CYCLE 1, (SCS = OE = VIL, SWE = VIH)
FIG. 5 SRAM WRITE CYCLE
SWE CONTROLLED
tWC
ADDRESS
tAW
tAH
tCW
SCS
tAS
tWP
SWE
tOW
tWHZ
tDW
tDH
SRAM
DATA I/O
DATA VALID
WRITE CYCLE 1, SWE CONTROLLED
FIG. 6
SRAM WRITE CYCLE
SCS CONTROLLED
tWC
WS32K32-XHX
ADDRESS
tAS
tAW
tAH
tCW
SCS
tWP
SWE
tDW
SRAM
DATA I/O
tDH
DATA VALID
WRITE CYCLE 2, SCS CONTROLLED
5
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WSE128K16-XXX
EEPROM AC WRITE CHARACTERISTICS
(VCC = 5.0V, V SS = 0V, TA = -55°C to +125°C)
EEPROM WRITE
A write cycle is initiated when OE is high and a low pulse is on
EWE or ECS with ECS or EWE low. The address is latched on the
falling edge of ECS or EWE whichever occurs last. The data is
latched by the rising edge of ECS or EWE, whichever occurs first.
A byte write operation will automatically continue to completion.
Write Cycle Parameter
WRITE CYCLE TIMING
Figures 7 and 8 show the write cycle timing relationships. A
write cycle begins with address application, write enable and
chip select. Chip select is accomplished by placing the ECS
line low. Write enable consists of setting the EWE line low.
The write cycle begins when the last of either ECS or EWE goes
low.
The EWE line transition from high to low also initiates an
internal 150 µsec delay timer to permit page mode operation.
Each subsequent EWE transition from high to low that occurs
before the completion of the 150 µsec time out will restart the
timer from zero. The operation of the timer is the same as a
retriggerable one-shot.
White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520
6
Symbol
Min
Max
Unit
10
ms
Write Cycle Time, TYP = 6ms
tWC
Address Set-up Time
tAS
0
ns
Write Pulse Width (EWE or ECS)
tWP
150
ns
Chip Select Set-up Time
tCS
0
ns
Address Hold Time
tAH
100
ns
Data Hold Time
tDH
10
ns
Chip Select Hold Time
tCSH
0
ns
Data Set-up Time
tDS
100
ns
Output Enable Set-up Time
tOES
10
ns
Output Enable Hold Time
tOEH
10
ns
Write Pulse Width High
tWPH
50
ns
WSE128K16-XXX
FIG. 7 EEPROM WRITE WAVEFORMS
EWE CONTROLLED
t WC
OE
t OEH
t OES
ADDRESS
t AS
ECS 1-2
tCSH
t AH
t CS
EWE 1-2
t WP
t WPH
t DS
t DH
EEPROM
DATA IN
FIG. 8
EEPROM WRITE WAVEFORMS
ECS CONTROLLED
t WC
OE
t OEH
t OES
ADDRESS
t AS
tCSH
t AH
ECS 1-2
t CS
EWE 1-2
t WP
t WPH
t DS
t DH
EEPROM
DATA IN
7
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WSE128K16-XXX
EEPROM READ
The WSE128K16-XXX EEPROM stores data at the memory
location determined by the address pins. When ECS and OE
are low and EWE is high, this data is present on the outputs.
When ECS and OE are high, the outputs are in a high impedance state. This two line control prevents bus contention.
EEPROM AC READ CHARACTERISTICS
(VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C)
Read Cycle Parameter
Symbol
-120
Min
120
-150
Max
Min
150
-300
Max
Min
300
Unit
Max
Read Cycle Time
t RC
Address Access Time
t ACC
120
150
300
ns
Chip Select Access Time
t ACS
120
150
300
ns
Output Hold from Add. Change, OE or ECS
t OH
0
Output Enable to Output Valid
t OE
0
Chip Select or OE to High Z Output
t DF
FIG. 9
0
50
0
0
55
70
0
70
EEPROM READ WAVEFORMS
t RC
ADDRESS
ADDRESS VALID
ECS1-2
t ACS
t OE
OE
t DF
NOTES:
OE may be delayed up to tACS - tOE after the
falling edge of ECS without impact on t OE or by
t ACC - tOE after an address change without
impact on t ACC.
t ACC
EEPROM
DATA
OUTPUT
White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520
HIGH Z
8
ns
t OH
OUTPUT
VALID
ns
85
ns
70
ns
WSE128K16-XXX
EEPROM DATA POLLING
The WSE128K16-XXX offers a data polling feature for the
EEPROM which allows a faster method of writing to the device.
Figure 11 shows the timing diagram for this function. During a
byte or page write cycle, an attempted read of the last byte
written will result in the complement of the written data on D7
(for each chip.) Once the write cycle has been completed, true
data is valid on all outputs and the next cycle may begin. Data
polling may begin at any time during the write cycle.
EEPROM DATA POLLING CHARACTERISTICS
(VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C)
Parameter
Symbol
Min
Data Hold Time
tDH
10
OE Hold Time
tOEH
10
OE To Output Valid
tOE
Write Recovery Time
tWR
FIG. 10
Max
Unit
ns
ns
55
0
ns
ns
EEPROM DATA POLLING WAVEFORMS
EWE1-2
ECS1-2
t OEH
OE
ED7
t DH
t OE
HIGH Z
t WR
ADDRESS
9
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WSE128K16-XXX
EEPROM PAGE WRITE OPERATION
EEPROM PAGE WRITE CHARACTERISTICS
(VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C)
The WSE128K16-XXX has a page write operation that allows one
to 128 bytes of data to be written into the device and consecutively
loads during the internal programming period. Successive bytes
may be loaded in the same manner after the first data byte has
been loaded. An internal timer begins a time out operation at each
write cycle. If another write cycle is completed within 150µs or
less, a new time out period begins. Each write cycle restarts the
delay period. The write cycles can be continued as long as the
interval is less than the time out period.
Page Mode Write Characteristics
The usual procedure is to increment the least significant
address lines from A0 through A6 at each write cycle. In this
manner a page of up to 128 bytes can be loaded in to the
EEPROM in a burst mode before beginning the relatively long
interval programming cycle.
tWC
Address Set-up Time
tAS
0
ns
Address Hold Time (1)
tAH
100
ns
Data Set-up Time
tDS
100
ns
Data Hold Time
t DH
10
ns
Write Pulse Width
tWP
150
ns
Byte Load Cycle Time
tBLC
Write Pulse Width High
tWPH
EEPROM PAGE MODE
WRITE WAVEFORMS
OE
ECS1-2
t BLC
EWE1-2
ADDRESS
t AH
VALID
ADDRESS
t DS
EEPROM
DATA
White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520
VALID DATA
t WC
t DH
BYTE 0
10
150
50
1. Page address must remain valid for duration of write cycle.
t WPH
BYTE 1
10
Max
Write Cycle Time, TYP = 6ms
FIG. 11
t AS
Unit
Min
After the 150µs time out is completed, the EEPROM begins an
internal write cycle. During this cycle the entire page of bytes
will be written at the same time. The internal programming
cycle is the same regardless of the number of bytes accessed.
t WP
Symbol
Parameter
BYTE 2
BYTE 3
BYTE 127
ms
µs
ns
WSE128K16-XXX
FIG. 12
EEPROM SOFTWARE DATA PROTECTION
ENABLE ALGORITHM(1)
LOAD DATA AA
TO
ADDRESS 5555
➞
LOAD DATA 55
TO
ADDRESS 2AAA
➞
WRITES ENABLED(2)
➞
LOAD DATA A0
TO
ADDRESS 5555
➞
LOAD DATA XX
TO
ANY ADDRESS(4)
LOAD LAST BYTE
TO
LAST ADDRESS
ENTER DATA
PROTECT STATE
NOTES:
1. Data Format: ED 7 - ED 0 (Hex);
Address Format: A 16 - A0 (Hex).
2. Write Protect state will be activated at end of write even if no other
data is loaded.
3. Write Protect state will be deactivated at end of write period even if
no other data is loaded.
4. 1 to 128 bytes of data may be loaded.
11
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WSE128K16-XXX
EEPROM SOFTWARE DATA PROTECTION
FIG. 13
A software write protection feature may be enabled or disabled
by the user. When shipped by WEDC, the WSE128K16-XXX has
the feature disabled. Write access to the device is unrestricted.
EEPROM SOFTWARE DATA PROTECTION
DISABLE ALGORITHM(1)
To enable software write protection, the user writes three
access code bytes to three special internal locations. Once
write protection has been enabled, each write to the EEPROM
must use the same three byte write sequence to permit writing.
After setting software data protection, any attempt to write to
the device without the three-byte command sequence will start
the internal write timers. No data will be written to the device,
however, for the duration of tWC. The write protection feature
can be disabled by a six byte write sequence of specific data to
specific locations. Power transitions will not reset the
software write protection.
LOAD DATA AA
TO
ADDRESS 5555
➞
LOAD DATA 55
TO
ADDRESS 2AAA
➞
LOAD DATA 80
TO
ADDRESS 5555
➞
Each 128K byte block of the EEPROM has independent write
protection. One or more blocks may be enabled and the rest
disabled in any combination. The software write protection
guards against inadvertent writes during power transitions, or
unauthorized modification using a PROM programmer.
LOAD DATA AA
TO
ADDRESS 5555
➞
LOAD DATA 55
TO
ADDRESS 2AAA
➞
EEPROM HARDWARE DATA PROTECTION
(3)
➞
EXIT DATA
PROTECT STATE
These features protect against inadvertent writes to the
WSE128K16-XXX. These are included to improve reliability
during normal operation:
LOAD DATA 20
TO
ADDRESS 5555
a) V CC power on delay
As VCC climbs past 3.8V typical the device will wait 5msec
typical before allowing write cycles.
LOAD DATA XX
TO
ANY ADDRESS(4)
➞
LOAD LAST BYTE
TO
LAST ADDRESS
b) V CC sense
While below 3.8V typical write cycles are inhibited.
c) Write inhibiting
Holding OE low and either ECS or EWE high inhibits write
cycles.
d) Noise filter
Pulses of <8ns (typ) on EWE or ECS will not initiate a write
cycle.
NOTES:
1. Data Format: ED 7 - ED 0 (Hex);
Address Format: A 16 - A0 (Hex).
2. Write Protect state will be activated at end of write even if no other
data is loaded.
3. Write Protect state will be deactivated at end of write period even if
no other data is loaded.
4. 1 to 128 bytes of data may be loaded.
White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520
12
WSE128K16-XXX
PACKAGE 400:
66 PIN, PGA TYPE, CERAMIC HEX-IN-LINE PACKAGE, HIP (H1)
27.3 (1.075) ± 0.25 (0.010) SQ
PIN 1 IDENTIFIER
SQUARE PAD
ON BOTTOM
25.4 (1.0) TYP
4.34 (0.171)
MAX
3.81 (0.150)
± 0.13 (0.005)
1.42 (0.056) ± 0.13 (0.005)
0.76 (0.030) ± 0.13 (0.005)
2.54 (0.100)
TYP
15.24 (0.600) TYP
1.27 (0.050) TYP DIA
0.46 (0.018) ± 0.05 (0.002) DIA
25.4 (1.0) TYP
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
13
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WSE128K16-XXX
PACKAGE 509:
68 LEAD, CERAMIC QUAD FLAT PACK, CQFP (G2T)
25.15 (0.990) ± 0.26 (0.010) SQ
4.57 (0.180) MAX
22.36 (0.880) ± 0.26 (0.010) SQ
0.27 (0.011) ± 0.04 (0.002)
0.25 (0.010) REF
Pin 1
R 0.25
(0.010)
24.03 (0.946)
± 0.26 (0.010)
0.19 (0.007)
± 0.06 (0.002)
1° / 7°
1.0 (0.040)
± 0.127 (0.005)
23.87
(0.940) REF
DETAIL A
1.27 (0.050) TYP
SEE DETAIL "A"
0.38 (0.015) ± 0.05 (0.002)
20.3 (0.800) REF
The WEDC 68 lead G2T CQFP
fills the same fit and function as
the JEDEC 68 lead CQFJ or 68
PLCC. But the G2T has the TCE
and lead inspection advantage
of the CQFP form.
0.940"
TYP
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520
14
WSE128K16-XXX
ORDERING INFORMATION
W S E 128K16 - XXX X X X
LEAD FINISH:
Blank = Gold plated leads
A = Solder dip leads
DEVICE GRADE:
M = Military Screened
I = Industrial
C = Commercial
-55°C to +125°C
-40°C to +85°C
0°C to +70°C
PACKAGE TYPE:
H1 = 1.075" sq. Ceramic Hex-In-line Package, HIP (Package 400)
G2T = 22.4mm Ceramic Quad Flat Pack, CQFP (Package 509)
ACCESS TIME (ns)
35 = 35ns SRAM and 150ns EEPROM
42 = 45ns SRAM and 120ns EEPROM
73 = 70ns SRAM and 300ns EEPROM
ORGANIZATION, 128K x 16
EEPROM
SRAM
WHITE ELECTRONIC DESIGNS CORP.
15
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com