White Electronic Designs WE128K32-XXX 128Kx32 EEPROM MODULE, SMD 5962-94585 FEATURES Access Times of 120**, 140, 150, 200, 250, 300ns Page Write Cycle Time: 10ms Max Packaging: Data Polling for End of Write Detection • 66-pin, PGA Type, 27.3mm (1.075") square, Hermetic Ceramic HIP (Package 400) • 68 lead, 22.4mm sq. CQFP (G2T), 4.57mm (0.180") high, (Package 509) Hardware and Software Data Protection TTL Compatible Inputs and Outputs 5 Volt Power Supply Built-in Decoupling Caps and Multiple Ground Pins for Low Noise Operation Weight Organized as 128Kx32; User Configurable as 256Kx16 or 512Kx8 Write Endurance 10,000 Cycles Data Retention Ten Years Minimum (at +25°C) Commercial, Industrial and Military Temperature Ranges Low Power CMOS Automatic Page Write Operation WE128K32-XG2TX - 8 grams typical WE128K32-XH1X - 13 grams typical ** 120ns not available for SMD product *This product is subject to change without notice. FIGURE 1 – PIN CONFIGURATION FOR WE128K32N-XH1X Pin Description Top View 1 12 23 34 45 I/O0-31 A0-16 WE1-4# CS1-4# OE# VCC GND NC 56 I/O8 WE2# I/O15 I/O24 VCC I/O31 I/O9 CS2# I/O14 I/O25 CS4# I/O30 I/O10 GND I/O13 I/O26 WE4# I/O29 A13 I/O11 I/O12 A6 I/O27 I/O28 A14 A10 OE# A7 A3 A0 A15 A11 NC NC A4 A1 A16 A12 WE1# A8 A5 A2 NC VCC I/O7 A9 WE3# I/O23 I/O0 CS1# I/O6 I/O16 CS3# I/O22 I/O1 NC I/O5 I/O17 GND I/O21 I/O4 I/O18 Block Diagram W E 1 # CS 1 # I/O3 I/O2 22 33 I/O20 I/O19 44 55 W E 2 # CS 2 # W E 3 # CS 3 # W E 4 # CS 4 # 128K x 8 128K x 8 128K x 8 OE# A0-16 128K x 8 11 Data Input/Output Address Inputs Write Enable Chip Selects Output Enable Power Supply Ground Not Connected 8 8 8 8 I/O0-7 I/O8-15 I/O16-23 I/O24-31 66 White Electronic Designs Corp. reserves the right to change products or specifications without notice. March 2006 Rev. 10 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WE128K32-XXX FIGURE 3 – PIN CONFIGURATION FOR WE128K32-XG2TX NC A0 A1 A2 A3 A4 A5 CS3# GND CS4# WE1# A6 A7 A8 A9 A10 VCC Top View Pin Description I/O0-31 A0-16 WE1-4# CS1-4# OE# VCC GND NC 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 GND I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 Data Input/Output Address Inputs Write Enable Chip Selects Output Enable Power Supply Ground Not Connected Block Diagram NC NC NC NC WE2# WE3# WE4# OE# CS2# A16 CS1# A15 A14 A13 A12 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 A11 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 VCC I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 GND I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 W E 1 # CS 1 # W E 2 # CS 2 # W E 3 # CS 3 # W E 4 # CS 4 # 128K x 8 128K x 8 128K x 8 128K x 8 OE# A0-16 8 8 8 8 I/O0-7 I/O8-15 I/O16-23 I/O24-31 The WEDC 68 lead CQFP fills the same fit and function as the JEDEC 68 lead CQFJ or 68 PLCC. But it has the TCE and lead inspection advantage of the CQFP form. White Electronic Designs Corp. reserves the right to change products or specifications without notice. March 2006 Rev. 10 2 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WE128K32-XXX ABSOLUTE MAXIMUM RATINGS Parameter Operating Temperature Storage Temperature Signal Voltage Relative to GND Voltage on OE# and A9 Symbol TA TSTG VG -55 to +125 -65 to +150 -0.6 to + 6.25 -0.6 to +13.5 TRUTH TABLE Unit °C °C V V CS# H L L X X X NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Symbol VCC VIH VIL TA TA Min 4.5 2.0 -0.5 -55 -40 Max 5.5 VCC + 0.3 +0.8 +125 +85 WE# X H L X H X Mode Standby Read Write Out Disable Write Inhibit Data I/O High Z Data Out Data In High Z/Data Out CAPACITANCE TA = +25°C Parameter OE# capacitance WE1-4# capacitance HIP (PGA) CQFP G2T CS1-4# capacitance Data I/O capacitance Address input capacitance RECOMMENDED OPERATING CONDITIONS Parameter Supply Voltage Input High Voltage Input Low Voltage Operating Temp. (Mil.) Operating Temp. (Ind.) OE# X L H H X L Unit V V V °C °C Symbol COE CWE CCS CI/O CAD Conditions Max Unit VIN = 0 V, f = 1.0 MHz 50 pF pF VIN = 0 V, f = 1.0 MHz 20 20 VIN = 0 V, f = 1.0 MHz 20 pF VI/O = 0 V, f = 1.0 MHz 20 pF VIN = 0 V, f = 1.0 MHz 50 pF This parameter is guaranteed by design but not tested. DC CHARACTERISTICS VCC = 5.0V, GND = 0V, -55°C ≤ TA ≤ +125°C Parameter Input Leakage Current Output Leakage Current Operating Supply Current (x32) Standby Current Output Low Voltage Output High Voltage Symbol ILI ILOx32 ICCx32 ISB VOL VOH Conditions VCC = 5.5, VIN = GND to VCC CS# = VIH, OE# = VIH, VOUT = GND to VCC CS# = VIL, OE# = VIH, f = 5MHz CS# = VIH, OE# = VIH, f = 5MHz IOL = 2.1mA, VCC = 4.5V IOH = -400µA, VCC = 4.5V Min Max 10 10 250 2.5 0.45 2.4 Unit µA µA mA mA V V NOTE: DC test conditions: VIH = VCC -0.3V, VIL = 0.3V FIGURE 3 AC Test Circuit AC TEST CONDITIONS IOL Parameter Input Pulse Levels Input Rise and Fall Input and Output Reference Level Output Timing Reference Level Current Source Vz ~ ~ 1.5V Bipolar Supply D.U.T Ceff = 50 pf Current Source Typ VIL = 0, VIH = 3.0 5 1.5 1.5 Unit V ns V V Notes: VZ is programmable from -2V to +7V. IOL & IOH programmable from 0 to 16mA. Tester Impedance Z0 = 75Ω. VZ is typically the midpoint of VOH and VOL. IOL & IOH are adjusted to simulate a typical resistive load circuit. ATE tester includes jig capacitance. IOH White Electronic Designs Corp. reserves the right to change products or specifications without notice. March 2006 Rev. 10 3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WE128K32-XXX AC WRITE CHARACTERISTICS WRITE VCC = 5.0V, GND = 0V, -55°C ≤ TA ≤ +125°C A write cycle is initiated when OE# is high and a low pulse is on WE# or CS# with CS# or WE# low. The address is latched on the falling edge of CS# or WE# whichever occurs last. The data is latched by the rising edge of CS# or WE#, whichever occurs first. A byte write operation will automatically continue to completion. Write Cycle Parameter write cycle timing Figures 5 and 6 show the write cycle timing relationships. A write cycle begins with address application, write enable and chip select. Chip select is accomplished by placing the CS# line low. Write enable consists of setting the WE# line low. The write cycle begins when the last of either CS# or WE# goes low. Symbol Min Max Unit 10 ms Write Cycle Time, TYP = 6ms tWC Address Set-up Time tAS 0 ns ns Write Pulse Width (WE# or CS#) tWP 100 Chip Select Set-up Time tCS 0 ns Address Hold Time tAH 100 ns Data Hold Time tDH 10 ns Chip Select Hold Time tCSH 0 ns Data Set-up Time tDS 50 ns Output Enable Set-up Time tOES 0 ns Output Enable Hold Time tOEH 0 ns Write Pulse Width High tWPH 50 ns The WE# line transition from high to low also initiates an internal 150 µsec delay timer to permit page mode operation. Each subsequent WE# transition from high to low that occurs before the completion of the 150 µsec time out will restart the timer from zero. The operation of the timer is the same as a retriggerable one-shot. White Electronic Designs Corp. reserves the right to change products or specifications without notice. March 2006 Rev. 10 4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WE128K32-XXX FIGURE 5 – WRITE WAVEFORMS WE# CONTROLLED t WC OE# t OEH t OES ADDRESS t AS CS1-4# tCSH t AH t CS WE1-4# t WP t WPH t DS t DH DATA IN FIGURE 6 – WRITE WAVEFORMS CS# CONTROLLED t WC OE# t OEH t OES ADDRESS t AS tCSH t AH WE1 - 4# t CS CS1 - 4# t WP t WPH t DS t DH DATA IN White Electronic Designs Corp. reserves the right to change products or specifications without notice. March 2006 Rev. 10 5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WE128K32-XXX READ The WE128K32-XXX stores data at the memory location determined by the address pins. When CS# and OE# are low and WE# is high, this data is present on the outputs. When CS# and OE# are high, the outputs are in a high impedance state. This two line control prevents bus contention. AC READ CHARACTERISTICS VCC = 5.0V, GND = 0V, -55°C ≤ TA ≤ +125°C Read Cycle Parameter Symbol Read Cycle Time Address Access Time Chip Select Access Time Output Hold from Add. Change, OE# or CS# Output Enable to Output Valid Chip Select or OE# to High Z Output tRC tACC tACS tOH tOE tDF -120 Min 120 -140 Max Min 140 120 120 0 0 50 60 -150 Max Min 150 140 140 0 0 55 70 -200 Max Min 200 150 150 0 0 55 70 -250 Max Min 250 200 200 0 0 55 70 -300 Max Min 300 250 250 0 0 85 70 Max 300 300 0 0 85 70 Unit ns ns ns ns ns ns FIGURE 7 – READ WAVEFORMS t RC ADDRESS ADDRESS VALID CS# t ACS t OE OE# t DF t ACC OUTPUT t OH HIGH Z OUTPUT VALID Notes: OE# may be delayed up to tACS - tOE after the falling edge of CS# without impact on tOE or by tACC - tOE after an address change without impact on tACC. White Electronic Designs Corp. reserves the right to change products or specifications without notice. March 2006 Rev. 10 6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WE128K32-XXX DATA POLLING CHARACTERISTICS DATA POLLING (VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C) The WE128K32-XXX offers a data polling feature which allows a faster method of writing to the device. Figure 8 shows the timing diagram for this function. During a byte or page write cycle, an attempted read of the last byte written will result in the complement of the written data on D7 (for each chip.) Once the write cycle has been completed, true data is valid on all outputs and the next cycle may begin. Data polling may begin at any time during the write cycle. Parameter Data Hold Time OE# Hold Time OE# To Output Valid Write Recovery Time Symbol tDH tOEH tOE tWR Min 10 10 Max 55 0 Unit ns ns ns ns FIGURE 8 – DATA POLLING WAVEFORMS WE1-4# CS1-4# t OEH OE# I/O7 t OE t DH HIGH Z t WR ADDRESS TOGGLE BUT CHARACTERISTICS(1) TOGGLE BIT: In addition to DATA# Polling another method for determining the end of a write cycle is provided. During the write operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the write has completed, I/O6 will stop toggling and valid data will be read. Reading the toggle bit may begin at any time during the write cycle. Symbol Parameter Min Max Units tDH Data Hold Time 10 ns tOEH OE# Hold Time 10 ns tOE OE# to Output Delay tOEHP OE# High Pulse tWR Write Recovery Time ns 150 ns 0 ns WE# CS# tOEH OE# tDH tOE I/O6 (2) HIGH Z tWR NOTE: 1. Toggling either OE# or CS# or both OE# and CS# will operate toggle bit. 2. Beginning and ending state of I/O6 will vary 3. Any address location may be used but the address should not vary. White Electronic Designs Corp. reserves the right to change products or specifications without notice. March 2006 Rev. 10 7 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WE128K32-XXX PAGE WRITE CHARACTERISTICS PAGE WRITE OPERATION (VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C) The WE128K32-XXX has a page write operation that allows one to 128 bytes of data to be written into the device and consecutively loads during the internal programming period. Successive bytes may be loaded in the same manner after the first data byte has been loaded. An internal timer begins a time out operation at each write cycle. If another write cycle is completed within 150µs or less, a new time out period begins. Each write cycle restarts the delay period. The write cycles can be continued as long as the interval is less than the time out period. Page Mode Write Characteristics Parameter Write Cycle Time, TYP = 6ms Address Set-up Time Address Hold Time (1) Data Set-up Time Data Hold Time Write Pulse Width Byte Load Cycle Time Write Pulse Width High The usual procedure is to increment the least significant address lines from A0 through A6 at each write cycle. In this manner a page of up to 128 bytes can be loaded in to the EEPROM in a burst mode before beginning the relatively long interval programming cycle. Symbol tWC tAS tAH tDS tDH tWP tBLC tWPH Min Max 10 0 100 50 10 100 150 50 Unit ms ns ns ns ns ns µs ns 1. Page address must remain valid for duration of write cycle. After the 150µs time out is completed, the EEPROM begins an internal write cycle. During this cycle the entire page of bytes will be written at the same time. The internal programming cycle is the same regardless of the number of bytes accessed. FIGURE 9 – PAGE MODE WRITE WAVEFORMS OE# CS# WE# ADDRESS DATA White Electronic Designs Corp. reserves the right to change products or specifications without notice. March 2006 Rev. 10 8 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WE128K32-XXX FIGURE 10 – SOFTWARE BLOCK DATA PROTECTION ENABLE ALGORITHM(1) LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA A0 TO ADDRESS 5555 WRITES ENABLED(2) LOAD DATA XX TO ANY ADDRESS(4) LOAD LAST BYTE TO LAST ADDRESS ENTER DATA PROTECT STATE NOTES: 1. Data Format: D7 - D0 (Hex); Address Format: A16 - A0 (Hex). 2. Write Protect state will be activated at end of write even if no other data is loaded. 3. Write Protect state will be deactivated at end of write period even if no other data is loaded. 4. 1 to 128 bytes of data to be loaded. White Electronic Designs Corp. reserves the right to change products or specifications without notice. March 2006 Rev. 10 9 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs FIGURE 10 – SOFTWARE BLOCK DATA PROTECTION DISABLE ALGORITHM(1) SOFTWARE DATA PROTECTION A software write protection feature may be enabled or disabled by the user. When shipped by White Microelectronics, the WE-128K32-XXX has the feature disabled. Write access to the device is unrestricted. To enable software write protection, the user writes three access code bytes to three special internal locations. Once write protection has been enabled, each write to the EEPROM must use the same three byte write sequence to permit writing. After setting software data protection, any attempt to write to the device without the three-byte command sequence will start the internal write timers. No data will be written to the device, however, for the duration of tWC. The write protection feature can be disabled by a six byte write sequence of specific data to specific locations. Power transitions will not reset the software write protection. LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 80 TO ADDRESS 5555 LOAD DATA AA TO ADDRESS 5555 Each 128K byte block of the EEPROM has independent write protection. One or more blocks may be enabled and the rest disabled in any combination. The software write protection guards against inadvertent writes during power transitions, or unauthorized modification using a PROM programmer. LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 20 TO ADDRESS 5555 LOAD DATA XX TO ANY ADDRESS(4) WE128K32-XXX EXIT DATA HARDWARE DATA PROTECTION PROTECT STATE(3) These features protect against inadvertent writes to the WE128K32-XXX. These are included to improve reliability during normal operation: LOAD LAST BYTE TO LAST ADDRESS a) VCC power on delay As VCC climbs past 3.8V typical the device will wait 5msec typical before allowing write cycles. b) VCC sense c) Write inhibiting While below 3.8V typical write cycles are inhibited. Holding OE# low and either CS# or WE# high inhibits write cycles. d) Noise filter Pulses of <8ns (typ) on WE# or CS# will not initiate a write cycle. NOTES: 1. Data Format: D7 - D0 (Hex); Address Format: A16 - A0 (Hex). 2. Write Protect state will be activated at end of write even if no other data is loaded. 3. Write Protect state will be deactivated at end of write period even if no other data is loaded. 4. 1 to 128 bytes of data may be loaded. White Electronic Designs Corp. reserves the right to change products or specifications without notice. March 2006 Rev. 10 10 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WE128K32-XXX PACKAGE 400: 66 PIN, PGA TYPE, CERAMIC HEX-IN-LINE PACKAGE, HIP (H1) 4.60 (0.181) MAX ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES White Electronic Designs Corp. reserves the right to change products or specifications without notice. March 2006 Rev. 10 11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WE128K32-XXX PACKAGE 509: 68 LEAD, CERAMIC QUAD FLAT PACK, CQFP (G2T) ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES White Electronic Designs Corp. reserves the right to change products or specifications without notice. March 2006 Rev. 10 12 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WE128K32-XXX FIGURE 12 – ALTERNATE PIN CONFIGURATION FOR WE128K32NP-XH1X Top View 1 12 23 Pin Description 34 45 I/O8 WE2# I/O15 I/O24 VCC I/O31 I/O9 CS2# I/O14 I/O25 CS4# I/O30 I/O10 GND I/O13 I/O26 WE4# I/O29 A14 I/O11 I/O12 A7 I/O27 I/O28 A16 A10 OE# A12 A4 A1 A11 A9 NC NC A5 A2 A0 A15 WE1# A13 A5 A3 NC VCC I/O7 A8 WE3# I/O23 I/O0 CS1# I/O6 I/O16 CS3# I/O22 I/O1 NC I/O5 I/O17 GND I/O21 I/O2 I/O3 I/O4 I/O18 I/O19 I/O20 11 22 33 44 55 I/O0-31 A0-16 WE1-4# CS1-4# OE# VCC GND NC 56 Data Inputs/Outputs Address Inputs Write Enables Chip Selects Output Enable Power Supply Ground Not Connected Block Diagram W E 1 # CS 1 # W E 2 # CS 2 # W E 3 # CS 3 # W E 4 # CS 4 # 128K x 8 128K x 8 128K x 8 128K x 8 OE# A0-16 66 8 8 8 8 I/O0-7 I/O8-15 I/O16-23 I/O24-31 ORDERING INFORMATION W E 128K32 X - XXX X X X LEAD FINISH: Blank = Gold plated leads A = Solder dip leads DEVICE GRADE: Q = Compliant M = Military Screened I = Industrial C = Commercial -55°C to +125°C -40°C to +85°C 0°C to +70°C PACKAGE TYPE: H1 = 1.075" sq. Ceramic Hex In-line Package, HIP (Package 400*) G2T = 22.4mm Ceramic Quad Flat Pack, Low Profile CQFP (Package 509) ACCESS TIME (ns) IMPROVEMENT MARK N = No Connect at pins 8, 21, 28, and 39 in HIP for upgrade P = Alternate Pin Configuration for HIP package ORGANIZATION 128K x 32 User Configurable as 256K x 16 or 512K x 8 EEPROM WHITE ELECTRONIC DESIGNS CORP. White Electronic Designs Corp. reserves the right to change products or specifications without notice. March 2006 Rev. 10 13 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WE128K32-XXX DEVICE TYPE SPEED PACKAGE SMD NO. 128K x 32 EEPROM Module 300ns 66 pin HIP (H1) 5962-94585 01H5X 128K x 32 EEPROM Module 250ns 66 pin HIP (H1) 5962-94585 02H5X 128K x 32 EEPROM Module 200ns 66 pin HIP (H1) 5962-94585 03H5X 128K x 32 EEPROM Module 150ns 66 pin HIP (H1) 5962-94585 04H5X 128K x 32 EEPROM Module 140ns 66 pin HIP (H1) 5962-94585 05H5X 128K x 32 EEPROM Module 300ns 66 pin HIP (H1, P type pinout) 5962-94585 01H6X 128K x 32 EEPROM Module 250ns 66 pin HIP (H1, P type pinout) 5962-94585 02H6X 128K x 32 EEPROM Module 200ns 66 pin HIP (H1, P type pinout) 5962-94585 03H6X 128K x 32 EEPROM Module 150ns 66 pin HIP (H1, P type pinout) 5962-94585 04H6X 128K x 32 EEPROM Module 140ns 66 pin HIP (H1, P type pinout) 5962-94585 05H6X 128K x 32 EEPROM Module 300ns 68 lead CQFP/J (G2T) 5962-94585 01HMX 128K x 32 EEPROM Module 250ns 68 lead CQFP/J (G2T) 5962-94585 02HMX 128K x 32 EEPROM Module 200ns 68 lead CQFP/J (G2T) 5962-94585 03HMX 128K x 32 EEPROM Module 150ns 68 lead CQFP/J (G2T) 5962-94585 04HMX 128K x 32 EEPROM Module 140ns 68 lead CQFP/J (G2T) 5962-94585 05HMX White Electronic Designs Corp. reserves the right to change products or specifications without notice. March 2006 Rev. 10 14 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com