Revised March 2000 DM96LS02 Dual Retriggerable Resettable Monostable Multivibrator General Description Features The DM96LS02 is a dual retriggerable and resettable monostable multivibrator. The one-shot provides exceptionally wide delay range, pulse width stability, predictable accuracy and immunity to noise. The pulse width is set by an external resistor and capacitor. Resistor values up to 1.0 MΩ reduce required capacitor values. Hysteresis is provided on both trigger inputs of the DM96LS02 for increased noise immunity. ■ Required timing capacitance reduced by factors of 10 to 100 over conventional designs ■ Broad timing resistor range—1.0 kΩ to 2.0 MΩ ■ Output Pulse Width is variable over a 2000:1 range by resistor control ■ Propagation delay of 35 ns ■ 0.3V hysteresis on trigger inputs ■ Output pulse width independent of duty cycle ■ 35 ns to ∞ output pulse width range Ordering Code: Order Number Package Number Package Description DM96LS02M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow DM96LS02N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Logic Symbol VCC = Pin 16 GND = Pin 8 Pin Descriptions Pin Names I0 Description Trigger Input (Active Falling Edge) I0 Schmitt Trigger Input (Active Falling Edge) I1 Schmitt Trigger Input (Active Rising Edge) CD Direct Clear Input (Active LOW) Q True Pulse Output Q Complementary Pulse Output © 2000 Fairchild Semiconductor Corporation DS009816 www.fairchildsemi.com DM96LS02 Dual Retriggerable Resettable Monostable Multivibrator October 1988 DM96LS02 Functional Description during the timing cycle will retrigger the circuit and result in Q remaining HIGH. The output pulse may be terminated (Q to the LOW state) at any time by setting the Direct Clear input LOW. Retriggering may be inhibited by tying the Q output to I0 or the Q output to I1. Differential sensing techniques are used to obtain excellent stability over temperature and power supply variations and a feedback Darlington capacitor discharge circuit minimizes pulse width variation from unit to unit. Schottky TTL output stages provide high switching speeds and output compatibility with all TTL logic families. The DM96LS02 dual retriggerable resettable monostable multivibrator has two DC coupled trigger inputs per function, one active LOW (I0) and one active HIGH (I1). The I1 input and I0 input of the DM96LS02 utilize an internal Schmitt trigger with hysteresis of 0.3V to provide increased noise immunity. The use of active HIGH and LOW inputs allows either rising or falling edge triggering and optional non-retriggerable operation. The inputs are DC coupled making triggering independent of input transition times. When input conditions for triggering are met, the Q output goes HIGH and the external capacitor is rapidly discharged and then allowed to recharge. An input trigger which occurs Logic Diagram Operation Notes TIMING TRIGGERING 1. An external resistor (RX) and an external capacitor (CX) are required as shown in the Logic Diagram. The value of RX may vary from 1.0 kΩ to 1.0 MΩ. 1. The minimum negative pulse width into I0 is 8.0 ns; the minimum positive pulse width into I1 is 12 ns. 2. Input signals to the DM96LS02 exhibiting slow or noisy transitions can use either trigger as both are Schmitt triggers. 2. The value of CX may vary from 0 to any necessary value available. If, however, the capacitor has significant leakage relative to VCC/RX the timing equations may not represent the pulse width obtained. 3. The output pulse width tW for RX ≥ 10 kΩ and CX ≥ 1000 pF is determined as follows: tW = 0.43 RXCX 3. When non-retriggerable operation is required, i.e., when input triggers are to be ignored during quasi-stable state, input latching is used to inhibit retriggering. 4. An overriding active LOW level direct clear is provided on each multivibrator. By applying a LOW to the clear, any timing cycle can be terminated or any new cycle inhibited until the LOW reset input is removed. Trigger inputs will not produce spikes in the output when the reset is held LOW. A LOW-to-HIGH transition on CD will not trigger the DM96LS02. If the CD input goes HIGH coincident with a trigger transition, the circuit will respond to the trigger. Where RX is in kΩ, CX is in pF, t is in ns or RX is in kΩ, CX is in µF, t is in ms. 4. The output pulse width for RX < 10 kΩ or CX < 1000 pF should be determined from pulse width versus CX or RX graphs. 5. To obtain variable pulse width by remote trimming, the following circuit is recommended: 6. Under any operating condition, CX and RX (Min) must be kept as close to the circuit as possible to minimize stray capacitance and reduce noise pickup. 7. VCC and ground wiring should conform to good high frequency standards so that switching transients on VCC and ground leads do not cause interaction between one shots. Use of a 0.01 µF to 0.1 µF bypass capacitor between VCC and ground located near the circuit is recommended. www.fairchildsemi.com 2 Triggering Truth Table Pin Numbers 5(11) 4(12) Operation 3(13) H→L L H Trigger H L→H H Trigger X X L Reset H = HIGH Voltage Level ≥ V IH L = LOW Voltage Level ≤ VIL X = Immaterial (either H or L) H→L = HIGH-to-LOW Voltage Level Transition L→H = LOW-to-HIGH Voltage Level Transition Typical Performance Characteristics Output tW vs. RX and CX I1 Delay Time vs. TA I0 Delay Time vs. TA Output tW vs. TA 3 www.fairchildsemi.com DM96LS02 Operation Notes (continued) DM96LS02 Typical Performance Characteristics (continued) Normalized ∆tW vs. TA Pulse Width vs. RX CX Input Pulse f ≅ 100 kHz Amp ≅ 3.0V Width ≅ 100 ns tr = tf ≤ 5 ns FIGURE 1. www.fairchildsemi.com 4 Supply Voltage Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. 7V Input Voltage 7V 0°C to +70°C Operating Free Air Temperature Range −65°C to +150°C Storage Temperature Range Recommended Operating Conditions Symbol Parameter Min Nom Max 4.75 5 5.25 Units VCC Supply Voltage VIH HIGH Level Input Voltage V VIL LOW Level Input Voltage 0.8 V IOH HIGH Level Output Current −0.4 mA IOL LOW Level Output Current 8 mA TA Free Air Operating Temperature 70 °C 2 V 0 Electrical Characteristics Over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Conditions VI Input Clamp Voltage VCC = Min, II = −18 mA VOH HIGH Level VCC = Min, IOH = Max, Output Voltage VIL = Max VOL LOW Level VCC = Min, IOL = Max, Output Voltage VIH = Min Min Typ (Note 2) Max −1.5 2.7 IOL = 4 mA, VCC = Min 3.4 Units V V 0.35 0.5 0.25 0.4 V Input Current @ Max VCC = Max, VI = 7V Input Voltage VI = 10V IIH HIGH Level Input Current VCC = Max, VI = 2.7V 20 µA IIL LOW Level Input Current VCC = Max, VI = 0.4V −0.4 mA II IOS Short Circuit Output Current VCC = Max (Note 3) ICC Supply Current VCC = Max VT+ Positive-Going Threshold 0.1 −20 Voltage, I0, I1 VT− Negative-Going Threshold 0.8 Voltage, I0, I1 mA −100 mA 36 mA 2.0 V V Note 2: All typicals are at VCC = 5V, TA = 25°C. Note 3: Not more than one output should be shorted at a time, and the duration should not exceed one second. 5 www.fairchildsemi.com DM96LS02 Absolute Maximum Ratings(Note 1) DM96LS02 Switching Characteristics VCC = +5.0V, TA = +25°C Symbol tPLH CL = 15 pF Parameter Min Propagation Delay I0 to Q tPHL Propagation Delay I0 to Q tPLH Propagation Delay I1 to Q tPHL Propagation Delay I1 to Q tPHL Propagation Delay CD to Q tPLH Propagation Delay CD to Q Max Units 55 ns 50 ns 60 ns 55 ns 30 ns 35 ns tW(L) I0 Pulse Width LOW 15 tW(H) I1 Pulse With HIGH 30 ns tW(L) CD Pulse Width LOW 22 ns tW(H) Minimum Q Pulse Width HIGH 25 55 ns tW Q Pulse Width 4.1 4.5 µs RX Timing Resistor Range (Note 4) 1 1000 kΩ t Change in Q Pulse 1.0 % Width over Temperature t ns Change in Q Pulse 0.8 Width over VCC Range 1.5 Note 4: Applies only over commercial VCC and TA range for 96S02. www.fairchildsemi.com 6 % DM96LS02 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A 7 www.fairchildsemi.com DM96LS02 Dual Retriggerable Resettable Monostable Multivibrator Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 8