LTC4251/LTC4251-1/ LTC4251-2 Negative Voltage Hot Swap Controllers in SOT-23 U DESCRIPTIO FEATURES ■ ■ ■ ■ ■ ■ ■ The LTC®4251/LTC4251-1/LTC4251-2 negative voltage Hot SwapTM controllers allow a board to be safely inserted and removed from a live backplane. Output current is controlled by three stages of current limiting: a timed circuit breaker, active current limiting and a fast feedforward path that limits peak current under worst-case catastrophic fault conditions. Allows Safe Board Insertion and Removal from a Live –48V Backplane Floating Topology Permits Very High Voltage Operation Programmable Analog Current Limit with Circuit Breaker Timer Fast Response Time Limits Peak Fault Current Programmable Timer Programmable Undervoltage/Overvoltage Protection Low Profile (1mm) ThinSOTTM Package Programmable undervoltage and overvoltage detectors disconnect the load whenever the input supply exceeds the desired operating range. The supply input is shunt regulated, allowing safe operation with very high supply voltages. A multifunction timer delays initial start-up and controls the circuit breaker’s response time. U APPLICATIO S ■ ■ ■ ■ ■ ■ ■ Hot Board Insertion Electronic Circuit Breaker –48V Distributed Power Systems Negative Power Supply Control Central Office Switching Programmable Current Limiting Circuit High Availability Servers Disk Arrays The LTC4251 UV/OV thresholds are designed to match the standard telecom operating range of – 43V to – 75V. The LTC4251-1 UV/OV thresholds extend the operating range to encompass – 36V to – 72V. The LTC4251-2 implements a UV threshold of – 43V only. All parts are available in the 6-Pin SOT-23 package. , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. ThinSOT and Hot Swap are trademarks of Linear Technology Corporation. U ■ TYPICAL APPLICATIO –48V, 2.5A Hot Swap Controller Start-Up Behavior GND RIN* 10k 500mW GND (SHORT PIN) R1 402k 1% 3 VIN 5 UV/OV C1 10nF R2 32.4k 1% GATE 6 CL 100µF + LOAD VOUT CIN 1µF Q1 IRF530S LTC4251 4 TIMER SENSE VEE CT 150nF 2 1 *TWO 0.25W RESISTORS IN SERIES FOR RIN ON THE PCB ARE RECOMMENDED. SENSE 2.5A/DIV 3 1 RS 0.02Ω RC 10Ω CC 18nF VOUT 20V/DIV 2 4 –48V GATE 5V/DIV 425112 TA01 1ms/DIV 425112 TA02 425112fa 1 LTC4251/LTC4251-1/ LTC4251-2 U W W W ABSOLUTE AXI U RATI GS U W U PACKAGE/ORDER I FOR ATIO (Note 1), All Voltages are Referred to VEE TOP VIEW Current into VIN (100µs Pulse) ........................... 100mA Minimum VIN Voltage ........................................... – 0.3V Gate, UV/OV, Timer Voltage .......................– 0.3V to 16V Sense Voltage ............................................– 0.6V to 16V Current Out of Sense Pin (20µs Pulse) ............. –200mA Maximum Junction Temperature .......................... 125°C Operating Temperature Range LTC4251C/LTC4251-1C/LTC4251-2C ...... 0°C to 70°C LTC4251I/LTC4251-1I/LTC4251-2I .... – 40°C to 85°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C 6 GATE SENSE 1 VEE 2 5 UV/OV* VIN 3 4 TIMER S6 PACKAGE 6-LEAD PLASTIC SOT-23 *UV FOR LTC4251-2 TJMAX = 125°C, θJA = 256°C/W ORDER PART NUMBER S6 PART MARKING LTC4251CS6 LTC4251IS6 LTC42511CS6 LTC4251-1IS6 LTC42512CS6 LTC4251-2IS6 LTUQ LTUR LTQU LTQV LTK6 LTAAZ Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 2, 3) SYMBOL PARAMETER CONDITIONS VZ VIN to VEE Zener Voltage IIN = 2mA rZ VIN to VEE Zener Dynamic Impedance IIN = 2mA to 30mA IIN VIN Supply Current UV/OV = 4V, VIN = (VZ – 0.3V) ● 0.8 2 VLKO VIN Undervoltage Lockout Coming out of UVLO (Rising VIN) ● 9.2 11.5 VLKH VIN Undervoltage Lockout Hysteresis VCB Circuit Breaker Current Limit Voltage VCB = (VSENSE – VEE) ● 40 50 60 mV VACL Analog Current Limit Voltage VACL = (VSENSE – VEE) ● 80 100 120 mV VFCL Fast Current Limit Voltage VFCL = (VSENSE – VEE) ● 150 200 300 mV IGATE GATE Pin Output Current UV/OV = 4V, VSENSE = VEE, VGATE = 0V (Sourcing) UV/OV = 4V, VSENSE – VEE = 0.15V, VGATE = 3V (Sinking) UV/OV = 4V, VSENSE – VEE = 0.3V, VGATE = 1V (Sinking) ● 40 58 17 190 80 µA mA mA VGATE External MOSFET Gate Drive VGATE – VEE, IIN = 2mA ● 10 12 VZ V VGATEL Gate Low Threshold (Before Gate Ramp-Up) VUVHI UV Threshold High LTC4251/LTC4251-2 LTC4251-1 ● ● 3.075 2.300 3.225 2.420 3.375 2.540 V V VUVLO UV Threshold Low LTC4251/LTC4251-2 LTC4251-1 ● ● 2.775 2.050 2.925 2.160 3.075 2.270 V V VUVHST UV Hysteresis LTC4251/LTC4251-2 LTC4251-1 VOVHI OV Threshold High LTC4251 LTC4251-1 ● MIN TYP MAX UNITS 11.5 13 14.5 V Ω 5 1 V 0.30 0.26 5.85 5.86 6.15 6.17 V V 0.5 ● ● mA V V 6.45 6.48 V V 425112fa 2 LTC4251/LTC4251-1/ LTC4251-2 ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 2, 3) SYMBOL PARAMETER CONDITIONS VOVLO OV Threshold Low LTC4251 LTC4251-1 VOVHST OV Hysteresis LTC4251 LTC4251-1 ISENSE SENSE Input Current UV/OV = 4V, VSENSE = 50mV ● IINP UV/OV Input Current UV/OV = 4V ● VTMRH Timer Voltage High Threshold 4 V VTMRL Timer Voltage Low Threshold 1 V ITMR Timer Current tPLLUG UV Low to GATE Low tPHLOG OV High to GATE Low ● ● MAX UNITS 5.85 6.21 V V –30 –15 µA ±0.1 ±1 µA µA mA µA µA 0.7 µs 1 µs UV/OV = 4V refers to UV = 4V for the LTC4251-2. IIN vs VIN 10 1000 VIN = (VZ – 0.3V) V V Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to VEE unless otherwise specified. Note 3: UV/OV = 4V refers to UV = 4V for the LTC4251-2. U W IIN vs Temperature 0.60 0.26 5.8 28 230 5.8 LTC4251/LTC4251-1 TYPICAL PERFOR A CE CHARACTERISTICS 1800 TYP 5.55 5.91 Timer On (Initial Cycle, Sourcing), VTMR = 2V Timer Off (Initial Cycle, Sinking), VTMR = 2V Timer On (Circuit Breaker, Sourcing), VTMR = 2V Timer Off (Cooling Cycle, Sinking), VTMR = 2V Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. 2000 MIN 5.25 5.61 TA = –40°C rZ vs Temperature IIN = 2mA 9 1600 TA = 25°C 1000 800 10 TA = 85°C 6 5 600 TA = 125°C 1 400 4 3 200 0 –55 –35 –15 7 rZ (Ω) 1200 IIN (mA) IIN (µA) 8 100 1400 5 25 45 65 85 105 125 TEMPERATURE (°C) 425112 G01 0.1 0 2 4 6 8 10 12 14 16 18 20 22 VIN (V) 425112 G02 2 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 425112 G03 425112fa 3 LTC4251/LTC4251-1/ LTC4251-2 U W TYPICAL PERFOR A CE CHARACTERISTICS Undervoltage Lockout VLKO vs Temperature VZ vs Temperature 12.0 1.6 11.5 1.4 11.0 1.2 10.5 1 Undervoltage Lockout Hysteresis VLKH vs Temperature IIN = 2mA 14.0 VZ (V) VLKO (V) 13.5 13.0 VLKH 14.5 UV/OV = 4V refers to UV = 4V for the LTC4251-2. 10.0 0.8 9.5 0.6 9.0 0.4 8.5 0.2 12.5 12.0 –55 –35 –15 8.0 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 0 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 425112 G05 425112 G04 Circuit Breaker Current Limit Voltage VCB vs Temperature 425112 G06 Analog Current Limit Voltage VACL vs Temperature 60 120 58 115 56 Fast Current Limit Voltage VFCL vs Temperature 300 275 110 250 50 48 VFCL (mV) 105 52 VACL (V) VCB (mV) 54 100 95 46 225 200 90 44 175 85 42 80 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 150 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 425112 G08 425112 G07 IGATE (Source) vs Temperature IGATE (ACL, Sink) vs Temperature 30 70 UV/0V = 4V TIMER = 0V 65 VSENSE = VEE VGATE = 0V 25 IGATE (FCL, Sink) vs Temperature 400 UV/0V = 4V TIMER = 0V VSENSE – VEE = 0.15V VGATE = 3V 350 300 20 IGATE (mA) 60 55 15 50 10 45 5 5 25 45 65 85 105 125 TEMPERATURE (°C) 425112 G09 IGATE (mA) 40 –55 –35 –15 IGATE (µA) 5 25 45 65 85 105 125 TEMPERATURE (°C) UV/0V = 4V TIMER = 0V VSENSE – VEE = 0.3V VGATE = 1V 250 200 150 100 40 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 425112 G10 0 –55 –35 –15 50 5 25 45 65 85 105 125 TEMPERATURE (°C) 425112 G11 0 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 425112 G12 425112fa 4 LTC4251/LTC4251-1/ LTC4251-2 U W TYPICAL PERFOR A CE CHARACTERISTICS VGATE vs Temperature 14.0 13.5 VGATEL vs Temperature 0.8 UV/0V = 4V VTMR = 0V VSENSE = VEE 0.7 0.6 VGATEL (V) VGATE (V) 13.0 12.5 12.0 11.5 UV Threshold vs Temperature 3.375 UV/0V = 4V, VTMR = 0V, GATE THRESHOLD BEFORE RAMP-UP LTC4251/LTC4251-2 3.275 UV THRESHOLD (V) 14.5 0.5 0.4 0.3 10.0 –55 –35 –15 0 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 3.075 2.975 VUVL 2.775 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 425112 G13 UV Threshold vs Temperature 425112 G15 OV Threshold vs Temperature OV Threshold vs Temperature 6.51 6.45 LTC4251-1 LTC4251 6.25 VOVH VUVHI OV THRESHOLD (V) 2.40 2.35 2.30 2.25 2.20 5.85 5.65 VOVL 5.25 –55 –35 –15 ISENSE vs (VSENSE – VEE) TIMER Threshold vs Temperature 5.0 0.01 4.5 4.0 –ISENSE (mA) –16 –20 –22 1.0 10 –24 –30 –55 –35 –15 UV/0V = 4V TIMER = 0V GATE = HIGH VSENSE – VEE = 50mV 5 25 45 65 85 105 125 TEMPERATURE (°C) 425112 G19 100 UV/0V = 4V TIMER = 0V GATE = HIGH TA = 25°C 1000 –1.5 –1.0 –0.5 0 0.5 1.0 (VSENSE – VEE) (V) 1.5 2.0 425112 G20 TIMER THRESHOLD (V) 0.1 –14 –18 5 25 45 65 85 105 125 TEMPERATURE (°C) 425112 G18 –12 –28 VOVLO 5.91 425112 G17 ISENSE vs Temperature –26 6.01 5.61 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 425112 G16 –10 VOVHI 6.11 5.71 2.10 5 25 45 65 85 105 125 TEMPERATURE (°C) 6.21 5.81 5.45 2.05 –55 –35 –15 LTC4251-1 6.31 6.05 VUVLO 2.15 6.41 OV THRESHOLD (V) 2.45 5 25 45 65 85 105 125 TEMPERATURE (°C) 425112 G14 2.55 UV THRESHOLD (V) 3.175 2.875 0.1 10.5 ISENSE (µA) VUVH 0.2 11.0 2.50 UV/OV = 4V refers to UV = 4V for the LTC4251-2. VTMRH 3.5 3.0 2.5 2.0 1.5 1.0 VTMRL 0.5 0 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 425112 G21 425112fa 5 LTC4251/LTC4251-1/ LTC4251-2 U W TYPICAL PERFOR A CE CHARACTERISTICS UV/OV = 4V refers to UV = 4V for the LTC4251-2. ITMR (Initial Cycle, Sinking) vs Temperature ITMR (Initial Cycle, Sourcing) vs Temperature 10 ITMR (Circuit Breaking, Sourcing) vs Temperature 280 50 9 45 8 260 40 5 4 35 ITMR (µA) 6 ITMR (mA) ITMR (µA) 7 30 25 240 220 3 20 2 200 15 1 0 –55 –35 –15 10 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 425112 G22 5 25 45 65 85 105 125 TEMPERATURE (°C) 180 –55 –35 –15 425112 G24 425112 G23 t PLLUG and t PHLOG vs Temperature ITMR (Cooling Cycle, Sinking) vs Temperature 10 1.3 9 1.2 8 1.1 7 tPHLOG (LTC4251/LTC4251-1) DELAY (µs) ITMR (µA) 5 25 45 65 85 105 125 TEMPERATURE (°C) 6 5 4 1.0 0.9 0.8 tPLLUG 3 0.7 2 0.6 1 0 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 425112 G25 0.5 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 425112 G26 425112fa 6 LTC4251/LTC4251-1/ LTC4251-2 U U U PI FU CTIO S UV/OV refers to the UV pin for the LTC4251-2. The OV comparator in the LTC4251-2 is disabled. All references in the text to overvoltage, OV, VOVHI and VOVLO do not apply to the LTC4251-2. SENSE (Pin 1): Circuit Breaker/Current Limit SENSE Pin. Load current is monitored by sense resistor RS connected between SENSE and VEE, and controlled in three steps. If SENSE exceeds VCB (50mV), the circuit breaker comparator activates a 230µA TIMER pin pull-up current. The LTC4251/LTC4251-1/LTC4251-2 latch off when CT charges to 4V. If SENSE exceeds VACL (100mV), the analog current limit amplifier pulls GATE down and regulates the MOSFET current at VACL/RS. In the event of a catastrophic shortcircuit, SENSE may overshoot 100mV. If SENSE reaches VFCL (200mV), the fast current limit comparator pulls GATE low with a strong pull-down. To disable the circuit breaker and current limit functions, connect SENSE to VEE. Kelvin-sense connections between the sense resistor and the VEE and SENSE pins are strongly recommended, see Figure 6. VEE (Pin 2): Negative Supply Voltage Input. Connect this pin to the negative side of the power supply. VIN (Pin 3): Positive Supply Input. Connect this pin to the positive side of the supply through a dropping resistor. A shunt regulator typically clamps VIN at 13V. An internal undervoltage lockout (UVLO) circuit holds GATE low until the VIN pin is greater than VLKO (9.2V), overriding UV/OV. If UV is high, OV is low and VIN comes out of UVLO, TIMER starts an initial timing cycle before initiating a GATE ramp up. If VIN drops below approximately 8.2V, GATE pulls low immediately. TIMER (Pin 4): Timer Input. TIMER is used to generate a delay at start up, and to delay shutdown in the event of an output overload. TIMER starts an initial timing cycle when the following conditions are met: UV is high, OV is low, VIN clears UVLO, TIMER pin is low, GATE is lower than VGATEL and VSENSE – VEE < VCB. A pull-up current of 5.8µA then charges CT, generating a time delay. If CT charges to VTMRH (4V) the timing cycle terminates, TIMER quickly pulls low and GATE is activated. If SENSE exceeds 50mV while GATE is high, a 230µA pullup current charges CT. If SENSE drops below 50mV before TIMER reaches 4V, a 5.8µA pull-down current slowly discharges CT. In the event that CT eventually integrates up to the 4V VTMRH threshold, TIMER latches high with a 5.8µA pull-up source and GATE quickly pulls low. The LTC4251/LTC4251-1/LTC4251-2 fault latches may be cleared by either pulling TIMER low with an external device, or by pulling UV/OV below VUVLO. UV/OV (Pin 5): Undervoltage/Overvoltage Input. This dual function pin detects undervoltage as well as overvoltage. The high threshold at the UV comparator is set at VUVHI with VUVHST hysteresis. The high threshold at the OV comparator is set at VOVHI with VOVHST hysteresis. If UV/OV < VUVLO or UV/OV > VOVHI, GATE pulls low. If UV/OV > VUVHI and UV/OV < VOVLO, the LTC4251/ LTC4251-1/LTC4251-2 attempt to start-up. The internal UVLO at VIN always overrides UV/OV. A low at UV resets an internal fault latch. A high at OV pulls GATE low but does not reset the fault latch. A 1nF to 10nF capacitor at UV/OV eliminates transients and switching noise from affecting the UV/OV thresholds and prevents glitches at the GATE pin. GATE (Pin 6): N-Channel MOSFET Gate Drive Output. This pin is pulled high by a 58µA current source. GATE is pulled low by invalid conditions at VIN (UVLO), UV/OV, or the fault latch. GATE is actively servoed to control fault current as measured at SENSE. A compensation capacitor at GATE stabilizes this loop. A comparator monitors GATE to ensure that it is low before allowing an initial timing cycle, GATE ramp up after an overvoltage event, or restart after a current limit fault. 425112fa 7 LTC4251/LTC4251-1/ LTC4251-2 W BLOCK DIAGRA VIN 3 VOVHI VIN – OV** 58µA + 6 GATE VEE – 5 + UV/OV* VEE 0.5V UV 230µA + VIN 5.8µA LOGIC 4V + VIN – VUVLO – FCL VIN TIMER – + 200mV 22µA +– VEE 4 – 1V VEE 5.8µA + ACL 5k VOS = 10mV + –+ VEE – VEE VEE + CB – 2 *UV FOR THE LTC4251-2 ** THE OV COMPARATOR IS DISABLED FOR LTC4251-2 1 SENSE 50mV +– VEE 425112 BD VEE U OPERATIO Note that for simplicity, the following assumptions are made in the text. Firstly, UV/OV also means the UV pin of the LTC4251-2. Secondly, all overvoltage conditions and references to OV, VOVHI and VOVLO do not apply to the LTC4251-2 as the OV comparator in this part is disabled. Hot Circuit Insertion When circuit boards are inserted into a live backplane, the supply bypass capacitors can draw huge transient currents from the power bus as they charge. The flow of current damages the connector pins and glitches the power bus, causing other boards in the system to reset. The LTC4251/ LTC4251-1/LTC4251-2 are designed to turn on a circuit board supply in a controlled manner, allowing insertion or removal without glitches or connector damage. Initial Start-Up The LTC4251/LTC4251-1/LTC4251-2 reside on a removable circuit board and control the path between the connector and load or power conversion circuitry with an 8 external MOSFET switch (see Figure 1). Both inrush control and short-circuit protection are provided by the MOSFET. A detailed schematic is shown in Figure 2. –48V and –48RTN receive power through the longest connector pins, and are the first to connect when the board is inserted. The GATE pin holds the MOSFET off during this time. UV/OV determines whether or not the MOSFET should be turned on based upon internal, high-accuracy thresholds and an external divider. UV/OV does double duty by also monitoring whether or not the connector is seated. The top of the divider detects –48RTN by way of a short connector pin that is the last to mate during the insertion sequence. 425112fa LTC4251/LTC4251-1/ LTC4251-2 U OPERATIO PLUG-IN BOARD + –48RTN LTC4251 + ISOLATED DC/DC CONVERTER MODULE + CLOAD – –48V LOW VOLTAGE CIRCUITRY – BACKPLANE 425112 F01 Figure 1. Basic LTC4251 Hot Swap Topology LONG –48RTN RIN 10k 500mW SHORT R1 402k 1% CIN 1µF VIN UV/OV C1 10nF VEE R2 32.4k 1% LONG –48V + LTC4251 TIMER CT 150nF 3 SENSE CL 100µF TYP GATE RC 10Ω CC 18nF 4 1 RS 2 20mΩ Q1 IRF530S 425112 F02 Figure 2. –48V, 2.5A Hot Swap Controller Interlock Conditions A start-up sequence commences once five initial “interlock” conditions are met: 1. The input voltage VIN exceeds 9.2V (VLKO) 2. The voltage at UV/OV falls within the range of VUVHI to VOVLO (UV > VUVHI, LTC4251-2) 3. The (SENSE – VEE) voltage is <50mV (VCB) 4. The voltage on the timer capacitor (CT) is less than 1V (VTMRL) 5. GATE is less than 0.5V (VGATEL) The first two conditions are continuously monitored and the latter three are checked prior to initial timing or GATE ramp-up. Upon exiting an OV condition, the TIMER pin voltage requirement is inhibited. Details are described in the Applications Information, Timing Waveforms section. TIMER begins the start-up sequence by sourcing 5.8µA into CT. If VIN or UV/OV falls out of range, the start-up cycle stops and TIMER discharges CT to less than 1V, then waits until the aforementioned conditions are once again met. If CT successfully charges to 4V, TIMER pulls low and GATE is released. GATE sources 58µA (IGATE), charging the MOSFET gate and associated capacitance. Two modes of operation are possible during the time the MOSFET is first turning on, depending on the values of external components, MOSFET characteristics and nominal design current. One possibility is that the MOSFET will turn on gradually so that the inrush into the load capacitance remains a low value. The output will simply ramp to –48V and the MOSFET will be fully enhanced. A second possibility is that the load current exceeds the current limit threshold of 100mV/RS. In this case, the LTC4251/ LTC4251-1/LTC4251-2 will ramp the output by sourcing 100mV/RS current into the load capacitance. It is important to set the timer delay so that, regardless of which start-up mode is used, the start-up time is less than the TIMER delay time. If this condition is not met, the LTC4251/ LTC4251-1/LTC4251-2 may shut down after one TIMER delay. Board Removal If the board is withdrawn from the card cage, the UV/OV divider is the first to lose connection. This shuts off the MOSFET and commutates the flow of current in the connector. When the power pins subsequently separate, there is no arcing. Current Control Three levels of protection handle short-circuit and overload conditions. Load current is monitored by SENSE and resistor RS. There are three distinct thresholds at SENSE: 50mV for a timed circuit breaker function; 100mV for an analog current limit loop; and 200mV for a fast, feedforward comparator which limits peak current in the event of a catastrophic short-circuit. If, owing to an output overload, the voltage drop across RS exceeds 50mV, TIMER sources 230µA into CT. CT eventually charges to a 4V threshold and the LTC4251/LTC4251-1/ LTC4251-2 latch off. If the overload goes away and SENSE measures less than 50mV, CT slowly discharges (5.8µA). In this way the circuit breaker function will also respond to low duty cycle overloads, and accounts for fast heating and slow cooling characteristic of the MOSFET. 425112fa 9 LTC4251/LTC4251-1/ LTC4251-2 U OPERATIO Higher overloads are handled by an analog current limit loop. If the drop across RS reaches 100mV, the current limiting loop servos the MOSFET gate and maintains a constant output current of 100mV/RS. Note that because SENSE > 50mV, TIMER charges CT during this time and the LTC4251/LTC4251-1/LTC4251-2 will eventually shut down. Low impedance failures on the load side of the LTC4251/ LTC4251-1/LTC4251-2 coupled with 48V or more driving potential can produce current slew rates well in excess of 50A/µs. Under these conditions, overshoot is inevitable. A fast SENSE comparator with a threshold of 200mV detects overshoot and pulls GATE low much harder and hence much faster than can the weaker current limit loop. The 100mV/RS current limit loop then takes over, and servos the current as previously described. As before, TIMER runs and latches the LTC4251/LTC4251-1/LTC4251-2 off when CT reaches 4V. U W U U APPLICATIO S I FOR ATIO The LTC4251/LTC4251-1/LTC4251-2 circuit breaker latch is reset by either pulling UV/OV momentarily low, or dropping the input voltage VIN below the internal UVLO threshold of 8.2V. Although short-circuits are the most obvious fault type, several operating conditions may invoke overcurrent protection. Noise spikes from the backplane or load, input steps caused by the connection of a second, higher voltage supply, transient currents caused by faults on adjacent circuit boards sharing the same power bus, or the insertion of non-hot swappable products could cause higher than anticipated input current and temporary detection of an overcurrent condition. The action of TIMER and CT rejects these events allowing the LTC4251/ LTC4251-1/LTC4251-2 to “ride out” temporary overloads and disturbances that would trip a simple current comparator and in some cases, blow a fuse. (Refer to Block Diagram) SHUNT REGULATOR UV/OV COMPARATORS A fast responding regulator shunts the LTC4251/ LTC4251-1/LTC4251-2 VIN pin. Power is derived from –48RTN by an external current limiting resistor. The shunt regulator clamps VIN to 13V (VZ). A 1µF decoupling capacitor at VIN filters supply transients and contributes a short delay at start-up. A 10k 1/2W (RIN) resistor can be two 5k 1/4W resistors in series. Two hysteretic comparators for detecting under- and overvoltage conditions, with the following thresholds, monitor the dual function UV/OV pin: INTERNAL UNDERVOLTAGE LOCKOUT (UVLO) Internal circuitry monitors VIN for undervoltage. The exact thresholds are defined by VLKO and its hysteresis, VLKH. When VIN rises above 9.2V (VLKO) the chip is enabled; below 8.2V (VLKO-VLKH) it is disabled and GATE is pulled low. The UVLO function at VIN should not be confused with the UV/OV pin. These are completely separate functions. UV turning on at VUVHI UV turning off at VUVLO OV turning off at VOVHI OV turning on at VOVLO The UV and OV trip point ratio for LTC4251 is designed to match the standard telecom operating range of 43V to 75V. The LTC4251-2 implements a UV threshold of 43V only. A divider (R1, R2) is used to scale the supply voltage. Using R1 = 402k and R2 = 32.4k gives a typical operating range of 43.2V to 74.4V. The under- and overvoltage shutdown thresholds are then 39.2V and 82.5V. 1% divider resistors are recommended to preserve threshold accuracy. The same resistor values can be used for the LTC4251-2. 425112fa 10 LTC4251/LTC4251-1/ LTC4251-2 U W U U APPLICATIO S I FOR ATIO The R1-R2 divider values shown in the Typical Application set a standing current of slightly more than 100µA, and define an impedance at UV/OV of 30k. In most applications, 30k impedance coupled with 300mV UV hysteresis makes the LTC4251/LTC4251-1/LTC4251-2 insensitive to noise. If more noise immunity is desired, add a 1nF to 10nF filter capacitor from UV/OV to VEE. The UV and OV trip point thresholds for the LTC4251-1 are designed to encompass the standard telecom operating range of –36V to –72V. A divider (R1, R2) is used to scale the supply voltage. Using R1 = 442k and R2 = 34.8k gives a typical operating range of 33.2V to 81V. The typical under- and overvoltage shutdown thresholds are then 29.6V and 84.5V. 1% divider resistors are recommended to preserve threshold accuracy. The R1-R2 divider values shown in the Typical Application set a standing current of slightly more than 100µA, and define an impedance at UV/OV of 32k. In most applications, 32k impedance coupled with 260mV UV hysteresis makes the LTC4251-1 insensitive to noise. If more noise immunity is desired, add a 1nF to 10nF filter capacitor from UV/OV to VEE. UV/OV OPERATION A low input to the UV comparator will reset the chip and pull the GATE and TIMER pins low. A low-to-high UV transition will initiate an initial timing sequence if the three remaining interlock conditions are met. Overvoltage conditions detected by the OV comparator will also pull GATE low, thereby shutting down the load, but it will not reset the circuit breaker latch. Returning the supply voltage to an acceptable range restarts the GATE pin provided all interlock conditions except TIMER are met. TIMER The operation of the TIMER pin is somewhat complex as it handles several key functions. A capacitor, CT, is used at TIMER to provide timing for the LTC4251/LTC4251-1/ LTC4251-2. Four different charging and discharging modes are available at TIMER: 1. 5.8µA slow charge; initial timing delay 2. 230µA fast charge; circuit breaker delay 3. 5.8µA slow discharge; circuit breaker “cool-off” 4. Low impedance switch; resets capacitor after initial timing delay, in undervoltage lockout, and in overvoltage For initial startup, the 5.8µA pull-up is used. The low impedance switch is turned off and the 5.8µA current source is enabled when the four interlock conditions are met. CT charges to 4V in a time period given by: t= 4V • C T 5.8µA (1) When CT reaches 4V (VTMRH), the low impedance switch turns on and discharges CT. The GATE output is enabled and the load turns on. CIRCUIT BREAKER TIMER OPERATION If the SENSE pin detects more than 50mV across RS, the TIMER pin charges CT with 230µA. If CT charges to 4V, the GATE pin pulls low and the LTC4251/LTC4251-1/ LTC4251-2 latch off. The part remains latched off until either the UV/OV pin is momentarily pulsed low, or VIN dips into UVLO and is then restored. The circuit breaker timeout period is given by t= 4V • C T 230µA (2) Intermittent overloads may exceed the 50mV threshold at SENSE, but if their duration is sufficiently short TIMER will not reach 4V and the LTC4251/LTC4251-1/LTC4251-2 will not latch off. To handle this situation, the TIMER discharges CT slowly with a 5.8µA pull-down whenever the SENSE voltage is less than 50mV. Therefore any intermittent overload with an aggregate duty cycle of 2.5% or more will eventually trip the circuit breaker and latch off the LTC4251/LTC4251-1/LTC4251-2. Figure 3 shows the circuit breaker response time in seconds normalized to 1µF. The asymmetric charging and discharging of CT is a fair gauge of MOSFET heating. 425112fa 11 LTC4251/LTC4251-1/ LTC4251-2 U W U U APPLICATIO S I FOR ATIO NORMALIZED RESPONSE TIME (s/µF) 10 1 4 t = CT(µF) (235.8 • D) – 5.8 0.1 0.01 0 20 40 60 80 FAULT DUTY CYCLE, D (%) 100 425112 F03 Figure 3. Circuit Breaker Response Time GATE GATE is pulled low to VEE under any of the following conditions: in UVLO, during the initial timing cycle, in an overvoltage condition, or when the LTC4251/LTC4251-1/ LTC4251-2 are latched off after a short-circuit. When GATE turns on, a 58µA current source charges the MOSFET gate and any associated external capacitance. VIN limits gate drive to no more than 14.5V. Gate-drain capacitance (CGD) feed through at the first abrupt application of power can cause a gate-source voltage sufficient to turn on the MOSFET. A unique circuit pulls GATE low with practically no usable voltage at VIN, and eliminates current spikes at insertion. A large external gate-source capacitor is thus unnecessary for the purpose of compensating CGD. Instead, a smaller value (≥10nF) capacitor CC is adequate. CC also provides compensation for the analog current limit loop. SENSE The SENSE pin is monitored by the circuit breaker (CB) comparator, the analog current limit (ACL) amplifier, and the fast current limit (FCL) comparator. Each of these three measures the potential of SENSE relative to VEE. If SENSE exceeds 50mV, the CB comparator activates the 230µA TIMER pull-up. At 100mV, the ACL amplifier servos the MOSFET current, and at 200mV the FCL comparator abruptly pulls GATE low in an attempt to bring the MOSFET current under control. If any of these conditions persists long enough for TIMER to charge CT to 4V (see Equation (2)), the LTC4251/LTC4251-1/LTC4251-2 latch off and pull GATE low. If the SENSE pin encounters a voltage greater than 100mV, the ACL amplifier will servo GATE downwards in an attempt to control the MOSFET current. Since GATE overdrives the MOSFET in normal operation, the ACL amplifier needs time to discharge GATE to the threshold of the MOSFET. For a mild overload, the ACL amplifier can control the MOSFET current, but in the event of a severe overload the current may overshoot. At SENSE = 200mV, the FCL comparator takes over, quickly discharging the GATE pin to near VEE potential. FCL then releases, and the ACL amplifier takes over. All the while TIMER is running. The effect of FCL is to add a nonlinear response to the control loop in favor of reducing MOSFET current. Owing to inductive effects in the system, FCL typically overcorrects the current limit loop, and GATE undershoots. A zero in the loop (resistor RC in series with the gate capacitor) helps the ACL amplifier recover. SHORT-CIRCUIT OPERATION Circuit behavior arising from a load-side low impedance short is shown in Figure 4. Initially, the current overshoots the analog current limit level of VSENSE = 100mV (Trace 2) as the GATE pin works to bring VGS under control (Trace 3). The overshoot glitches the backplane in the negative direction, and when the current is reduced to 100mV/RS the backplane responds by glitching in the positive direction. TIMER commences charging CT (Trace 4) while the analog current limit loop maintains the fault current at 100mV/RS, which in this case is 5A (Trace 2). Note that the backplane voltage (Trace 1) sags under load. When CT reaches 4V, GATE turns off, the load current drops to zero and the backplane rings up to over 100V. The positive peak is usually limited by avalanche breakdown in the MOSFET, and can be further limited by adding a zener diode across the input from – 48V to – 48RTN, such as Diodes Inc. SMAT70A. A low-impedance short on one card may influence the behavior of others sharing the same backplane. The initial glitch and backplane sag as seen in Figure 4, Trace 1, can rob charge from output capacitors on adjacent cards. When the faulty card shuts down, current flows in to refresh the 425112fa 12 LTC4251/LTC4251-1/ LTC4251-2 U W U U APPLICATIO S I FOR ATIO capacitors. If LTC4251, LTC4251-1 or LTC4251-2s are used throughout, they respond by limiting the inrush current to a value of 100mV/RS. If CT is sized correctly, the capacitors will recharge long before CT times out. SUPPLY RING OWING TO CURRENT OVERSHOOT –48RTN 50V/DIV SUPPLY RING OWING TO MOSFET TURN-OFF IINRUSH(MIN)= TRACE 2 FAST CURRENT LIMIT TRACE 4 TIMER LATCH OFF ISHORT − CIRCUIT(MAX) = CTIMER RAMP 2ms/DIV 425112 F04 Figure 4. Output Short-Circuit Behavior (All Waveforms are Referenced to VEE) MOSFET SELECTION The external MOSFET switch must have adequate safe operating area (SOA) to charge the load capacitance on start-up and handle short-circuit conditions until TIMER latchoff. These considerations take precedence over DC current ratings. A MOSFET with adequate SOA for a given application can always handle the required current, but the opposite cannot be said. Consult the manufacturer’s MOSFET data sheet for safe operating area and effective transient thermal impedance curves. MOSFET selection is a three-step process. First, RS is calculated, and then the time required to charge the load capacitance is determined. This timing, along with the maximum short-circuit current and maximum input voltage defines an operating point that is checked against the MOSFET’s SOA curve. To begin a design, first specify the required load current and load capacitance, IL and CL. The circuit breaker current trip point (50mV/RS) should be set to accommodate the maximum load current. Note that maximum input current to a DC/DC converter is expected at VSUPPLY (MIN). RS is given by: RS = 40mV IL(MAX) 80mV RS (4) Maximum short-circuit current limit is calculated using maximum VSENSE, or: TRACE 3 ANALOG CURRENT LIMIT 5V/DIV During the initial charging process, the LTC4251/ LTC4251-1/LTC4251-2 may operate the MOSFET in current limit, forcing 80mV to 120mV across RS. The minimum inrush current is given by: TRACE 1 ONSET OF OUTPUT SHORT-CIRCUIT SENSE 200mV/DIV GATE 10V/DIV where 40mV represents the guaranteed minimum circuit breaker threshold. (3) 120mV RS (5) The TIMER capacitor CT must be selected based on the slowest expected charging rate; otherwise TIMER might time out before the load capacitor is fully charged. A value for CT is calculated based on the maximum time it takes the load capacitor to charge. That time is given by: t CL CHARGE = C • V C L • VSUPPLY(MAX) = I IINRUSH(MIN) (6) Substituting Equation (4) for IINRUSH(MIN) and equating (6) with (2) gives: CT = C L • VSUPPLY(MAX) • RS • 230µA (4V • 80mV) (7) Returning to Equation (2), the TIMER period is calculated and used in conjunction with V SUPPLY(MAX) and ISHORT-CIRCUIT(MAX) to check the SOA curves of a prospective MOSFET. As a numerical design example, consider a 30W load, which requires 1A input current at 36V. If VSUPPLY(MAX) = 72V and CL = 100µF, Equation (3) gives RSENSE = 40mΩ; Equation (7) gives CT = 207nF. To account for errors in RSENSE, CT, TIMER current (230µA) and TIMER threshold (4V), the calculated value should be multiplied by 1.5, giving a nearest standard value of CT = 330nF. If a short-circuit occurs, a current of up to 120mV/40mΩ = 3A will flow in the MOSFET for 5.7ms as dictated by 425112fa 13 LTC4251/LTC4251-1/ LTC4251-2 U W U U APPLICATIO S I FOR ATIO SUMMARY OF DESIGN FLOW To summarize the design flow, consider the application shown in Figure 2, which was designed for 50W: Calculate maximum load current: 50W/36V = 1.4A; allowing 83% converter efficiency, IIN (MAX) = 1.7A. zener diode is required to clamp the input supply voltage and prevent MOSFET avalanche. 60 COMPENSATION CAPACITOR CC (nF) CT = 330nF in Equation (2). The MOSFET must be selected based on this criterion. The IRF530S can handle 100V and 3A for 10ms, and is safe to use in this application. MTY100N10E 50 40 IRF3710 30 IRF540 IRF530 20 IRF740 10 0 Calculate RS: from Equation (3) RS = 20mΩ. 0 2000 6000 4000 MOSFET CISS (pF) 8000 425112 F05 Calculate CT: from Equation (7) CT = 150nF (including 1.5X correction factor). Calculate TIMER period: from Equation (2) the shortcircuit time-out period is t = 2.6ms. Calculate maximum short-circuit current: from Equation (5) maximum short-circuit current could be as high as 120mV/20mΩ = 6A. Consult MOSFET SOA curves: the IRF530S can handle 6A at 72V for 5ms, so it is safe to use in this application. FREQUENCY COMPENSATION The LTC4251/LTC4251-1/LTC4251-2 typical frequency compensation network for the analog current limit loop is a series RC (10Ω) and CC connected to VEE. Figure 5 depicts the relationship between the compensation capacitor CC and the MOSFET’s CISS. The line in Figure 5 is used to select a starting value for CC based upon the MOSFET’s CISS specification. Optimized values for CC are shown for several popular MOSFETs. Differences in the optimized value of CC versus the starting value are small. Nevertheless, compensation values should be verified by board level short-circuit testing. As seen in Figure 4 previously, at the onset of a shortcircuit event, the input supply voltage can ring dramatically owing to series inductance. If this voltage avalanches the MOSFET, current continues to flow through the MOSFET to the output. The analog current limit loop cannot control this current flow and therefore the loop undershoots. This effect cannot be eliminated by frequency compensation. A Figure 5. Recommended Compensation Capacitor CC vs MOSFET CISS SENSE RESISTOR CONSIDERATIONS For proper circuit breaker operation, Kelvin-sense PCB connections between the sense resistor and the VEE and SENSE pins are strongly recommended. The drawing in Figure 6 illustrates the correct way of making connections between the LTC4251/LTC4251-1/LTC4251-2 and the sense resistor. PCB layout should be balanced and symmetrical to minimize wiring errors. In addition, the PCB layout for the sense resistor should include good thermal management techniques for optimal sense resistor power dissipation. CURRENT FLOW FROM LOAD CURRENT FLOW TO –48V BACKPLANE SENSE RESISTOR TRACK WIDTH W: 0.03" PER AMP ON 1 OZ COPPER W 425112 F06 TO SENSE TO VEE Figure 6. Making PCB Connections to the Sense Resistor TIMING WAVEFORMS System Power-Up Figure 7 details the timing waveforms for a typical powerup sequence in the case where a board is already installed in the backplane and system power is applied abruptly. At time point 1, the supply ramps up, together with UV/OV 425112fa 14 LTC4251/LTC4251-1/ LTC4251-2 U W U U APPLICATIO S I FOR ATIO and VOUT. VIN follows at a slower rate as set by the VIN bypass capacitor. At time point 2, VIN exceeds VLKO and the internal logic checks for VUVHI < UV/OV < VOVLO, TIMER < VTMRL, GATE < VGATEL and SENSE < VCB. When all conditions are met, an initial timing cycle starts and the TIMER capacitor is charged by a 5.8µA current source pull-up. At time point 3, TIMER reaches the VTMRH threshold and the initial timing cycle terminates. The TIMER capacitor is then quickly discharged. At time point 4, the VTMRL threshold is reached and the conditions of GATE < VGATEL and SENSE < VCB must be satisfied before a startup cycle is allowed to begin. GATE sources 58µA into the external MOSFET gate and compensation network. When the GATE voltage reaches the MOSFET’s threshold, current begins flowing into the load capacitor. At time point 5, the SENSE voltage (VSENSE – VEE ) reaches the VCB threshold and activates the TIMER. The TIMER capacitor is charged by a 230µA current-source pull-up. At time point 6, the analog current limit loop activates. Between time point 6 and time point 7, the GATE voltage is held essentially constant and the sense voltage is regulated at VACL. As the load capacitor nears full charge, its current begins to decline. At point 7, the load current falls and the sense voltage drops below VACL. The analog current limit loop shuts off and the GATE pin ramps further. At time point 8, the sense voltage drops below VCB and TIMER now discharges through a 5.8µA current source pulldown. At time point 9, GATE reaches its maximum voltage as determined by VIN. Live Insertion with Short Pin Control of UV/OV In this example as shown in Figure 8, power is delivered through long connector pins whereas the UV/OV divider makes contact through a short pin. This ensures the power connections are firmly established before the LTC4251/ LTC4251-1/LTC4251-2 are activated. At time point 1, the power pins make contact and VIN ramps through VLKO. At time point 2, the UV/OV divider makes contact and its voltage exceeds VUVHI. In addition, the internal logic checks for VUVHI < UV/OV < VOVHI, TIMER < VTMRL, GATE < VGATEL and SENSE < VCB. When all conditions are met, an initial timing cycle starts and the TIMER capacitor is charged by a 5.8µA current source pull-up. At time point 3, TIMER reaches the VTMRH threshold and the initial timing cycle terminates. The TIMER capacitor is then quickly discharged. At time point 4, the VTMRL threshold is reached and the conditions of GATE < VGATEL and SENSE < VCB must be satisfied before a start-up cycle is allowed to begin. GATE sources 58µA into the external MOSFET gate and compensation network. When the GATE voltage reaches the MOSFET’s threshold, current begins flowing into the load capacitor. At time point 5, the SENSE voltage (VSENSE – VEE ) reaches the VCB threshold and activates the TIMER. The TIMER capacitor is charged by a 230µA current source pull-up. At time point 6, the analog current limit loop activates. Between time point 6 and time point 7, the GATE voltage is held essentially constant and the sense voltage is regulated at VACL. As the load capacitor nears full charge, its current begins to decline. At time point 7, the load current falls and the sense voltage drops below VACL. The analog current limit loop shuts off and the GATE pin ramps further. At time point 8, the sense voltage drops below VCB and TIMER now discharges through a 5.8µA current source pull-down. At time point 9, GATE reaches its maximum voltage as determined by VIN. Undervoltage Lockout Timing In Figure 9, when UV/OV drops below VUVLO (time point 1), TIMER and GATE pull low. If current has been flowing, the SENSE pin voltage decreases to zero as GATE collapses. When UV/OV recovers and clears VUVHI (time point 2), an initial time cycle begins followed by a start-up cycle. Undervoltage Timing with Overvoltage Glitch In Figure 10, when UV/OV clears VUVHI (time point 1), an initial timing cycle starts. If the system bus voltage overshoots VOVHI as shown at time point 2, TIMER discharges. At time point 3, the supply voltage recovers and drops below the VOVLO threshold. The initial timing cycle restarts followed by a start-up cycle. Overvoltage Timing During normal operation, if UV/OV exceeds VOVHI as shown at time point 1 of Figure 11, the TIMER status is unaffected. Nevertheless, GATE pulls down and disconnects the load. At time point 2, UV/OV recovers and drops below the VOVLO threshold. A gate ramp up cycle ensues. 425112fa 15 LTC4251/LTC4251-1/ LTC4251-2 U W U U APPLICATIO S I FOR ATIO If the overvoltage glitch is long enough to deplete the load capacitor, a full start-up cycle may occur as shown between time points 3 through 6. Timer Behavior In Figure 12a, the TIMER capacitor charges at 230µA if the SENSE pin exceeds VCB. It is discharged with 5.8µA if the VIN CLEARS VLKO, CHECK VUVHI <UV/0V < VOVLO, TIMER< VTMRL, GATE < VGATEL AND SENSE < VCB. TIMER CLEARS VTMRL, CHECK GATE < VGATEL AND SENSE < VCB. 1 2 3 4 56 78 9 GND-VEE UV/0V VLKO VIN VTMRH 5.8µA TIMER 230µA VTMRL 5.8µA 5.8µA 58µA GATE 58µA VACL SENSE VCB VOUT 425112 F07 INITIAL TIMING CYCLE START-UP CYCLE Figure 7. System Power-Up Timing (All Waveforms are Referenced to VEE) UV/0V CLEARS VUVHI, CHECK VIN < VLKO – VLKH, TIMER < VTMRL, GATE < VGATEL AND SENSE < VCB. TIMER CLEARS VTMRL, CHECK GATE < VGATEL AND SENSE < VCB. 1 2 3 4 56 78 9 GND-VEE VUVHI UV/0V VIN VLKO VTMRH TIMER 5.8µA 230µA VTMRL 5.8µA 5.8µA 58µA GATE 58µA VACL SENSE VCB VOUT 425112 F08 INITIAL TIMING CYCLE START-UP CYCLE Figure 8. Power-Up Timing with a Short-Pin (All Waveforms are Referenced to VEE) 425112fa 16 LTC4251/LTC4251-1/ LTC4251-2 U W U U APPLICATIO S I FOR ATIO current amplifier can establish control. If TIMER reaches VTMRH, GATE pulls low and latches off. SENSE pin is less than VCB. In Figure 12b, when TIMER exceeds VTMRH, TIMER is latched high by the 5.8µA pullup and GATE pulls down immediately. In Figure 12c, multiple momentary faults cause the TIMER capacitor to integrate until it latches. Resetting a Fault Latch As shown in Figure 14, a latched fault is reset by either pulling UV/OV below VUVLO or pulling TIMER below VTMRL. An initial timing cycle is initiated if UV/OV is used for reset. If TIMER is used for reset, the initial timing cycle is skipped. Analog Current Limit and Fast Current Limit In Figure 13a, when SENSE exceeds VACL, GATE is regulated by the analog current limit amplifier loop. When SENSE drops below VACL, GATE is allowed to pull up. In Figure 13b, when a severe fault occurs, SENSE exceeds VFCL and GATE immediately pulls down until the analog Internal Soft-Start An internal soft-start feature ramps the positive input of the analog current limit amplifier during initial start-up. VUV/0V DROPS BELOW VUVLO. TIMER, GATE, AND SENSE ARE PULLED TO VEE. VUV/0V CLEARS VUVHI, CHECK TIMER < VTMRL, GATE < VGATEL AND SENSE < VCB. TIMER CLEARS VTMRL, CHECK GATE < VGATEL AND SENSE < VCB. 1 UV/0V 2 3 4 56 78 9 VUVHI VUVLO VTMRH 5.8µA TIMER 230µA VTMRL 5.8µA 5.8µA 58µA GATE 58µA VACL SENSE VCB 425112 F09 INITIAL TIMING CYCLE START-UP CYCLE Figure 9. Undervoltage Lockout Timing (All Waveforms are Referenced to VEE) VUV/0V CLEARS VUVHI. CHECK TIMER < VTMRL, GATE < VGATEL AND SENSE < VCB. VUV/0V OVERSHOOTS VOVHI AND TIMER ABORTS INITIAL TIMING CYCLE. VUV/0V DROPS BELOW VOVLO AND TIMER RESTARTS INITIAL TIMING CYCLE. TIMER CLEARS VTMRL, CHECK GATE < VGATEL AND SENSE < VCB. 1 VOVHI 2 3 4 5 6 7 8 9 10 VOVLO UV/0V V UVHI VTMRH TIMER 5.8µA 230µA VTMRL 5.8µA 5.8µA 58µA GATE 58µA VACL SENSE VCB 425112 F10 INITIAL TIMING CYCLE START-UP CYCLE Figure 10. Undervoltage Timing with an Overvoltage Glitch (All Waveforms are Referenced to VEE) 425112fa 17 LTC4251/LTC4251-1/ LTC4251-2 U W U U APPLICATIO S I FOR ATIO The ramp duration is approximately 200µs. This feature reduces load current dl/dt at start-up. As illustrated in Figure 15, soft-start is initiated by a TIMER transition from VTMRH to VTMRL or when UV/OV falls below the VOVLO threshold after an OV fault. After soft-start duration, load current is limited by VACL/RS. VUV/0V OVERSHOOTS VOVHI AND GATE PULLS TO VEE. TIMER UNAFFECTED. VUV/0V DROPS BELOW VOVLO AND GATE RESTARTS. 1 UV/0V 2 3 4 56 7 VOVHI VOVLO VTMRH TIMER 5.8µA 230µA 5.8µA 5.8µA 5.8µA 58µA GATE 58µA VACL SENSE VCB 425112 F11 Figure 11. Overvoltage Timing (All Waveforms are Referenced to VEE) TIMER LATCHES OFF 1 2 1 230µA 230µA TIMER 5.8µA TIMER LATCHES OFF 1 5.8µA VTMRH VTMRL TIMER 2 230µA TIMER 2 3 5.8µA 4 230µA 5.8µA VTMRH 5.8µA GATE GATE GATE VACL VACL VACL VCB SENSE VCB SENSE VOUT VCB SENSE VOUT VOUT 425112 F12c CB FAULT CB FAULT 425112 F12a (12a) Momentary Circuit-Breaker Fault 425112 F12b (12b) Circuit-Breaker Time-Out (12c) Multiple Circuit-Breaker Faults Figure 12. Timer Behavior (All Waveforms are Referenced to VEE) TIMER LATCHES OFF 12 1 34 TIMER 2 5.8µA VTMRH VTMRH 230µA TIMER 5.8µA 230µA 5.8µA GATE 58µA GATE VFCL VACL SENSE SENSE VCB VACL VCB VOUT VOUT 425112 F13b 425112 F13a (13a) Analog Current Limit Fault (13b) Fast Current Limit Fault Figure 13. Current Limit Behavior (All Waveforms are Referenced to VEE) 425112fa 18 LTC4251/LTC4251-1/ LTC4251-2 U W U U APPLICATIO S I FOR ATIO RESET LATCHED TIMER FAULT BY EXTERNAL LOW PULSE. 5.8µA 1 2 3 END OF INITIAL TIMING CYCLE 45 6 1 2 3 4 VTMRH TIMER V TMRL GATE 5.8µA 230µA 5.8µA 5.8µA TIMER 5 6 VTMRH 230µA VTMRL 58µA ~VGS(th) 58µA 58µA GATE VACL VACL VCB SENSE SENSE 425112 F14 VCB VACL + 10mV INTERNAL SOFT-START REFERENCE Figure 14. Latched Fault Reset Timing (All Waveforms are Referenced to VEE) 10mV 425112 F15 Figure 15. Internal Soft-Start Timing (All Waveforms are Referenced to VEE) U PACKAGE DESCRIPTIO S6 Package 6-Lead Plastic TSOT-23 (Reference LTC DWG # 05-08-1636) 0.62 MAX 2.90 BSC (NOTE 4) 0.95 REF 1.22 REF 3.85 MAX 2.62 REF 1.4 MIN 2.80 BSC 1.50 – 1.75 (NOTE 4) PIN ONE ID RECOMMENDED SOLDER PAD LAYOUT PER IPC CALCULATOR 0.30 – 0.45 6 PLCS (NOTE 3) 0.95 BSC 0.80 – 0.90 0.20 BSC 0.01 – 0.10 1.00 MAX DATUM ‘A’ 0.30 – 0.50 REF 0.09 – 0.20 (NOTE 3) NOTE: 1. DIMENSIONS ARE IN MILLIMETERS 2. DRAWING NOT TO SCALE 3. DIMENSIONS ARE INCLUSIVE OF PLATING 4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR 5. MOLD FLASH SHALL NOT EXCEED 0.254mm 6. JEDEC PACKAGE REFERENCE IS MO-193 1.90 BSC S6 TSOT-23 0302 425112fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 19 LTC4251/LTC4251-1/ LTC4251-2 U TYPICAL APPLICATIO S GND RIN 10k 500mW GND (SHORT PIN) R1 402k 1% 3 VIN 5 UV/OV C1 10nF R2 32.4k 1% PUSHRESET GATE CL 100µF TIMER SENSE CT 82nF Q1 IRF540 R3 22Ω 1 3 1 RS 0.01Ω 2 RC 10Ω CC 22nF VEE S1 LOAD CIN 1µF 6 LTC4251 4 + 2 4 –48V 425112 TA03 Figure 16. –48V/5A Application with Reverse SENSE Pin Limiting and Push-Reset at TIMER Pin GND RIN 10k 500mW GND (SHORT PIN) R1 442k 1% 3 VIN 5 UV/OV C1 10nF GATE 6 R3 31.6k CIN 1µF R2 34.8k 1% TIMER SENSE 1 LOAD VOUT Q1 IRF540S 3 1 RS 0.02Ω RC 10Ω CC 22nF VEE CT 220nF + D1 BZX84C36 R4 22Ω LTC4251-1 4 CL 100µF 2 2 4 VSUPPLY = –48V 425112 TA04 Figure 17. Power-Limited Circuit Breaker Application RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT1640AH/LT1640AL Negative High Voltage Hot Swap Controllers in SO-8 Negative High Voltage Supplies from –10V to –80V LT1641-1/LT1641-2 Positive High Voltage Hot Swap Controllers in SO-8 Supplies from 9V to 80V, Latched Off/Autoretry LTC1642 Fault Protected Hot Swap Controller 3V to 16.5V, Overvoltage Protection up to 33V LTC1921 Dual – 48V Supply and Fuse Monitor ±1V UV and ±1.5V OV Threshold Accuracy, ±200V Transient Protection, Drives Three Optoisolators for Status LT4250 –48V Hot Swap Controller in SO-8 Active Current Limiting, Supplies from –20V to –80V LTC4252-1/ LTC4252-2 Negative Voltage Hot Swap Controller in MSOP Fast Active Current Limiting with Drain Accelerated Response, Supplies from –15V LTC4253 Negative Voltage Hot Swap Controller with 3-Output Sequencer Fast Active Current Limiting with Drain Accelerated Response, Supplies from –15V 425112fa 20 Linear Technology Corporation LT 0406 REV A • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2001