TCA6416 www.ti.com ........................................................................................................................................ SCPS153A – DECEMBER 2007 – REVISED FEBRUARY 2009 LOW-VOLTAGE 16-BIT I2C AND SMBus I/O EXPANDER WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS FEATURES 1 PW PACKAGE (TOP VIEW) RTW PACKAGE (TOP VIEW) 1 24 VCCP 2 23 3 22 4 21 SDA SCL ADDR P17 P16 P15 P14 P13 P12 P11 P10 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 • RESET VCCI INT VCCI RESET P00 P01 P02 P03 P04 P05 P06 P07 GND • 5-V Tolerant I/O Ports Active-Low Reset (RESET) Input Open-Drain Active-Low Interrupt (INT) Output 400-kHz Fast I2C Bus Input/Output Configuration Register Polarity Inversion Register Internal Power-On Reset Power Up With All Channels Configured as Inputs No Glitch On Power Up Noise Filter on SCL/SDA Inputs Latched Outputs With High-Current Drive Maximum Capability for Directly Driving LEDs Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) ZQS PACKAGE (TOP VIEW) SDA SCL • • • • • • INT VCCP • • • • • • • • • Operating Power-Supply Voltage Range of 1.65 V to 5.5 V Allows Bidirectional Voltage-Level Translation and GPIO Expansion Between: – 1.8-V SCL/SDA and 1.8-V, 2.5-V, 3.3-V, or 5-V P Port – 2.5-V SCL/SDA and 1.8-V, 2.5-V, 3.3-V, or 5-V P Port – 3.3-V SCL/SDA and 1.8-V, 2.5-V, 3.3-V, or 5-V P Port – 5-V SCL/SDA and 1.8-V, 2.5-V, 3.3-V, or 5-V P Port 2 I C to Parallel Port Expander Low Standby Current Consumption of 1 µA Schmitt-Trigger Action Allows Slow Input Transition and Better Switching Noise Immunity at the SCL and SDA Inputs – Vhys = 0.18 V Typ at 1.8 V – Vhys = 0.25 V Typ at 2.5 V – Vhys = 0.33 V Typ at 3.3 V – Vhys = 0.5 V Typ at 5 V 24 23 22 21 20 19 P00 P01 P02 P03 P04 P05 18 1 2 17 3 16 4 15 5 14 6 13 7 8 9 10 11 12 ADDR P17 P16 P15 P14 P13 E D C B A 5 4 3 2 1 P06 P07 GND P10 P11 P12 • DESCRIPTION/ORDERING INFORMATION This 16-bit I/O expander for the two-line bidirectional bus (I2C) is designed to provide general-purpose remote I/O expansion for most microcontroller families via the I2C interface [serial clock (SCL) and serial data (SDA)]. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007–2009, Texas Instruments Incorporated TCA6416 SCPS153A – DECEMBER 2007 – REVISED FEBRUARY 2009 ........................................................................................................................................ www.ti.com DESCRIPTION/ORDERING INFORMATION (CONTINUED) The major benefit of this device is its wide VCC range. It can operate from 1.65 V to 5.5 V on the P-port side and on the SDA/SCL side. This allows the TCA6416 to interface with next-generation microprocessors and microcontrollers on the SDA/SCL side, where supply levels are dropping down to conserve power. In contrast to the dropping power supplies of microprocessors and microcontrollers, some PCB components, such as LEDs, remain at a 5-V power supply. The bidirectional voltage level translation in the TCA6416 is provided through VCCI. VCCI should be connected to the VCC of the external SCL/SDA lines. This indicates the VCC level of the I2C bus to the TCA6416. The voltage level on the P-port of the TCA6416 is determined by the VCCP. The TCA6416 consists of two 8-bit Configuration (input or output selection), Input, Output, and Polarity Inversion (active high) registers. At power on, the I/Os are configured as inputs. However, the system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each input or output is kept in the corresponding input or output register. The polarity of the Input Port register can be inverted with the Polarity Inversion register. All registers can be read by the system master. The system master can reset the TCA6416 in the event of a timeout or other improper operation by asserting a low in the RESET input. The power-on reset puts the registers in their default state and initializes the I2C/SMBus state machine. The RESET pin causes the same reset/initialization to occur without depowering the part. The TCA6416 open-drain interrupt (INT) output is activated when any input state differs from its corresponding Input Port register state and is used to indicate to the system master that an input state has changed. INT can be connected to the interrupt input of a microcontroller. By sending an interrupt signal on this line, the remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via the I2C bus. Thus, the TCA6416 can remain a simple slave device. The device P-port outputs have high-current sink capabilities for directly driving LEDs while consuming low device current. One hardware pin (ADDR) can be used to program and vary the fixed I2C address and allow up to two devices to share the same I2C bus or SMBus. ORDERING INFORMATION PACKAGE (1) (2) TA –40°C to 85°C TOP-SIDE MARKING Reel of 1000 TCA6416ZQSR PH416 QFN – RTW Reel of 3000 TCA6416RTWR PH416 Tube of 70 TCA6416PW Reel of 2000 TCA6416PWR TSSOP – PW (1) (2) ORDERABLE PART NUMBER BGA – ZQS (Pb-free) PH416 Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. ZQS Package Terminal Assignments 2 E P13 P11 P10 GND P06 D P15 P14 P12 P07 P05 C P16 P17 P01 P04 P03 B ADDR VCCP VCCI NB P02 A SCL SDA INT RESET P00 5 4 3 2 1 Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): TCA6416 TCA6416 www.ti.com ........................................................................................................................................ SCPS153A – DECEMBER 2007 – REVISED FEBRUARY 2009 TERMINAL FUNCTIONS TERMINAL NO. DESCRIPTION TSSOP (PW) QFN (RTW) BGA (ZQS) NAME 1 22 A3 INT Interrupt output. Connect to VCCI or VCCP through a pullup resistor. 2 23 B3 VCCI Supply voltage of I2C bus. Connect directly to the VCC of the external I2C master. Provides voltage-level translation. 3 24 A2 RESET Active-low reset input. Connect to VCCP through a pullup resistor, if no active connection is used. 4 1 A1 P00 P-port input/output (push-pull design structure). At power on, P00 is configured as an input. 5 2 C3 P01 P-port input/output (push-pull design structure). At power on, P01 is configured as an input. 6 3 B1 P02 P-port input/output (push-pull design structure). At power on, P02 is configured as an input. 7 4 C1 P03 P-port input/output (push-pull design structure). At power on, P03 is configured as an input. 8 5 C2 P04 P-port input/output (push-pull design structure). At power on, P04 is configured as an input. 9 6 D1 P05 P-port input/output (push-pull design structure). At power on, P05 is configured as an input. 10 7 E1 P06 P-port input/output (push-pull design structure). At power on, P06 is configured as an input. 11 8 D2 P07 P-port input/output (push-pull design structure). At power on, P07 is configured as an input. 12 9 E2 GND Ground 13 10 E3 P10 P-port input/output (push-pull design structure). At power on, P10 is configured as an input. 14 11 E4 P11 P-port input/output (push-pull design structure). At power on, P11 is configured as an input. 15 12 D3 P12 P-port input/output (push-pull design structure). At power on, P12 is configured as an input. 16 13 E5 P13 P-port input/output (push-pull design structure). At power on, P13 is configured as an input. 17 14 D4 P14 P-port input/output (push-pull design structure). At power on, P14 is configured as an input. 18 15 D5 P15 P-port input/output (push-pull design structure). At power on, P15 is configured as an input. 19 16 C5 P16 P-port input/output (push-pull design structure). At power on, P16 is configured as an input. 20 17 C4 P17 P-port input/output (push-pull design structure). At power on, P17 is configured as an input. 21 18 B5 ADDR 22 19 A5 SCL Serial clock bus. Connect to VCCI through a pullup resistor. 23 20 A4 SDA Serial data bus. Connect to VCCI through a pullup resistor. 24 21 B4 VCCP Supply voltage of TCA6416 for P port Address input. Connect directly to VCCP or ground. Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): TCA6416 3 TCA6416 SCPS153A – DECEMBER 2007 – REVISED FEBRUARY 2009 ........................................................................................................................................ www.ti.com Voltage Translation Table 1 shows how to set up VCC levels for the necessary voltage translation between the I2C bus and the TCA6416. Table 1. Voltage Translation 4 VCCI (SDA AND SCL OF I2C MASTER) (V) VCCP (P PORT) (V) 1.8 1.8 1.8 2.5 1.8 3.3 1.8 5 2.5 1.8 2.5 2.5 2.5 3.3 2.5 5 3.3 1.8 3.3 2.5 3.3 3.3 3.3 5 5 1.8 5 2.5 5 3.3 5 5 Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): TCA6416 TCA6416 www.ti.com ........................................................................................................................................ SCPS153A – DECEMBER 2007 – REVISED FEBRUARY 2009 LOGIC DIAGRAM (POSITIVE LOGIC) INT ADDR SCL SDA VCCI VCCP RESET GND 1 Interrupt Logic LP Filter 21 22 23 Input Filter 2 I C Bus Control 2 16 Bits I/O Port P17–P10 P07–P00 Write Pulse Read Pulse 24 3 Shift Register Power-On Reset 12 A. All I/Os are set to inputs at reset. B. Pin numbers shown are for the PW package. Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): TCA6416 5 TCA6416 SCPS153A – DECEMBER 2007 – REVISED FEBRUARY 2009 ........................................................................................................................................ www.ti.com Simplified Schematic of P0 to P17 Data From Shift Register Data From Shift Register Output Port Register Data VCCP Configuration Register D Q Q1 FF Write Configuration Pulse CK Q D Q FF Write Pulse P00 to P17 CK Q Output Port Register Q2 Input Port Register Q D FF Read Pulse ESD Protection Diode GND Input Port Register Data CK Q To INT Data From Shift Register D Q FF Write Polarity Pulse Polarity Register Data CK Q Polarity Inversion Register A. On power up or reset, all registers return to default values. I/O Port When an I/O is configured as an input, FETs Q1 and Q2 are off, which creates a high-impedance input. The input voltage may be raised above VCC to a maximum of 5.5 V. If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the output port register. In this case, there are low-impedance paths between the I/O pin and either VCC or GND. The external voltage applied to this I/O pin should not exceed the recommended levels for proper operation. I2C Interface The bidirectional I2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be connected to a positive supply through a pullup resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. I2C communication with this device is initiated by a master sending a Start condition, a high-to-low transition on the SDA input/output, while the SCL input is high (see Figure 1). After the Start condition, the device address byte is sent, most significant bit (MSB) first, including the data direction bit (R/W). After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA input/output during the high of the ACK-related clock pulse. The address (ADDR) input of the slave device must not be changed between the Start and the Stop conditions. On the I2C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control commands (Start or Stop) (see Figure 2). 6 Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): TCA6416 TCA6416 www.ti.com ........................................................................................................................................ SCPS153A – DECEMBER 2007 – REVISED FEBRUARY 2009 A Stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the master (see Figure 1). Any number of data bytes can be transferred from the transmitter to receiver between the Start and the Stop conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK clock pulse, so that the SDA line is stable low during the high pulse of the ACK-related clock period (see Figure 3). When a slave receiver is addressed, it must generate an ACK after each byte is received. Similarly, the master must generate an ACK after each byte that it receives from the slave transmitter. Setup and hold times must be met to ensure proper operation. A master receiver signals an end of data to the slave transmitter by not generating an acknowledge (NACK) after the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line high. In this event, the transmitter must release the data line to enable the master to generate a Stop condition. SDA SCL S P Stop Condition Start Condition Figure 1. Definition of Start and Stop Conditions SDA SCL Data Line Change Figure 2. Bit Transfer Data Output by Transmitter NACK Data Output by Receiver ACK SCL From Master 1 2 8 9 S Clock Pulse for Acknowledgment Start Condition Figure 3. Acknowledgment on the I2C Bus Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): TCA6416 7 TCA6416 SCPS153A – DECEMBER 2007 – REVISED FEBRUARY 2009 ........................................................................................................................................ www.ti.com Interface Definition BIT BYTE 7 (MSB) 6 5 4 3 2 1 0 (LSB) L H L L L L ADDR R/W P07 P06 P05 P04 P03 P02 P01 P00 P17 P16 P15 P14 P13 P12 P11 P10 I2C slave address I/O data bus Device Address The address of the TCA6416 is shown in Figure 4. Slave Address 0 1 0 0 Fixed 0 AD 0 DR R/W Programmable Figure 4. TCA6416 Address Address Reference ADDR I2C BUS SLAVE ADDRESS L 32 (decimal), 20 (hexadecimal) H 33 (decimal), 21 (hexadecimal) The last bit of the slave address defines the operation (read or write) to be performed. A high (1) selects a read operation, while a low (0) selects a write operation. Control Register and Command Byte Following the successful acknowledgment of the address byte, the bus master sends a command byte, which is stored in the control register in the TCA6416. Three bits of this data byte state the operation (read or write) and the internal registers (input, output, polarity inversion, or configuration) that will be affected. This register can be written or read through the I2C bus. The command byte is sent only during a write transmission. Once a new command has been sent, the register that was addressed continues to be accessed by reads until a new command byte has been sent. B6 B7 B5 B4 B3 B2 B1 B0 Figure 5. Control Register Bits Command Byte CONTROL REGISTER BITS B7 B6 B5 B4 B3 B2 B1 B0 COMMAND BYTE (HEX) REGISTER PROTOCOL POWER-UP DEFAULT 0 0 0 0 0 0 0 0 00 Input Port 0 Read byte xxxx xxxx (1) 0 0 0 0 0 0 0 1 01 Input Port 1 Read byte xxxx xxxx 0 0 0 0 0 0 1 0 02 Output Port 0 Read/write byte 1111 1111 0 0 0 0 0 0 1 1 03 Output Port 1 Read/write byte 1111 1111 0 0 0 0 0 1 0 0 04 Polarity Inversion Port 0 Read/write byte 0000 0000 0 0 0 0 0 1 0 1 05 Polarity Inversion Port 1 Read/write byte 0000 0000 0 0 0 0 0 1 1 0 06 Configuration Port 0 Read/write byte 1111 1111 0 0 0 0 0 1 1 1 07 Configuration Port 1 Read/write byte 1111 1111 (1) 8 Undefined Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): TCA6416 TCA6416 www.ti.com ........................................................................................................................................ SCPS153A – DECEMBER 2007 – REVISED FEBRUARY 2009 Register Descriptions The Input Port registers (registers 0 and 1) reflect the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by the Configuration register. They act only on read operation. Writes to these registers have no effect. The default value (X) is determined by the externally applied logic level. Before a read operation, a write transmission is sent with the command byte to indicate to the I2C device that the Input Port register will be accessed next. Registers 0 and 1 (Input Port Registers) BIT I-07 I-06 I-05 I-04 I-03 I-02 I-01 I-00 DEFAULT X X X X X X X X BIT I-17 I-16 I-15 I-14 I-13 I-12 I-11 I-10 DEFAULT X X X X X X X X The Output Port registers (registers 2 and 3) shows\ the outgoing logic levels of the pins defined as outputs by the Configuration register. Bit values in these registers have no effect on pins defined as inputs. In turn, reads from these registers reflect the value that is in the flip-flop controlling the output selection, NOT the actual pin value. Registers 2 and 3 (Output Port Registers) BIT O-07 O-06 O-05 O-04 O-03 O-02 O-01 O-00 DEFAULT 1 1 1 1 1 1 1 1 BIT O-17 O-16 O-15 O-14 O-13 O-12 O-11 O-10 DEFAULT 1 1 1 1 1 1 1 1 The Polarity Inversion registers (register 4 and 5) allow polarity inversion of pins defined as inputs by the Configuration register. If a bit in these registers is set (written with 1), the corresponding port pin's polarity is inverted. If a bit in these registers is cleared (written with a 0), the corresponding port pin's original polarity is retained. Registers 4 and 5 (Polarity Inversion Registers) BIT P-07 P-06 P-05 P-04 P-03 P-02 P-01 DEFAULT 0 0 0 0 0 0 0 P-00 0 BIT P-17 P-16 P-15 P-14 P-13 P-12 P-11 P-10 DEFAULT 0 0 0 0 0 0 0 0 The Configuration registers (registers 6 and 7) configure the direction of the I/O pins. If a bit in these registers is set to 1, the corresponding port pin is enabled as an input with a high-impedance output driver. If a bit in these registers is cleared to 0, the corresponding port pin is enabled as an output. Registers 6 and 7 (Configuration Registers) BIT C-07 C-06 C-05 C-04 C-03 C-02 C-01 DEFAULT 1 1 1 1 1 1 1 C-00 1 BIT C-17 C-16 C-15 C-14 C-13 C-12 C-11 C-10 DEFAULT 1 1 1 1 1 1 1 1 Power-On Reset When power (from 0 V) is applied to VCCP, an internal power-on reset holds the TCA6416 in a reset condition until VCCP has reached VPOR. At that time, the reset condition is released, and the TCA6416 registers and I2C/SMBus state machine initializes to their default states. After that, VCCP must be lowered to below 0.2 V and back up to the operating voltage for a power-reset cycle. Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): TCA6416 9 TCA6416 SCPS153A – DECEMBER 2007 – REVISED FEBRUARY 2009 ........................................................................................................................................ www.ti.com Reset Input (RESET) The RESET input can be asserted to initialize the system while keeping the VCCP at its operating level. A reset can be accomplished by holding the RESET pin low for a minimum of tW. The TCA6416 registers and I2C/SMBus state machine are changed to their default state once RESET is low (0). When RESET is high (1), the I/O levels at the P port can be changed externally or through the master. This input requires a pullup resistor to VCCP, if no active connection is used. Interrupt (INT)Output An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time tiv, the signal INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original setting, data is read from the port that generated the interrupt or in a stop event. Resetting occurs in the read mode at the acknowledge (ACK) or not acknowledge (NACK) bit after the rising edge of the SCL signal. Interrupts that occur during the ACK or NACK clock pulse can be lost (or be very short) due to the resetting of the interrupt during this pulse. Each change of the I/Os after resetting is detected and is transmitted as INT. Reading from or writing to another device does not affect the interrupt circuit, and a pin configured as an output cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur, if the state of the pin does not match the contents of the Input Port register. In the TCA6416, an interrupt is not immediately generated by any rising or falling edge of port inputs in input mode after issuing any I2C commands (read or write). In order to capture the INT in the TCA6416, the user needs to add one more SCL clock pulse after a Stop signal. The INT output has an open-drain structure and requires a pullup resistor to VCCP or VCCI depending on the application. If the INT signal is connected back to the processor that provides the SCL signal to the TCA6416, then the INT pin has to be connected to VCCI. If not, the INT pin can be connected to VCCP. Bus Transactions Data is exchanged between the master and TCA6416 through write and read commands. Writes Data is transmitted to the TCA6416 by sending the device address and setting the least-significant bit (LSB) to a logic 0 (see Figure 4 for device address). The command byte is sent after the address and determines which register receives the data that follows the command byte. There is no limitation on the number of data bytes sent in one write transmission. The eight registers within the TCA6416 are configured to operate as four register pairs. The four pairs are input ports, output ports, polarity inversion ports and configuration ports. After sending data to one register, the next data byte is sent to the other register in the pair (see Figure 6 and Figure 7). For example, if the first byte is send to Output Port 1 (register 3), the next byte is stored in Output Port 0 (register 2). There is no limitation on the number of data bytes sent in one write transmission. In this way, each 8-bit register may be updated independently of the other registers. 10 Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): TCA6416 TCA6416 www.ti.com ........................................................................................................................................ SCPS153A – DECEMBER 2007 – REVISED FEBRUARY 2009 SCL 1 2 3 4 5 6 7 8 9 Command Byte Slave Address SDA 0 S 1 0 0 0 0 AD 0 DR A 0 0 0 0 0 0 Data to Port 0 1 0 R/W Acknowledge From Slave Start Condition A 0.7 Data to Port 1 0.0 A 1.7 Data 0 Acknowledge From Slave Data 1 1.0 A P Acknowledge From Slave Write to Port Data Out from Port 0 tpv Data Valid Data Out from Port 1 tpv Figure 6. Write to Output Port Register <br/> SCL 1 2 3 4 5 6 7 8 9 1 3 2 Slave Address SDA S 0 1 0 Start Condition 0 0 4 5 6 7 8 9 1 A 0 0 0 R/W Acknowledge From Slave 0 0 1 1/0 0/1 3 4 5 6 7 8 9 1 Data to Register Command Byte 0 AD DR 0 2 A MSB Data 0 Acknowledge From Slave 3 2 4 5 Data to Register LSB A MSB Data1 LSB A P Acknowledge From Slave Figure 7. Write to Configuration or Polarity Inversion Registers Reads The bus master first must send the TCA6416 address with the LSB set to a logic 0 (see Figure 4 for device address). The command byte is sent after the address and determines which register is accessed. After a restart, the device address is sent again but, this time, the LSB is set to a logic 1. Data from the register defined by the command byte then is sent by the TCA6416 (see Figure 8 and Figure 9). After a restart, the value of the register defined by the command byte matches the register being accessed when the restart occurred. For example, if the command byte references Input Port 1 before the restart, and the restart occurs when Input Port 0 is being read, the stored command byte changes to reference Input Port 0. The original command byte is forgotten. If a subsequent restart occurs, Input Port 0 is read first. Data is clocked into the register on the rising edge of the ACK clock pulse. After the first byte is read, additional bytes may be read, but the data now reflects the information in the other register in the pair. For example, if Input Port 1 is read, the next byte read is Input Port 0. Data is clocked into the register on the rising edge of the ACK clock pulse. There is no limitation on the number of data bytes received in one read transmission, but when the final byte is received, the bus master must not acknowledge the data. Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): TCA6416 11 TCA6416 SCPS153A – DECEMBER 2007 – REVISED FEBRUARY 2009 ........................................................................................................................................ www.ti.com Slave Address S 0 0 1 0 0 Acknowledge From Slave Acknowledge From Slave 0 AD DR 0 Command Byte A R/W A S Acknowledge From Slave Slave Address 0 1 0 0 0 AD 1 DR 0 Data A MSB LSB A First Byte R/W At this moment, master transmitter becomes master receiver, and slave receiver becomes slave transmitter. Data From Lower or Upper Byte Acknowledge of Register From Master Data From Upper or Lower Byte No Acknowledge of Register From Master MSB Data LSB NA P Last Byte Figure 8. Read From Register <br/> SCL 1 2 3 4 5 6 7 8 9 I0.x SDA S 0 1 0 0 0 0 AD DR Data 1 1 A R/W Acknowledge From Slave I1.x 1 A Data 2 Acknowledge From Master I0.x A Data 3 Acknowledge From Master I1.x A Data 4 Acknowledge From Master 1 P No Acknowledge From Master Read From Port 0 Data Into Port 0 Read From Port 1 Data Into Port 1 INT tiv tir A. Transfer of data can be stopped at any time by a Stop condition. When this occurs, data present at the latest acknowledge phase is valid (output mode). It is assumed that the command byte previously has been set to 00 (read Input Port register). B. This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address call and actual data transfer from P port (see Figure 8). Figure 9. Read Input Port Register 12 Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): TCA6416 TCA6416 www.ti.com ........................................................................................................................................ SCPS153A – DECEMBER 2007 – REVISED FEBRUARY 2009 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCCI Supply voltage range –0.5 6.5 UNIT V VCCP Supply voltage range –0.5 6.5 V (2) –0.5 6.5 V –0.5 6.5 V VI Input voltage range VO Output voltage range (2) IIK Input clamp current ADDR, RESET, SCL VI < 0 ±20 mA IOK Output clamp current INT VO < 0 ±20 mA P port VO < 0 or VO > VCCP ±20 SDA VO < 0 or VO > VCCI ±20 P port VO = 0 to VCCP 25 SDA, INT VO = 0 to VCCI 15 P port VO = 0 to VCCP IIOK Input/output clamp current IOL Continuous output low current IOH Continuous output high current ICC Tstg (1) (2) 25 Continuous current through GND 200 Continuous current through VCCP 160 Continuous current through VCCI 10 Storage temperature range –65 150 mA mA mA mA °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. THERMAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) UNIT PW package θJA (1) Package thermal impedance (1) 88 RTW package 66 ZQS package 171.6 °C/W The package thermal impedance is calculated in accordance with JESD 51-7. RECOMMENDED OPERATING CONDITIONS MIN MAX VCCI Supply voltage 1.65 5.5 VCCP Supply voltage 1.65 5.5 VIH High-level input voltage SCL, SDA 0.7 × VCCI 5.5 ADDR, P17–P00, RESET 0.7 × VCCP 5.5 VIL Low-level input voltage SCL, SDA –0.5 0.3 × VCCI ADDR, P17–P00, RESET –0.5 0.3 × VCCP IOH High-level output current P17–P00 10 mA IOL Low-level output current P17–P00 25 mA TA Operating free-air temperature 85 °C –40 Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): TCA6416 UNIT V V V 13 TCA6416 SCPS153A – DECEMBER 2007 – REVISED FEBRUARY 2009 ........................................................................................................................................ www.ti.com ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range, VCCI = 1.65 V to 5.5 V (unless otherwise noted) PARAMETER TEST CONDITIONS VCCP MIN VIK Input diode clamp II = –18 mA voltage 1.65 V to 5.5 V –1.2 VPOR Power-on reset voltage 1.65 V to 5.5 V VI = VCCP or GND, IO = 0 IOH = –8 mA P-port high-level output voltage VOH IOH = –10 mA IOL = 8 mA P-port low-level output voltage VOL IOL = 10 mA TYP (1) 1.2 2.3 V 1.8 3V 2.6 4.5 V 4.1 1.65 V 1 2.3 V 1.7 3V 2.5 4.5 V 4.0 1.4 1.65 V 0.45 2.3 V 0.25 3V 0.25 4.5 V 0.23 1.65 V 0.6 2.3 V 0.3 3V 0.25 4.5 V 1.65 V to 5.5 V 3 INT VOL = 0.4 V 1.65 V to 5.5 V 3 SCL, SDA VI = VCCI or GND ADDR, RESET VI = VCCP or GND IIH P port VI = VCCP IIL P port VI = GND SDA, P port, ADDR, RESET VI on SDA = VCCI or GND, VI on P port, ADDR and RESET = VCCP, IO = 0, I/O = inputs, fSCL = 400 kHz 1.65 V to 5.5 V 7.8 30 SDA, P port, ADDR, RESET VI on SDA = VCCI or GND, VI on P port, ADDR and RESET = VCCP, IO = 0, I/O = inputs, fSCL = 100 kHz 1.65 V to 5.5 V 1.7 10 SCL, SDA, P port, ADDR, RESET VI on SCL and SDA = VCCI or GND, VI on P port, ADDR and RESET = VCCP, IO = 0, I/O = inputs, fSCL = 0 1.65 V to 5.5 V 0.1 2 SCL, SDA One input at VCCI – 0.6 V, Other inputs at VCCI or GND P port, ADDR, RESET One input at VCCP – 0.6 V, Other inputs at VCCP or GND SCL VI = VCCI or GND SDA VIO = VCCI or GND P port VIO = VCCP or GND ICC (ICCI + ICCP) ΔICCI ΔICCP CI Cio (1) 14 V 0.24 VOL = 0.4 V II V V SDA IOL UNIT V 1 1.65 V MAX mA 15 ±0.1 1.65 V to 5.5 V ±0.1 1.65 V to 5.5 V µA 1 µA 1 µA µA 25 µA 1.65 V to 5.5 V 60 1.65 V to 5.5 V 1.65 V to 5.5 V 6 7 7 8 7.5 8.5 pF pF Except for ICC, all typical values are at nominal supply voltage (1.8-V, 2.5-V, 3.3-V, or 5-V VCC) and TA = 25°C. For ICC, the typical values are at VCCP = VCCI = 3.3 V and TA = 25°C. Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): TCA6416 TCA6416 www.ti.com ........................................................................................................................................ SCPS153A – DECEMBER 2007 – REVISED FEBRUARY 2009 I2C INTERFACE TIMING REQUIREMENTS over recommended operating free-air temperature range (unless otherwise noted) (see Figure 10) STANDARD MODE I2C BUS MIN MAX 100 FAST MODE I2C BUS UNIT MIN MAX 0 400 fscl I2C clock frequency 0 tsch I2C clock high time 4 0.6 µs tscl I2C clock low time 4.7 1.3 µs 2 tsp I C spike time tsds I2C serial data setup time tsdh I2C serial data hold time ticr I2C input rise time 0 50 0 250 100 0 0 2 50 kHz ns ns ns 1000 20 + 0.1Cb (1) 300 (1) 300 ns 300 µs ticf I C input fall time 300 20 + 0.1Cb tocf I2C output fall time; 10 pF to 400 pF bus 300 20 + 0.1Cb (1) tbuf I2C bus free time between Stop and Start ns 4.7 1.3 µs tsts I C Start or repeater Start condition setup time 4.7 0.6 µs tsth I2C Start or repeater Start condition hold time 4 0.6 µs tsps I2C Stop condition setup time 4 0.6 µs tvd(data) Valid data time; SCL low to SDA output valid 1 1 µs tvd(ack) Valid data time of ACK condition; ACK signal from SCL low to SDA (out) low 1 1 µs (1) 2 Cb = total capacitance of one bus line in pF RESET TIMING REQUIREMENTS over recommended operating free-air temperature range (unless otherwise noted) (see Figure 13) STANDARD MODE I2C BUS MIN MAX FAST MODE I2C BUS MIN UNIT MAX tW Reset pulse duration 4 4 ns tREC Reset recovery time 0 0 ns 600 600 ns tRESET Time to reset (1) (1) Minimum time for SDA to become high or minimum time to wait before doing a START Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): TCA6416 15 TCA6416 SCPS153A – DECEMBER 2007 – REVISED FEBRUARY 2009 ........................................................................................................................................ www.ti.com SWITCHING CHARACTERISTICS over recommended operating free-air temperature range, CL ≤ 100 pF (unless otherwise noted) (see Figure 10) PARAMETER FROM TO STANDARD MODE I2C BUS MIN FAST MODE I2C BUS MAX MIN UNIT MAX tIV Interrupt valid time P port INT 4 4 µs tIR Interrupt reset delay time SCL INT 4 4 µs tPV Output data valid SCL P7–P0 400 400 ns tPS Input data setup time P port SCL 0 0 ns tPH Input data hold time P port SCL 300 300 ns 16 Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): TCA6416 TCA6416 www.ti.com ........................................................................................................................................ SCPS153A – DECEMBER 2007 – REVISED FEBRUARY 2009 TYPICAL CHARACTERISTICS TA = 25°C (unless otherwise noted) SUPPLY CURRENT vs TEMPERATURE 60 50 VCC = 3.3 V 40 30 VCC = 2.5 V 20 VCC = 1.8 V 10 -15 6 VCC = 3.3 V 5 VCC = 2.5 V 4 3 2 1 10 35 60 85 60 0 1.65 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 85 TA = –40°C TA = 85°C 2 50 VCC = 2.5 V 22 20 4 18 TA = 25°C 16 14 12 10 8 TA = 85°C 6 4 0.2 0.3 0.4 0.5 TA = 25°C 30 25 20 15 TA = 85°C 10 0.1 0.2 0.3 0.4 0.5 0.6 0 0.1 0.2 0.3 0.4 0.5 Output Low Voltage, VOL (V) Output Low Voltage, VOL (V) Output Low Voltage, VOL (V) I/O SINK CURRENT vs OUTPUT LOW VOLTAGE I/O LOW VOLTAGE vs TEMPERATURE I/O SOURCE CURRENT vs OUTPUT HIGH VOLTAGE 400 TA = –40°C 40 TA = 25°C 30 25 20 15 10 TA = 85°C 5 0 0.1 0.2 0.3 0.4 0.5 Output Low Voltage, VOL (V) 0.6 20 VCC = 1.8 V 350 Source Current, ISOURCE (mA) Output Low Voltage, VOL (mV) VCC = 5 V 0 35 0 0 0.6 TA = –40°C 40 5 0 0.1 VCC = 3.3 V 45 TA = –40°C 2 0 35 20 I/O SINK CURRENT vs OUTPUT LOW VOLTAGE 6 45 30 I/O SINK CURRENT vs OUTPUT LOW VOLTAGE 8 50 40 I/O SINK CURRENT vs OUTPUT LOW VOLTAGE 10 0 50 Supply Voltage, VCC (V) TA = 25°C 12 35 60 Temperature, TA (°C) 16 14 10 70 Temperature, TA (°C) VCC = 1.8 V 18 –15 80 10 VCC = 1.8 V 0 –40 fSCL = 400 kHz All I/Os unloaded 90 VCC = 5 V 7 24 20 Sink Current, ISINK (mA) 8 100 SCL = VCC All I/Os unloaded Supply Current, ICC (µA) Supply Current, ICC (µA) VCC = 5 V 70 Sink Current, ISINK (mA) Supply Current, ICC (µA) 80 0 -40 Sink Current, ISINK (mA) 9 fSCL = 400 kHz All I/Os unloaded 90 SUPPLY CURRENT vs SUPPLY VOLTAGE Sink Current, ISINK (mA) 100 STANDBY SUPPLY CURRENT vs TEMPERATURE VCC = 5 V, ISINK = 10 mA 300 250 200 150 100 50 0 −40 VCC = 1.8 V, ISINK = 10 mA VCC = 5 V, ISINK = 1 mA VCC = 1.8 V, ISINK = 1 mA TA = –40°C 16 TA = 25°C 12 8 TA = 85°C 4 0 −15 10 35 60 Temperature, TA (°C) 85 0 0.1 0.2 0.3 0.4 0.5 Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): TCA6416 0.6 0.7 VCC – VOH (V) 17 TCA6416 SCPS153A – DECEMBER 2007 – REVISED FEBRUARY 2009 ........................................................................................................................................ www.ti.com TYPICAL CHARACTERISTICS (continued) TA = 25°C (unless otherwise noted) I/O SOURCE CURRENT vs OUTPUT HIGH VOLTAGE I/O SOURCE CURRENT vs OUTPUT HIGH VOLTAGE 50 50 VCC = 2.5 V VCC = 3.3 V 45 Source Current, ISOURCE (mA) TA = –40°C 20 TA = 25°C 15 10 TA = 85°C 5 TA = –40°C 40 35 TA = 25°C 30 25 20 15 TA = 85°C 10 5 0 0.1 0.2 0.3 0.4 0.5 0.6 0 0.7 TA = –40°C 40 TA = 25°C 35 30 25 20 15 TA = 85°C 10 5 0 0 0 VCC = 5 V 45 Source Current, ISOURCE (mA) 25 Source Current, ISOURCE (mA) I/O SOURCE CURRENT vs OUTPUT HIGH VOLTAGE 0.1 0.2 0.3 0.4 0.6 0.7 0.5 0.1 0.2 0.3 0.4 0.5 0.6 VCC – VOH (V) VCC – VOH (V) VCC – VOH (V) 0 I/O HIGH VOLTAGE vs TEMPERATURE 5 VCC – VOH (V) 4 3 VCC = 1.8 V, ISOURCE = 10 mA 2 1 VCC = 5 V, ISOURCE = 10 mA 0 −40 −15 10 35 60 85 Temperature, TA (°C) 18 Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): TCA6416 TCA6416 www.ti.com ........................................................................................................................................ SCPS153A – DECEMBER 2007 – REVISED FEBRUARY 2009 PARAMETER MEASUREMENT INFORMATION VCCI R L = 1 kW SDA DUT CL = 50 pF (see Note A) SDA LOAD CONFIGURATION Two Bytes for READ Input Port Register (see Figure 9) Address Bit 7 (MSB) Stop Start Condition Condition (P) (S) tscl Address Bit 1 R/W Bit 0 (LSB) Data Bit 7 (MSB) ACK (A) Data Bit 0 (LSB) Stop Condition (P) tsch 0.7 ´ VCCI SCL 0.3 ´ VCCI ticr ticf tbuf tvd tsp tvd tocf tsts tsps SDA 0.7 ´ VCCI 0.3 ´ VCCI ticr ticf tsth tsdh tsds tvd(ack) Repeat Start Condition Stop Condition VOLTAGE WAVEFORMS BYTE DESCRIPTION 2 1 I C address 2 Input register port data A. CL includes probe and jig capacitance. tocf is measured with CL of 10 pF or 400 pF. B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns. C. All parameters and waveforms are not applicable to all devices. Figure 10. I2C Interface Load Circuit and Voltage Waveforms Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): TCA6416 19 TCA6416 SCPS153A – DECEMBER 2007 – REVISED FEBRUARY 2009 ........................................................................................................................................ www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) VCCI RL = 4.7 kW INT DUT CL = 100 pF (see Note A) INTERRUPT LOAD CONFIGURATION ACK From Slave Start Condition 8 Bits (One Data Byte) From Port R/W Slave Address S 0 1 0 0 0 0 AD DR 1 A 1 2 3 4 5 6 7 8 A Data 1 ACK From Slave Data From Port A Data 2 1 P A tir tir B B INT tiv A tsps A Data Into Port Address Data 1 0.5 ´ VCCI INT SCL Data 2 0.7 ´ VCCI R/W tiv A 0.3 ´ VCCI tir 0.5 ´ VCCP Pn 0.5 ´ VCCI INT View A−A View B−B A. CL includes probe and jig capacitance. B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns. C. All parameters and waveforms are not applicable to all devices. Figure 11. Interrupt Load Circuit and Voltage Waveforms 20 Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): TCA6416 TCA6416 www.ti.com ........................................................................................................................................ SCPS153A – DECEMBER 2007 – REVISED FEBRUARY 2009 PARAMETER MEASUREMENT INFORMATION (continued) Pn 500 W DUT 2 ´ VCCP CL = 50 pF (see Note A) 500 W P-PORT LOAD CONFIGURATION SCL P0 A P3 0.7 ´ VCCP 0.3 ´ VCCI Slave ACK SDA tpv (see Note B) Pn Unstable Data Last Stable Bit WRITE MODE (R/W = 0) SCL 0.7 ´ VCCI P0 A tps P3 0.3 ´ VCCI tph Pn 0.5 ´ VCCP READ MODE (R/W = 1) A. CL includes probe and jig capacitance. B. tpv is measured from 0.7 × VCC on SCL to 50% I/O (Pn) output. C. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns. D. The outputs are measured one at a time, with one transition per measurement. E. All parameters and waveforms are not applicable to all devices. Figure 12. P Port Load Circuit and Timing Waveforms Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): TCA6416 21 TCA6416 SCPS153A – DECEMBER 2007 – REVISED FEBRUARY 2009 ........................................................................................................................................ www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) VCCI RL = 1 kW Pn SDA 500 W DUT DUT CL = 50 pF (see Note A) SDA LOAD CONFIGURATION 2 ´ VCCP CL = 50 pF (see Note A) 500 W P-PORT LOAD CONFIGURATION Start SCL ACK or Read Cycle SDA 0.3 ´ VCCI tRESET VCCP/2 RESET tREC tREC tW VCCP/2 Pn tRESET A. CL includes probe and jig capacitance. B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns. C. The outputs are measured one at a time, with one transition per measurement. D. I/Os are configured as inputs. E. All parameters and waveforms are not applicable to all devices. Figure 13. Reset Load Circuits and Voltage Waveforms 22 Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): TCA6416 TCA6416 www.ti.com ........................................................................................................................................ SCPS153A – DECEMBER 2007 – REVISED FEBRUARY 2009 APPLICATION INFORMATION Figure 14 shows an application in which the TCA6416 can be used. VCCI VCCP 10 kW (x 7) VCCI (1.8 V) 10 kW VCC 10 kW 10 kW 22 SCL Master Controller SDA 23 1 INT GND 2 VCCI 10 kW 3 RESET SCL 24 VCCP P00 Device address configured as 0100000 for this example. B. P00 and P02–P10 are configured as inputs. C. P01 and P11–P17 are configured as outputs. 4 A SDA INT P01 5 ENABLE RESET P02 P03 P04 TCA6416 P05 P06 P07 P10 P11 P12 P13 21 ADDR P14 P15 P16 P17 GND 12 A. ALARM (See Note E) Subsystem 1 (e.g., Alarm) 6 7 8 9 10 11 13 14 15 16 17 18 19 20 B Keypad D. Pin numbers shown are for the PW package. E. Resistors are required for inputs (on P port) that may float. If a driver to an input will never let the input float, a resistor is not needed. Outputs (in the P port) do not need pullup resistors. Figure 14. Typical Application Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): TCA6416 23 TCA6416 SCPS153A – DECEMBER 2007 – REVISED FEBRUARY 2009 ........................................................................................................................................ www.ti.com Minimizing ICC When I/Os Control LEDs When the I/Os are used to control LEDs, normally they are connected to VCC through a resistor as shown in Figure 14. The LED acts as a diode so, when the LED is off, the I/O VIN is about 1.2 V less than VCC. The ΔICC parameter in Electrical Characteristics shows how ICC increases as VIN becomes lower than VCC. Designs that must minimize current consumption, such as battery power applications, should consider maintaining the I/O pins greater than or equal to VCC when the LED is off. Figure 15 shows a high-value resistor in parallel with the LED. Figure 16 shows VCC less than the LED supply voltage by at least 1.2 V. Both of these methods maintain the I/O VIN at or above VCC and prevent additional supply current consumption when the LED is off. VCC LED 100 kW VCC Px Figure 15. High-Value Resistor in Parallel With the LED 3.3 V 5V LED VCC Px Figure 16. Device Supplied by a Low Voltage Power-On Reset Requirements In the event of a glitch or data corruption, TCA6416 can be reset to its default conditions by using the power-on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This reset also happens when the device is powered on for the first time in an application. The two types of power-on reset are shown in Figure 17 and Figure 18. VCC Ramp-Up Ramp-Down Re-Ramp-Up VCC_TRR_GND Time VCC_RT VCC_FT Time to Re-Ramp VCC_RT Figure 17. VCC is Lowered Below 0.2 V or 0 V and Then Ramped Up to VCC 24 Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): TCA6416 TCA6416 www.ti.com ........................................................................................................................................ SCPS153A – DECEMBER 2007 – REVISED FEBRUARY 2009 VCC Ramp-Down Ramp-Up VCC_TRR_VPOR50 VIN drops below POR levels Time Time to Re-Ramp VCC_FT VCC_RT Figure 18. VCC is Lowered Below the POR Threshold, Then Ramped Back Up to VCC Table 2 specifies the performance of the power-on reset feature for TCA6416 for both types of power-on reset. Table 2. RECOMMENDED SUPPLY SEQUENCING AND RAMP RATES (1) MAX UNIT VCC_FT Fall rate PARAMETER See Figure 17 1 100 ms VCC_RT Rise rate See Figure 17 0.01 100 ms VCC_TRR_GND Time to re-ramp (when VCC drops to GND) See Figure 17 0.001 ms VCC_TRR_POR50 Time to re-ramp (when VCC drops to VPOR_MIN – 50 mV) See Figure 18 0.001 ms VCC_GH Level that VCCP can glitch down to, but not cause a functional disruption when VCCX_GW = 1 µs See Figure 19 VCC_GW Glitch width that will not cause a functional disruption when VCCX_GH = 0.5 × VCCx See Figure 19 VPORF Voltage trip point of POR on falling VCC 0.767 1.144 V VPORR Voltage trip point of POR on fising VCC 1.033 1.428 V (1) MIN TYP 1.2 V µs TA = –40°C to 85°C (unless otherwise noted) Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width (VCC_GW) and height (VCC_GH) are dependent on each other. The bypass capacitance, source impedance, and device impedance are factors that affect power-on reset performance. Figure 19 and Table 2 provide more information on how to measure these specifications. VCC VCC_GH Time VCC_GW Figure 19. Glitch Width and Glitch Height VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition is released and all the registers and the I2C/SMBus state machine are initialized to their default states. The value of VPOR differs based on the VCC being lowered to or from 0. Figure 20 and Table 2 provide more details on this specification. Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): TCA6416 25 TCA6416 SCPS153A – DECEMBER 2007 – REVISED FEBRUARY 2009 ........................................................................................................................................ www.ti.com VCC VPOR VPORF Time POR Time Figure 20. VPOR 26 Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): TCA6416 PACKAGE OPTION ADDENDUM www.ti.com 21-Apr-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing TCA6416PW ACTIVE TSSOP PW 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TCA6416PWG4 ACTIVE TSSOP PW 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TCA6416PWR ACTIVE TSSOP PW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TCA6416PWRG4 ACTIVE TSSOP PW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TCA6416PWT ACTIVE TSSOP PW 24 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TCA6416PWTG4 ACTIVE TSSOP PW 24 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TCA6416RTWR ACTIVE QFN RTW 24 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TCA6416RTWT ACTIVE QFN RTW 24 250 CU NIPDAU Level-2-260C-1 YEAR TCA6416ZQSR ACTIVE ZQS 24 2500 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM BGA MI CROSTA R JUNI OR Pins Package Eco Plan (2) Qty Green (RoHS & no Sb/Br) Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 30-Jul-2010 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing TCA6416PWR TSSOP PW 24 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 16.4 6.95 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 8.3 1.6 8.0 16.0 Q1 TCA6416PWT TSSOP PW 24 250 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1 TCA6416RTWR QFN RTW 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 TCA6416RTWT QFN RTW 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 ZQS 24 2500 330.0 12.4 3.3 3.3 1.6 8.0 12.0 Q1 TCA6416ZQSR BGA MI CROSTA R JUNI OR Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 30-Jul-2010 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TCA6416PWR TSSOP PW 24 2000 346.0 346.0 33.0 TCA6416PWT TSSOP PW 24 250 346.0 346.0 33.0 TCA6416RTWR QFN RTW 24 3000 346.0 346.0 29.0 TCA6416RTWT QFN RTW 24 250 190.5 212.7 31.8 TCA6416ZQSR BGA MICROSTAR JUNIOR ZQS 24 2500 340.5 338.1 20.6 Pack Materials-Page 2 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. 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