Typical Size 6,4 mm X 9,7 mm TPS54073 www.ti.com SLVS547 – FEBRUARY 2005 2.2 – 4 -V, 14-A SYNCHRONOUS BUCK CONVERTER WITH DISABLED SINKING DURING START-UP FEATURES • • • • • • • • DESCRIPTION 8-mΩ MOSFET Switches for High Efficiency at 14.5-A Peak Output Current Separate Low-Voltage Power Bus Disabled Current Sinking During Start-Up Adjustable Output Voltage Down to 0.9 V Wide PWM Frequency: Fixed 350 kHz, 550 kHz or Adjustable 280 kHz to 700 kHz Synchronizable to 700 kHz Load Protected by Peak Current Limit and Thermal Shutdown Integrated Solution Reduces Board Area and Total Cost APPLICATIONS • • • • Low-Voltage, High-Density Distributed Power Systems Point of Load Regulation for HighPerformance DSPs, FPGAs, ASICs, and Microprocessors Broadband, Networking, and Optical Communications Infrastructure Power PC Series Processors As a member of the SWIFT™family of dc/dc regulators, the TPS54073 low-input voltage high-output current synchronous buck PWM converter integrates all required active components. Included on the substrate with the listed features are a true, high performance, voltage error amplifier that enables maximum performance and flexibility in choosing the output filter L and C components; an undervoltage-lockout circuit to prevent start-up until the input voltage reaches 3 V; an internally or externally set slow-start circuit to limit in-rush currents; and a power good output useful for processor/logic reset, fault signaling, and supply sequencing. For reliable power up in output precharge applications, the TPS54073 is designed to only source current during start-up. The TPS54073 is available in a thermally enhanced 28-pin TSSOP (PWP) PowerPAD™ package, which eliminates bulky heatsinks. TI provides evaluation modules and the SWIFT™ designer software tool to aid in quickly achieving high-performance power supply designs to meet aggressive equipment development cycles START-UP WAVEFORM WITH 3 PRECHARGE DIODES TYPICAL APPLICATION * Voltage Input 2 * RL = 1.5 W Output PVIN PH TPS54073 BOOT PGND VIN VBIAS VSENSE AGND COMP VI/O = 3.3 V 500 mV/div Voltage Input 1 * V(core) = 1.5 V * Optional t - Time - 5 ms/div Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SWIFT, PowerPAD are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005, Texas Instruments Incorporated TPS54073 www.ti.com SLVS547 – FEBRUARY 2005 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION (1) TA OUTPUT VOLTAGE PACKAGE PART NUMBER -40°C to 85°C Adjustible down to 0.9 V Plastic HTSSOP (PWP) (1) TPS54073PWP The PWP package is also available taped and reeled. Add an R suffix to the device type (i.e., TPS54073PWPR). See the application section of the data sheet for PowerPAD drawing and layout information. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) TPS54073 VI Input voltage range VO Output voltage range VO Source current IS Sink current SS/ENA, SYNC –0.3 to 7 RT –0.3 to 6 VSENSE –0.3 to 4 PVIN, VIN –0.3 to 4.5 BOOT –0.3 to 10 VBIAS, COMP, PWRGD –0.3 to 7 PH –0.6 to 6 V V PH Internally limited COMP, VBIAS 6 PH 25 A COMP 6 mA SS/ENA, PWRGD Voltage differential UNIT mA 10 AGND to PGND ±0.3 V TJ Operating junction temperature range –40 to 125 °C Tstg Storage temperature range –65 to 150 °C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds °C 1 kV 1000 V Human body model (HBM) Electrostatic Discharge (ESD) ratings (1) 300 CDM Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS MIN VI TJ Input voltage, VIN NOM MAX UNIT 3 4 Power Input voltage, PVIN 2.2 4 V V Operating junction temperature –40 125 °C DISSIPATION RATINGS (1) (2) (1) (2) (3) 2 PACKAGE THERMAL IMPEDANCE JUNCTION-TO-AMBIENT TA = 25°C POWER RATING TA = 70°C POWER RATING TA = 85°C POWER RATING 28-Pin PWP with solder 14.87°C/W 6.72 W (3) 3.69 W 2.69 W For more information on the PWP package, see TI technical brief, literature number SLMA002. Test board conditions: a. 3 inch x 3 inch, 4 layers, thickness = 0.062 inch b. 2-ounce copper traces located on die top of the PCB. c. 2-ounce copper mixed plane and traces on the bottom of the PCB. d. 2-ounce copper ground planes on the two internal layers of the PCB. e. 12 thermal vias (see the Figure 11 in the Application Section of this data sheet. Maximum power dissipation may be limited by over current protection. TPS54073 www.ti.com SLVS547 – FEBRUARY 2005 DISSIPATION RATINGS (continued) PACKAGE THERMAL IMPEDANCE JUNCTION-TO-AMBIENT TA = 25°C POWER RATING TA = 70°C POWER RATING TA = 85°C POWER RATING 28-Pin PWP without solder (4) 27.9°C/W 3.58 W 1.97 W 1.43 W ELECTRICAL CHARACTERISTICS TJ = -40°C to 125°C, VIN = 3 V to 4 V, PVIN = 2.2 V to 4 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY VOLTAGE, VIN VI Input voltage, VIN Supply voltage range, PVIN VIN = 3.3 V IQ Output = 1.8 V 3 4 V 2.2 4 V fs = 350 kHz, RT open, PH pin open, SYNC = 0 V, PVIN = 2.5 V 6.3 10 mA fs = 550 kHz, RT open, PH pin open, SYNC ≥ 2.5 V, PVIN = 2.5 V 8.6 13 mA SHUTDOWN, SS/ENA = 0 V, PVIN = 2.5 V Quiescent current PVIN = 2.5 V 1 1.4 mA fs = 350 kHz, RT open, PH pin open, SYNC = 0 V, VIN = 3.3 V 3.2 6 mA fs = 550 kHz, RT open, PH pin open, SYNC ≥ 2.5 V, VIN = 3.3 V 4.4 7 mA SHUTDOWN, SS/ENA = 0 V, VIN = 3.3 V < 140 µA UNDERVOLTAGE LOCKOUT (VIN) Start threshold voltage, UVLO 2.9 Stop threshold voltage, UVLO 2.7 3 V 2.8 V Hysteresis voltage, UVLO 100 mV Rising and falling edge deglitch, UVLO (1) 2.5 µs BIAS VOLTAGE Output voltage, VBIAS I(VBIAS) = 0 2.7 2.8 Output current, VBIAS (2) 2.9 V 100 µA 0.900 V CUMULATIVE REFERENCE Vref Accuracy 0.882 0.891 REGULATION Line regulation (1) (3) IL = 7 A, fs = 350 kHz, TJ = 85°C Load regulation (1) (3) IL = 0 A to 14 A, fs = 350 kHz, TJ = 85°C PVIN = 2.5 V, VIN = 3.3 V 0.05 %/V 0.013 %/A OSCILLATOR Internally set—free running frequency Externally set—free running frequency range High-level threshold voltage, SYNC RT open (1), SYNC ≤ 0.8 V 280 350 420 RT open (1), SYNC ≥ 2.5 V 440 550 660 RT = 180 kΩ (1% resistor to AGND) (1) 252 280 308 RT = 100 kΩ (1% resistor to AGND) 460 500 540 RT = 68 kΩ (1% resistor to AGND) (1) 663 700 762 2.5 0.8 50 Frequency range, SYNC 300 Ramp valley (1) Maximum duty cycle (1) (4) (1) (2) (3) 700 kHz V 1 Minimum controllable on time (1) V ns 0.75 Ramp amplitude (peak-to-peak) (1) kHz V Low-level threshold voltage, SYNC Pulse duration, SYNC (1) kHz V 200 ns 90% Estimated performance Specified by design Static resistive loads only Specified by the circuit used in Figure 12 3 TPS54073 www.ti.com SLVS547 – FEBRUARY 2005 ELECTRICAL CHARACTERISTICS (continued) TJ = -40°C to 125°C, VIN = 3 V to 4 V, PVIN = 2.2 V to 4 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ERROR AMPLIFIER Error amplifier open-loop voltage gain 1 kΩ COMP to AGND (4) 90 110 Error amplifier unity gain bandwidth Parallel 10 kΩ, 160 pF COMP to AGND (4) 3 5 Error amplifier common mode input voltage range Powered by internal LDO (4) 0 Input bias current, VSENSE VSENSE = Vref VBIAS 60 Output voltage slew rate (symmetric), COMP 1 dB MHz 250 1.4 V nA V/µs PWM COMPARATOR PWM comparator propagation delay time, PWM comparator input to PH pin (excluding deadtime) 10-mV overdrive (4) 70 85 ns 1.2 1.4 V SLOW-START/ENABLE Enable threshold voltage, SS/ENA 0.82 Enable hysteresis voltage, SS/ENA (4) Falling edge deglitch, SS/ENA (4) Internal slow-start time Charge current, SS/ENA SS/ENA = 0 V Discharge current, SS/ENA SS/ENA = 0.2 V, VIN = 2.7 V, PVIN = 2.5 V 0.03 V 2.5 µs 2.6 3.35 4.1 2 5 8 ms µA 1.3 2.3 4 mA POWER GOOD Power-good threshold voltage VSENSE falling Power-good hysteresis voltage (4) Power-good falling edge deglitch (4) 93 %Vref 3 %Vref 35 Output saturation voltage, PWRGD I(sink) = 2.5 mA Leakage current, PWRGD VIN = 3.3 V, PVIN = 2.5 V 0.18 µs 0.3 V 1 µA CURRENT LIMIT Current limit Current limit leading edge blanking VIN = 3.3 V, PVIN = 2.5 V (4), Output shorted 14.5 time (4) Current limit total response time (4) 21 A 100 ns 200 ns 165 °C 10 °C THERMAL SHUTDOWN Thermal shutdown trip point (4) 135 Thermal shutdown hysteresis (4) OUTPUT POWER MOSFETS rDS(on) (4) 4 Power MOSFET switches Specified by design VIN = 3 V, PVIN = 2.5 V 8 21 VIN = 3.6 V, PVIN = 2.5 V 8 18 mΩ TPS54073 www.ti.com SLVS547 – FEBRUARY 2005 DEVICE INFORMATION PWP PACKAGE (TOP VIEW) AGND VSENSE COMP PWRGD BOOT PH PH PH PH PH PH PH PH PH 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 THERMAL 22 PAD 21 20 19 18 17 16 15 RT SYNC SS/ENA VBIAS VIN PVIN PVIN PVIN PVIN PGND PGND PGND PGND PGND TERMINAL FUNCTIONS PIN NAME PIN NUMBER DESCRIPTION AGND 1 Analog ground. Return for compensation network/output divider, slow-start capacitor, VBIAS capacitor, and RT resistor. If using the PowerPAD, connect it to AGND. See the Application Information section for details. BOOT 5 Bootstrap output. 0.022-µF to 0.1-µF low-ESR capacitor connected from BOOT to PH generates floating drive for the high-side FET driver. COMP 3 Error amplifier output. Connect frequency compensation network from COMP to VSENSE PGND 15, 16, 17, 18, 19 PH 6-14 Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper areas to the input and output supply returns, and negative terminals of the input and output capacitors. A single point connection to AGND is recommended. Phase output. Junction of the internal high-side and low-side power MOSFETs, and output inductor. 20, 21, 22, 23 Input supply for the power MOSFET switches and internal bias regulator. Bypass the PVIN pins to the PGND pins close to device package with a high-quality, low-ESR 10-µF ceramic capacitor. PWRGD 4 Power-good open-drain output. High when VSENSE > 90% Vref, otherwise PWRGD is low. Note that output is low when SS/ENA is low or the internal shutdown signal is active. RT 28 Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency, fs. SS/ENA 26 Slow-start/enable input/output. Dual function pin which provides logic input to enable/disable device operation and capacitor input to externally set the start-up time. SYNC 27 Synchronization input. Dual function pin which provides logic input to synchronize to an external oscillator or pin select between two internally set switching frequencies. When used to synchronize to an external signal, a resistor must be connected to the RT pin. VBIAS 25 Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with a high-quality, low-ESR 0.1-µF to 1.0-µF ceramic capacitor. VIN 24 Input supply for the internal control circuits. Bypass the VIN pin to the PGND pins close to device package with a high-quality, low-ESR 1-µF ceramic capacitor. VSENSE 2 Error amplifier inverting input. Connect to output voltage compensation network/output divider. PVIN 5 TPS54073 www.ti.com SLVS547 – FEBRUARY 2005 FUNCTIONAL BLOCK DIAGRAM VBIAS AGND VIN SS/ENA Falling Edge Deglitch 1.2 V Hysteresis: 0.03 V 2.5 µs VIN UVLO Comparator VIN 2.95 V Hysteresis: 0.11 V PVIN ILIM Comparator Thermal Shutdown 150°C 2.2 − 4.0 V Leading Edge Blanking 100 ns SHUTDOWN BOOT 2.5 µs Start−Up Driver Suppression SS_DIS 8 mΩ PH + − R Q Error Amplifier Reference VREF = 0.891 V 3.0 − 4.0 V SHUTDOWN Falling and Rising Edge Deglitch Internal/External Slow-start (Internal Slow-start Time = 3.35 ms VIN REG VBIAS Enable Comparator S PWM Comparator CO Adaptive Dead-Time and Control Logic VIN 8 mΩ OSC PGND Power-Good Comparator PWRGD VSENSE Falling Edge Deglitch 0.90 Vref TPS54073 Hysteresis: 0.03 Vref VSENSE 6 COMP RT SYNC SHUTDOWN LOUT 35 µs VO TPS54073 www.ti.com SLVS547 – FEBRUARY 2005 TYPICAL CHARACTERISTICS DRAIN-SOURCE ON-STATE RESISTANCE vs JUNCTION TEMPERATURE DRAIN-SOURCE ON-STATE RESISTANCE vs JUNCTION TEMPERATURE VIN = 3.6 V, PVIN = 2.5 V, IO = 9 A 10 8 6 4 2 0 -40 VIN = 3.3 V, PVIN = 2.5 V, IO = 9 A 10 8 6 4 2 0 -20 0 20 40 60 80 100 125 -40 650 SYNC ≥ 2.5 V 550 450 SYNC ≤ 0.8 V 350 250 −40 0 25 85 125 TJ − Junction Temperature − °C Figure 1. Figure 2. Figure 3. EXTERNALLY SET OSCILLATOR FREQUENCY vs JUNCTION TEMPERATURE VOLTAGE REFERENCE vs JUNCTION TEMPERATURE DEVICE POWER DISSIPATION vs OUTPUT CURRENT 5 0.895 800 o TA = 25 C 4.5 RT = 68 kΩ 600 500 RT = 100 kΩ 400 300 0.893 PD - Power Dissipation - W 700 V ref − Voltage Reference − V 0.891 0.889 0.887 RT = 180 kΩ 0 25 85 125 −40 TJ − Junction Temperature − °C 2 1.5 1 0 25 85 TJ − Junction Temperature − °C 0 125 2 4 6 8 10 12 14 16 I O - Output Current - A Figure 4. Figure 5. Figure 6. REFERENCE VOLTAGE vs INPUT VOLTAGE ERROR AMPLIFIER OPEN-LOOP RESPONSE INTERNAL SLOWS-START TIME vs JUNCTION TEMPERATURE RL = 10 kΩ, CL = 160 pF, TA = 25°C 120 0.893 3.80 0 140 PVIN = 2.5 V −40 100 Gain − dB −60 0.891 0.889 80 Phase −80 −100 60 −120 40 Gain 20 −140 −160 0.887 0.885 0 −180 −20 −200 1 k 10 k 100 k 1 M 10 M 1 3.1 3.2 3.3 3.4 VI − Input Voltage − V Figure 7. 3.5 3.6 10 100 f − Frequency − Hz Figure 8. VIN = 3.3 V, PVIN = 2.5 V −20 Internal Slow-Start Time − ms 0.895 3 3 2.5 0 0.885 200 −40 4 3.5 0.5 Phase − Degrees f − Externally Set Oscillator Frequency − kHz 750 -20 0 20 40 60 80 100 125 TJ - Junction Temperature - oC TJ - Junction Temperature - oC VO − Output Voltage Regulation − V f − Internally Set Oscillator Frequency − kHz 12 Drain-Source On-State Resistance - mW Drain-Source On-State Resistance - mW 12 INTERNALLY SET OSCILLATOR FREQUENCY vs JUNCTION TEMPERATURE 3.65 3.50 3.35 3.20 3.05 2.90 2.75 −40 0 25 85 125 TJ − Junction Temperature − °C Figure 9. 7 TPS54073 www.ti.com SLVS547 – FEBRUARY 2005 APPLICATION INFORMATION PCB LAYOUT OPTIONAL PRE-CHARGE DIODES CONNECT TO PRE-CHARGE VOLTAGE SOURCE ANALOG GROUND TRACE FREQUENCY SET RESISTOR AGND RT VSENSE COMPENSATION NETWORK COMP SYNC SLOW START CAPACITOR INPUT BYPASS CAPACITOR SS/ENA BIAS CAPACITOR PWRGD BOOT CAPACITOR OUTPUT INDUCTOR OUTPUT FILTER CAPACITOR VIN BOOT PH EXPOSED POWERPAD PVIN AREA PH PVIN PH PVIN PH PVIN PH PGND PH PGND PH PGND PH PGND PH PGND VOUT PH VBIAS VIN PVIN INPUT BYPASS CAPACITOR INPUT BULK FILTER TOPSIDE GROUND AREA VIA to Ground Plane Figure 10. TPS54073 Layout The PVIN pins are connected together on the printedcircuit board (PCB) and bypassed with a low ESR ceramic bypass capacitor. Care should be taken to minimize the loop area formed by the bypass capacitor connections, the PVIN pins, and the TPS54073 ground pins. The minimum recommended bypass capacitance is a 10-µF ceramic capacitor with a X5R or X7R dielectric. The optimum placement is as close as possible to the PVIN pins, the AGND, and PGND pins. See Figure 10 for an example of a board layout. If the VIN is connected to a separate source supply, it is bypassed with its own capacitor. There is an area of ground on the top layer of the PCB, directly under the IC, with an exposed area for connection to the PowerPAD. Use vias to connect this ground area to any internal ground planes. Use additional vias at the 8 ground side of the input and output filter capacitors. The AGND and PGND pins are tied to the PCB ground by connecting them to the ground area under the device as shown in Figure 10. Use a separate wide trace for the analog ground signal path. This analog ground is used for the voltage set point divider, timing resistor RT, slow-start capacitor, and bias capacitor grounds. The PH pins are tied together and routed to the output inductor. Because the PH connection is the switching node, an inductor is located close to the PH pins, and the area of the PCB conductor is minimized to prevent excessive capacitive coupling. Connect the boot capacitor between the phase node and the BOOT pin as shown in Figure 10. Keep the boot capacitor close to the IC, and minimize the conductor trace lengths. Connect the TPS54073 www.ti.com SLVS547 – FEBRUARY 2005 output filter capacitor(s) between the VOUT trace and PGND. It is important to keep the loop formed by the PH pins, Lout, Cout, and PGND as small as is practical. Place the compensation components from the VOUT trace to the VSENSE and COMP pins. Do not place these components too close to the PH trace. Due to the size of the IC package and the device pinout, they must be routed close, but maintain as much separation as possible while keeping the layout compact. Connect the bias capacitor from the VBIAS pin to analog ground using the isolated analog ground trace. If a slow-start capacitor or RT resistor is used, or if the SYNC pin is used to select 350-kHz operating frequency, connect them to this trace. Optional prebias diodes should be connected between the output voltage trace and the prebias source. The source is VIN, PVIN, or some other voltage rail. This is dependent on the user's application circuit. In some cases, the diodes are not required if the prebias voltage is caused by an external load circuit leakage path. 8 PL Ø 0.0130 4 PL Ø 0.0180 For operation at full rated load current, the analog ground plane must provide an adequate heat-dissipating area. A 3-inch by 3-inch plane of 1-ounce copper is recommended, though not mandatory, depending on ambient temperature and airflow. Most applications have larger areas of internal ground plane available, and the PowerPAD must be connected to the largest area available. Additional areas on the top or bottom layers also help dissipate heat, and any area available must be used when 6-A or greater operation is desired. Connection from the exposed area of the PowerPAD to the analog ground plane layer must be made using 0.013-inch diameter vias to avoid solder wicking through the vias. Eight vias must be in the PowerPAD area with four additional vias located under the device package. The size of the vias under the package, but not in the exposed thermal pad area, can be increased to 0.018. Additional vias beyond the twelve recommended that enhance thermal performance must be included in areas not under the device package. Minimum Recommended Thermal Vias: 8 x 0.013 Diameter Inside PowerPAD Area 4 x 0.018 Diameter Under Device as Shown. Additional 0.018 Diameter Vias May Be Used if Top Side Analog Ground Area Is Extended. Connect Pin 1 to Analog Ground Plane in This Area for Optimum Performance 0.06 0.0150 0.0339 0.0650 0.0500 0.3820 0.3478 0.0500 0.0500 0.2090 0.0256 0.0650 0.0339 0.1700 0.1340 Minimum Recommended Top Side Analog Ground Area Minimum Recommended Exposed Copper Area for PowerPAD. 5mm Stencils May Require 10 Percent Larger Area 0.0630 0.0400 Figure 11. Recommended Land Pattern for 28-Pin PWP PowerPAD 9 TPS54073 www.ti.com SLVS547 – FEBRUARY 2005 Connect to Optional Precharge Voltage Figure 12. Application Circuit, 3.3 V to 1.5 V Figure 12 shows the schematic for a typical TPS54073 application. The TPS54073 provides up to 14-A output current at a nominal output voltage of 1.5 V. Nominal input voltages are 3.3 V for PVIN, and 3.3 V for VIN. For proper thermal performance, the exposed PowerPAD underneath the device must be soldered to the printed-circuit board. DESIGN PROCEDURE The following design procedure is used to select component values for the TPS54073. Alternately, the SWIFT Designer Software is used to generate a complete design. The SWIFT Designer Software uses an iterative design procedure and accesses a comprehensive database of components when generating a design. This section presents a simplified discussion of the design process. 10 DESIGN PARAMETERS To begin the design process, a few parameters must be decided. The designer needs to know: • Input voltage range • Output voltage • Input ripple voltage • Output ripple voltage • Output current rating • Operating frequency For this design example, use the following as the input parameters: DESIGN PARAMETER EXAMPLE VALUE Input voltage (VIN) 3.3 V Input voltage range (PVIN) 2.2 to 3.5 V Output voltage 1.5 V Input ripple voltage 350 mV Output ripple voltage 20 mV Output current rating 14 A Operating frequency 700 kHz TPS54073 www.ti.com SLVS547 – FEBRUARY 2005 SWITCHING FREQUENCY The switching frequency can be set to either one of two internally programmed frequencies or set to a externally programmed frequency. With the RT pin open, setting the SYNC pin at or above 2.5 V selects 550-kHz operation, while grounding or leaving the SYNC pin open selects 350-kHz operation. For this design, the switching frequency is externally programmed using the RT pin. By connecting a resistor (R4) from RT to AGND, any frequency in the range of 250 kHz to 700 kHz can be set. Use Equation 1 to determine the proper value of RT. R4(k) 500 kHz 100 k ƒs(kHz) (1) In this example circuit, R4 is calculated to be 71.5 kΩ and the switching frequency is set at 700 kHz. for 16 V, and the ripple current capacity is greater than 3 A at the operating frequency of 700 kHz. Total ripple current handling is in excess of 10.4 A. It is important that the maximum ratings for voltage and current are not exceeded under any circumstance. OUTPUT FILTER COMPONENTS Two components need to be selected for the output filter, L1 and C2. Because the TPS54073 is an externally compensated device, a wide range of filter component types and values can be supported. Inductor Selection To calculate the minimum value of the output inductor, use Equation 4 L MIN = INPUT CAPACITORS The TPS54073 requires an input de-coupling capacitor and, depending on the application, a bulk input capacitor. The minimum value for the de-coupling capacitor, C9, is 10 µF. A high-quality ceramic type X5R or X7R is recommended. The voltage rating should be greater than the maximum input voltage. Additionally, some bulk capacitance may be needed, especially if the TPS54073 circuit is not located within approximately 2 inches from the input voltage source. The value for this capacitor is not critical but it also should be rated to handle the maximum input voltage including ripple voltage, and should filter the output so that input ripple voltage is acceptable. This input ripple voltage can be approximated by Equation 2: I 0.25 OUT(MAX) V I ESR PVIN OUT(MAX) MAX C ƒ sw BULK (2) Where IOUT(MAX) is the maximum load current. ƒsw is the switching frequency, C(BULK) is the bulk capacitor value and ESRMAX is the maximum series resistance of the bulk capacitor. The maximum RMS ripple current also needs to be checked. For worst-case conditions, this can be approximated by Equation 3: I OUT(MAX) I CIN 2 (3) In this case, the input ripple voltage would be 329 mV and the RMS ripple current would be 7 A. The maximum voltage across the input capacitors would be Vin max plus delta Vin/2. The chosen bulk capacitor, a Sanyo POSCAP 6TPD330M is rated for 6.3 V and 4.4 A of ripple current; two bypass capacitors, TDK C3225X7R1C226KT are each rated VOUT ´ (VIN(MAX) - VOUT ) VIN(MAX) ´ K IND ´ I OUT ´ FSW x 0.8 (4) KIND is a coefficient that represents the amount of inductor ripple current relative to the maximum output current. For designs using low ESR output capacitors such as ceramics, use KIND = 0.3. When using higher ESR output capacitors, KIND = 0.2 yields better results. If designing for high output currents, the minimum current limit trip point must also be taken into consideration when choosing the output inductor. The minimum current limit trip point for the TPS54073 is 14.5 A. The maximum inductor ripple current can be calculated using Equation 5: I LMAX LIMIT(MIN) I(MAX) 2 I (5) For a 14 A maximum output current, the peak-to-peak inductor ripple current must be less than 1 A. This corresponds to a KIND of 0.071 in Equation 4. FSW is the nominal switching frequency. Use 0.8 times the nominal switching frequency to account for internal variations from the set frequency. The minimum inductor value is calculated to be 1.54 µH. A 2.2-µH inductor which is slightly larger than the minimum is selected. For the output filter inductor, it is important that the RMS current and saturation current ratings not be exceeded. The RMS inductor current can be found from Equation 6: I L(RMS) I 1 V OUT V OUT(MAX) 12 2 Vin(MAX) VOUT 2 L F sw 0.8 IN(MAX) OUT (6) and the peak inductor current can be found from Equation 7 11 TPS54073 www.ti.com SLVS547 – FEBRUARY 2005 I V V V OUT x IN(MAX) x OUT I = + OUT(MAX) 1.6 x V L(PK) x L x F sw x 0.8 IN(MAX) OUT VOUT VPVIN(MAX) VOUT V L F sw PVIN(MAX) OUT I 1 COUT(RMS) 12 (7) For this design, the RMS inductor current is 14.001 A, and the peak inductor current is 14.43 A. The Vishay IHLP5050CZ-01 style output inductor with a value of 2.2 µH meets these current requirements. Increasing the inductor value decreases the ripple current and the corresponding output ripple voltage. The inductor value can be decreased if more margin in the RMS current is required. In general, inductor values for use with the TPS54073 falls in the range of 1 µH to 3.3 µH, depending on the maximum required output current. Capacitor Requirements C OUT(MIN) L OUT K 2 ƒ CO 2 (8) Where K is the frequency multiplier for the spread between fLC and fCO. K should be between 5 and 15, typically 10 for one decade difference. For a desired crossover of 40-kHz and a 2.2-µH inductor, the minimum value for the output capacitor is 304 µF using a minimum K factor of 6.5. Increasing the K factor would require using a larger capacitance. The selected output capacitor must be rated for a voltage greater than the desired output voltage plus one half the ripple voltage. Any de-rating amount must also be included. The maximum RMS ripple current in the output capacitors is given by Equation 9: 12 The calculated RMS ripple current is 201 mA in the output capacitors. The maximum ESR of the output capacitor is determined by the amount of allowable output ripple as specified in the initial design parameters. The output ripple voltage is the inductor ripple current times the ESR of the output filter; therefore, the maximum specified ESR as listed in the capacitor data is given by Equation 10 : ESR The important design factors for the output capacitor are dc voltage rating, ripple current rating, and equivalent series resistance (ESR). The dc voltage and ripple current ratings cannot be exceeded. The ESR is important because along with the inductor current it determines the amount of output ripple voltage. The actual value of the output capacitor is not critical, but some practical limits do exist. Consider the relationship between the desired closed-loop crossover frequency of the design and LC corner frequency of the output filter. In general, it is desirable to keep the closed-loop crossover frequency at less than 1/5 of the switching frequency. With high switching frequencies such as the 700 kHz frequency of this design, internal circuit limitations of the TPS54073 limit the practical maximum crossover frequency to about 70 kHz. To allow for adequate phase gain in the compensation network, the LC corner frequency should be about one decade or so below the closed-loop crossover frequency. This limits the minimum capacitor value for the output filter to: 1 (9) VIN(MAX) LOUT F sw 0.8 VPP(MAX) VOUT VIN(MAX) VOUT N MAX C (10) and the maximum ESR required is 29 mΩ. A capacitor that meets these requirements is a Cornell Sanyo POSCAP 6TPD33M rated at 6.3 V with a maximum ESR of 0.015 Ω and a ripple current rating of 2 A. An additional small 0.1-µF ceramic bypass capacitor C13 is a also used. Other capacitor types work well with the TPS54073, depending on the needs of the application. Compensation Components The external compensation used with the TPS54073 allows for a wide range of output filter configurations. A large range of capacitor values and types of dielectric are supported. The design example uses Type-3 compensation consisting of R1, R3, R5, C6, C7, and C8. Additionally, R2 along with R1 forms a voltage divider network that sets the output voltage. These component reference designators are the same as those used in the SWIFT Designer Software. There are a number of different ways to design a compensation network. This procedure outlines a relatively simple procedure that produces good results with most output filter combinations. Use the SWIFT Designer Software for designs with unusually high closed-loop crossover frequencies, low value, low ESR output capacitors such as ceramics or if you are unsure about the design procedure. When designing compensation networks for the TPS54073, a number of factors need to be considered. The gain of the compensated error amplifier should not be limited by the open-loop amplifier gain characteristics and should not produce excessive gain at the switching frequency. Also, the closed-loop crossover frequency should be set less than one-fifth TPS54073 www.ti.com of the switching frequency, and the phase margin at crossover must be greater than 45 degrees. The general procedure outlined here produces results consistent with these requirements without going into great detail about the theory of loop compensation. First, calculate the output filter LC corner frequency using Equation 11: 1 ƒ LC 2 L C OUT OUT (11) For the design example, fLC = 5.906 kHz. The closed-loop crossover frequency should be chosen to be greater than fLC and less than one-fifth of the switching frequency. Also, the crossover frequency should not exceed 100 kHz, as the error amplifier may not provide the desired gain. For this design, a crossover frequency of 40 kHz was chosen. This value is chosen for comparatively wide loop bandwidth while still allowing for adequate phase boost to insure stability. Next, calculate the R2 resistor value for the output voltage of 1.5 V using Equation 12: R2 R1 0.891 V 0.891 OUT (12) For any TPS54073 design, start with an R1 value of 10 kΩ. R2 is 14.7 kΩ. Now, the values for the compensation components that set the poles and zeros of the compensation network can be calculated. Assuming that R1 >> than R5 and C6 >> C7, the pole and zero locations are given by Equation 13 through Equation 20: 1 ƒ Z1 2R3C6 (13) 1 ƒ Z2 2R1C8 (14) 1 ƒ P1 2R5C8 (15) 1 ƒ P2 2R3C7 (16) Additionally, there is a pole at the origin, which has unity gain at a frequency: 1 ƒ INT 2R1C6 (17) This pole is used to set the overall gain of the compensated error amplifier and determines the closed-loop crossover frequency. Because R1 is given as 10 kΩ and the nominal crossover frequency is selected as 40 kHz, the desired fINT can be calculated from Equation 18: SLVS547 – FEBRUARY 2005 f INT = f CO ´ f Z1 ´ f Z2 2 VIN(NOM) ´ f LC (18) For this design, one zero is placed at fLC and the other at one fourth fLC, so Equation 18 simplifies to: f INT = f CO VIN(NOM) ´ 4 (19) It is important to note that these equations are only valid for the pole and zero locations as specified The value for C6 is given by Equation 20: 1 C6 2R1 ƒ INT (20) The first zero, fZ1 is located at one-half the output filter LC corner frequency; so, R3 can be calculated from: 1 R3 C6 ƒ LC (21) The second zero, fZ2 is located at the output filter LC corner frequency; so, C8 can be calculated from: 1 C8 2R1 ƒ LC (22) The first pole, fP1 is located to coincide with output filter ESR zero frequency. This frequency is given by: 1 ƒ ESR0 2R C ESR OUT (23) where RESR is the equivalent series resistance of the output capacitor. In this case, the ESR zero frequency is 48.2 kHz, and R5 can be calculated from: 1 R5 2C8 ƒ ESR (24) The final pole is placed at a frequency above the closed-loop crossover frequency high enough to not cause the phase to decrease too much at the crossover frequency while still providing enough attenuation so that there is little or no gain at the switching frequency. The fP2 pole location for this circuit is set to 150 kHz and the last compensation component value C7 can be derived: 1 C7 = 2pR3 x 150000 (25) Note that capacitors are only available in a limited range of standard values, so the nearest standard value has been chosen for each capacitor. The measured closed-loop response for this design is shown in Figure 5. 13 TPS54073 www.ti.com SLVS547 – FEBRUARY 2005 BIAS AND BOOTSTRAP CAPACITORS SNUBBER CIRCUIT Every TPS54073 design requires a bootstrap capacitor, C3, and a bias capacitor, C4. The bootstrap capacitor must be a 0.1 µF. The bootstrap capacitor is located between the PH pins and BOOT. The bias capacitor is connected between the VBIAS pin and AGND. The value should be 1.0 µF. Both capacitors should be high-quality ceramic types with X7R or X5R grade dielectric for temperature stability. They should be placed as close to the device connection pins as possible. R8 and C14 of the application schematic comprise a snubber circuit. The snubber is included to reduce over-shoot and ringing on the phase node when the internal high side FET turns on. Since the frequency and amplitude of the ringing depends to a large degree on parasitic effects, it is best to choose these component values based on actual measurements of any design layout. See literature number SLVP100 for more detailed information on snubber design DESIGN WITH CERAMIC CAPACITORS POWER GOOD The TPS54073 is provided with a power-good output pin PWRGD. This output is an open-drain output and is intended to be pulled up to a 3.3-V logic supply. A 10-kΩ pullup works well in this application. The absolute maximum voltage is 6 V, so care must be taken not to connect this pull up to Vin if the maximum input voltage exceeds 6 V. Figure 13 shows an application where all ceramic capacitors, including the main output filter capacitor, are used. The compensation network components were calculated using SWIFT Designer Software. See Figure 23 through Figure 26 for loop response, performance graphs, and switching waveforms for this circuit. Connect to Optional Precharge Voltage Figure 13. 1.5 V Power Supply With Ceramic Output Capacitors 14 TPS54073 www.ti.com SLVS547 – FEBRUARY 2005 PERFORMANCE GRAPHS The performance data for Figure 14 through Figure 22 are for the circuit in Figure 12. Conditions are PVIN = 2.5 V, VIN = 3.3 V, VO = 1.5 V, fs = 700 kHz, and IO = 7 A, TA = 25°C, unless otherwise specified. MEASURED LOOP RESPONSE vs FREQUENCY 180 Phase 40 120 30 90 20 60 Gain 10 30 0 0 -10 -30 -20 -60 -30 -90 -40 -120 -50 -150 -60 -180 1M 10 100 1k 10 k f - Frequency - Hz 100 k Output Voltage Variation - % 150 Phase - o Gain 50 LINE REGULATION vs INPUT VOLTAGE 0.5 0.3 0.4 0.25 0.3 Output Voltage Variation - % 60 LOAD REGULATION vs OUTPUT CURRENT 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 0.2 IO = 0 A 0.15 0.1 0.05 IO = 7 A 0 -0.05 IO = 14 A -0.1 -0.15 -0.2 -0.25 -0.3 -0.5 0 2 4 6 8 10 12 I O - Output Current - A 14 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 4 VO - Output Voltage - V Figure 14. Figure 15. Figure 16. EFFICIENCY vs OUTPUT CURRENT INPUT RIPPLE VOLTAGE OUTPUT VOLTAGE RIPPLE 95 90 VO (RIPPLE) = 10 mV/div (ac coupled) Efficiency - % 85 80 75 PVIN(RIPPLE) = 100 mV/div (ac coupled) 70 V(PH) = 2 V/div IO = 14 A 65 IO = 14 A V(PH) = 2 V/div 60 55 50 0 2 4 6 8 10 12 14 16 t - Time = 500 ns/div t - Time = 500 ns/div I O - Output Current - A Figure 17. Figure 18. Figure 19. LOAD TRANSIENT RESPONSE START-UP WAVEFORM WITH PRECHARGE OUTPUT INDUCTOR RIPPLE CURRENT VO (RIPPLE) = 50 mV/div (ac coupled) V (SS/ENA) = 500 mV/div IO = 500 mA/div (ac coupled) V(PH) = 1 V/div VO = 500 mV/div IO = 5 A/div t - Time = 250 ms/div Figure 20. t - Time = 5 ms/div Figure 21. t - Time = 500 nsec/div Figure 22. 15 TPS54073 www.ti.com SLVS547 – FEBRUARY 2005 PERFORMANCE GRAPHS (continued) The performance data for Figure 23 through Figure 26 are for the circuit in Figure 13. Conditions are PVIN = VIN = 3.3 V, VO = 1.5 V, fs = 700 kHz, and IO = 7 A, TA = 25°C, unless otherwise specified. MEASURED LOOP RESPONSE vs FREQUENCY 70 OUTPUT VOLTAGE RIPPLE LOAD TRANSIENT RESPONSE 210 180 60 Phase 50 VO = 100 mV/div (ac coupled) VO (RIPPLE) = 10 mV/div (ac coupled) 150 120 30 90 Gain 20 60 Gain 10 30 0 0 -10 -30 -20 -60 -30 -90 -40 -120 -50 -150 1M 10 100 1k 10 k f - Frequency - Hz 100 k Phase - O 40 IO = 14 A V(PH) = 2 V/div IO = 5 A/div t - Time = 250 ms/div t - Time = 500 ns/div Figure 23. Figure 24. Figure 25. FREE-AIR TEMPERATURE vs OUTPUT CURRENT 130 Safe Operating Area, TJ = 125oC TA - Free-Air Temperature - oC 120 110 100 90 80 70 60 50 40 30 20 10 0 0 2 4 6 8 10 12 I O - Output Current - A Figure 26. 16 14 16 TPS54073 www.ti.com SLVS547 – FEBRUARY 2005 DETAILED DESCRIPTION PVIN and VIN can be tied together for 3.3-V bus operation. OPERATING WITH SEPARATE PVIN The TPS54073 is designed to operate with the power stage (high-side and low-side MOSFETs) and the PVIN input connected to a separate power source from VIN. The primary intended application has VIN connected to a 3.3-V bus and PVIN connected to a 2.5-V bus. The TPS54073 cannot be damaged by any sequencing of these voltages. However, the UVLO (see detailed description section) is referenced to the VIN input. Some conditions may cause undesirable operation. If PVIN is absent when the VIN input is high, the slow-start is released, and the PWM circuit goes to maximum duty factor. When the PVIN input ramps up, the output of the TPS54073 follows the PVIN input until enough voltage is present to regulate to the proper output value. NOTE: If the PVIN input is controlled via a fast bus switch, it results in a hard-start condition and may damage the load (i.e., whatever is connected to the regulated output of the TPS54073). If a power-good signal is not available from the 2.5-V power supply, one can be generated using a comparator and hold the SS/ENA pin low until the 2.5-V bus power is good. An example of this is shown in Figure 27. This circuit can also be used to prevent the TPS54073 output from following the PVIN input while the PVIN power supply is ramping up. DISABLED SINKING DURING START-UP (DSDS) The DSDS feature enables minimal voltage drooping of output precharge capacitors at start-up. The TPS54073 is designed to disable the low-side MOSFET to prevent sinking current from a precharge output capacitor during start-up. Once the high-side MOSFET has been turned on to the maximum duty cycle limit, the low-side MOSFET is allowed to switch. Once the maximum duty cycle condition is met, the converter functions as a sourcing converter until the SS/ENA is pulled low. 100 kΩ VIN MAXIMUM OUTPUT VOLTAGE The maximum attainable output voltage is limited by the minimum voltage at the PVIN pin. Nominal maximum duty cycle is limited to 90% in the TPS54073; so, maximum output voltage is: V PVIN 0.9 O(max) (min) (26) Care must be taken while operating when nominal conditions cause duty cycles near 90%. Load transients can require momentary increases in duty cycle. If the required duty cycle exceeds 90%, the output may fall out of regulation. GROUNDING AND PowerPAD LAYOUT The TPS54073 has two internal grounds (analog and power). Inside the TPS54073, the analog ground ties to all of the noise-sensitive signals, whereas the power ground ties to the noisier power signals. The PowerPAD must be tied directly to AGND. Noise injected between the two grounds can degrade the performance of the TPS54073, particularly at higher output currents. However, ground noise on an analog ground plane can also cause problems with some of the control and bias signals. For these reasons, separate analog and power ground planes are recommended. These two planes must tie together directly at the IC to reduce noise between the two grounds. The only components that must tie directly to the power ground plane are the input capacitor, the output capacitor, the input voltage de-coupling capacitor, and the PGND pins of the TPS54073. UNDERVOLTAGE LOCKOUT (UVLO) The TPS54073 incorporates an undervoltage-lockout circuit to keep the device disabled when the input voltage (VIN) is insufficient. During power up, internal circuits are held inactive until VIN exceeds the nominal UVLO threshold voltage of 2.95 V. Once the UVLO start threshold is reached, device start-up begins. The device operates until VIN falls below the nominal UVLO stop threshold of 2.8 V. Hysteresis in the UVLO comparator, and a 2.5-µs rising and falling edge deglitch circuit reduce the likelihood of shutting the device down due to noise on VIN. UVLO is with respect to VIN and not PVIN, see the Application Information section. 10 kΩ PVIN VBIAS + − 10 kΩ 27.4 kΩ SS/ENA 1/2 LM293 Figure 27. Undervoltage Lockout Circuit for PVIN Using Open-Collector or Open-Drain Comparator 17 TPS54073 www.ti.com SLVS547 – FEBRUARY 2005 SLOW-START/ENABLE (SS/ENA) The slow-start/enable pin provides two functions. First, the pin acts as an enable (shutdown) control by keeping the device turned off until the voltage exceeds the start threshold voltage of approximately 1.2 V. When SS/ENA exceeds the enable threshold, device start-up begins. The reference voltage fed to the error amplifier is linearly ramped up from 0 V to 0.891 V in 3.35 ms. Similarly, the converter output voltage reaches regulation in approximately 3.35 ms. Voltage hysteresis and a 2.5-µs falling edge deglitch circuit reduce the likelihood of triggering the enable due to noise. The second function of the SS/ENA pin provides an external means of extending the slow-start time with a low-value capacitor connected between SS/ENA and AGND. Adding a capacitor to the SS/ENA pin has two effects on start-up. First, a delay occurs between release of the SS/ENA pin and start-up of the output. The delay is proportional to the slow-start capacitor value and lasts until the SS/ENA pin reaches the enable threshold. The start-up delay is approximately: 1.2 V t C d (SS) 5 A (27) Second, as the output becomes active, a brief ramp-up at the internal slow-start rate may be observed before the externally set slow-start rate takes control and the output rises at a rate proportional to the slow-start capacitor. The slow-start time set by the capacitor is approximately: 0.7 V t C (SS) (SS) 5 A (28) The actual slow-start time is likely to be less than the above approximation due to the brief ramp-up at the internal rate. VBIAS REGULATOR (VBIAS) The VBIAS regulator provides internal analog and digital blocks with a stable supply voltage over variations in junction temperature and input voltage. A high-quality, low-ESR, ceramic bypass capacitor is required on the VBIAS pin. X7R or X5R grade dielectrics are recommended because their values are more stable over temperature. The bypass capacitor must be placed close to the VBIAS pin and returned to AGND. External loading on VBIAS is allowed, with the caution that internal circuits require a minimum VBIAS of 2.7 V, and external loads on VBIAS with ac 18 or digital-switching noise may degrade performance. The VBIAS pin may be useful as a reference voltage for external circuits. VBIAS is derived from the VIN pin; see the functional block diagram of this data sheet. VOLTAGE REFERENCE The voltage reference system produces a precise Vref signal by scaling the output of a temperature stable bandgap circuit. During manufacture, the bandgap and scaling circuits are trimmed to produce 0.891 V at the output of the error amplifier, with the amplifier connected as a voltage follower. The trim procedure adds to the high-precision regulation of the TPS54073, because it cancels offset errors in the scale and error amplifier circuits. OSCILLATOR AND PWM RAMP The oscillator frequency is set to an internally fixed value of 350 kHz. The oscillator frequency can be externally adjusted from 280 to 700 kHz by connecting a resistor between the RT pin to ground. The switching frequency is approximated by the following equation, where R is the resistance from RT to AGND: Switching Frequency 100 k 500 [kHz] R (29) ERROR AMPLIFIER The high-performance, wide bandwidth, voltage error amplifier sets the TPS54073 apart from most dc/dc converters. The user is given the flexibility to use a wide range of output L and C filter components to suit the particular application needs. Type-2 or Type-3 compensation can be employed using external compensation components. PWM CONTROL Signals from the error amplifier output, oscillator, and current limit circuit are processed by the PWM control logic. Referring to the internal block diagram, the control logic includes the PWM comparator, OR gate, PWM latch, and portions of the adaptive dead-time and control-logic block. During steady-state operation below the current limit threshold, the PWM comparator output and oscillator pulse train alternately reset and set the PWM latch. Once the PWM latch is set, the low-side FET remains on for a minimum duration set by the oscillator pulse width. During this period, the PWM ramp discharges rapidly to its valley voltage. When the ramp begins to charge back up, the low-side FET turns off and high-side FET turns on. As the PWM ramp voltage exceeds the error amplifier output voltage, the PWM comparator resets the latch, thus turning off the high-side FET and turning on the low-side FET. The low-side FET TPS54073 www.ti.com remains on until the next oscillator pulse discharges the PWM ramp. During transient conditions, the error amplifier output could be below the PWM ramp valley voltage or above the PWM peak voltage. If the error amplifier is high, the PWM latch is never reset, and the high-side FET remains on until the oscillator pulse signals the control logic to turn the high-side FET off and the low-side FET on. The device operates at its maximum duty cycle until the output voltage rises to the regulation set-point, setting VSENSE to approximately the same voltage as VREF. If the error amplifier output is low, the PWM latch is continually reset and the high-side FET does not turn on. The low-side FET remains on until the VSENSE voltage decreases to a range that allows the PWM comparator to change states. The TPS54073 is capable of sinking current continuously until the output reaches the regulation set-point. If the current limit comparator trips for longer than 100 ns, the PWM latch resets before the PWM ramp exceeds the error amplifier output. The high-side FET turns off and low-side FET turns on to decrease the energy in the output inductor and consequently the output current. This process is repeated each cycle in which the current limit comparator is tripped. DEAD-TIME CONTROL AND MOSFET DRIVERS Adaptive dead-time control prevents shoot-through current from flowing in both N-channel power MOSFETs during the switching transitions by actively controlling the turn-on times of the MOSFET drivers. The high-side driver does not turn on until the voltage at the gate of the low-side FET is below 2 V. While the low-side driver does not turn on until the voltage at the gate of the high-side MOSFET is below 2 V. The high-side and low-side drivers are designed with 300-mA source and sink capability to quickly drive the power MOSFETs gates. The low-side driver is supplied from VIN, whereas the high-side driver is supplied from the BOOT pin. A bootstrap circuit uses an external BOOT capacitor and an internal 2.5-Ω bootstrap switch connected between the VIN and BOOT pins. The integrated bootstrap switch improves drive efficiency and reduces external component count. SLVS547 – FEBRUARY 2005 OVERCURRENT PROTECTION The cycle-by-cycle current limiting is achieved by sensing the current flowing through the high-side MOSFET and comparing this signal to a preset overcurrent threshold. The high-side MOSFET is turned off within 200 ns of reaching the current limit threshold. A 100-ns leading-edge blanking circuit prevents current limit false tripping. Current limit detection occurs only when current flows from VIN to PH when sourcing current to the output filter. Load protection during current sink operation is provided by thermal shutdown. THERMAL SHUTDOWN The device uses the thermal shutdown to turn off the power MOSFETs and disable the controller if the junction temperature exceeds 150°C. The device is released from shutdown automatically when the junction temperature decreases to 10°C below the thermal shutdown trip point, and starts up under control of the slow-start circuit. Thermal shutdown provides protection when an overload condition is sustained for several milliseconds. With a persistent fault condition, the device cycles continuously; starting up by control of the slow-start circuit, heating up due to the fault condition, and then shutting down on reaching the thermal shutdown trip point. This sequence repeats until the fault condition is removed. POWER-GOOD (PWRGD) The power-good circuit monitors for undervoltage conditions on VSENSE. If the voltage on VSENSE is 10% below the reference voltage, the open-drain PWRGD output is pulled low. PWRGD is also pulled low if VIN is less than the UVLO threshold or SS/ENA is low. When VIN, UVLO threshold, SS/ENA, enable threshold, and VSENSE > 90% of Vref, the open-drain output of the PWRGD pin is high. A hysteresis voltage equal to 3% of Vref and a 35-µs falling-edge deglitch circuit prevent tripping of the power-good comparator due to high-frequency noise. 19 PACKAGE OPTION ADDENDUM www.ti.com 19-May-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TPS54073PWP ACTIVE HTSSOP PWP 28 50 TBD CU NIPDAU Level-1-220C-UNLIM TPS54073PWPR ACTIVE HTSSOP PWP 28 2000 TBD CU NIPDAU Level-1-220C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Amplifiers amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive DSP dsp.ti.com Broadband www.ti.com/broadband Interface interface.ti.com Digital Control www.ti.com/digitalcontrol Logic logic.ti.com Military www.ti.com/military Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork Microcontrollers microcontroller.ti.com Security www.ti.com/security Telephony www.ti.com/telephony Video & Imaging www.ti.com/video Wireless www.ti.com/wireless Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2005, Texas Instruments Incorporated