TI TPS54350

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SLVS456C − OCTOBER 2003 − REVISED OCTOBER 2004

FEATURES
D 100 mΩ, 4.5-A Peak MOSFET Switch for High
D
D
D
D
D
D
D
D
D
Efficiency at 3-A Continuous Output Current
Uses External Lowside MOSFET or Diode
Output Voltage Adjustable Down to 0.891 V
With 1% Accuracy
Synchronizes to External Clock
1805 Out of Phase Synchronization
Wide PWM Frequency − Fixed 250 kHz,
500 kHz or Adjustable 250 kHz to 700 kHz
Internal Slow Start
Load Protected by Peak Current Limit and
Thermal Shutdown
Adjustable Undervoltage Lockout
16-Pin TSSOP PowerPADE Package
APPLICATIONS
D Industrial & Commercial Low Power Systems
D LCD Monitors and TVs
D Computer Peripherals
D Point of Load Regulation for High
DESCRIPTION
The TPS54350 is a medium output current synchronous
buck PWM converter with an integrated high side
MOSFET and a gate driver for an optional low side
external MOSFET. Features include a high performance
voltage error amplifier that enables maximum
performance under transient conditions and flexibility in
choosing the output filter inductors and capacitors. The
TPS54350 has an under-voltage-lockout circuit to prevent
start-up until the input voltage reaches 4.5 V; an internal
slow-start circuit to limit in-rush currents; and a power good
output to indicate valid output conditions. The
synchronization feature is configurable as either an input
or an output for easy 180° out of phase synchronization.
The TPS54350 device is available in a thermally
enhanced 16-pin TSSOP (PWP) PowerPAD package.
TI provides evaluation modules and the SWIFT Designer
software tool to aid in quickly achieving high-performance
power supply designs to meet aggressive equipment
development cycles.
Performance DSPs, FPGAs, ASICs and
Microprocessors
EFFICIENCY
vs
LOAD CURRENT
Simplified Schematic
Input
Voltage
TPS54350
SYNC
95
VIN
90
PWRGD
85
BOOT
VBIAS
PH
COMP
LSG
Output
Voltage
Efficiency − %
ENA
80
75
70
65
PGND
VSENSE
PWRPAD
60
VI = 12 V
VO = 5 V
fS = 250 kHz
55
50
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
IL − Load Current − A
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD and SWIFT are trademarks of Texas Instruments.
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)$"#$% '$ (,+)!#!)&'!$"( ,+% '0+ '+%( $# +1&( "('%*+"'( ('&"/&%/ 2&%%&"'3
%$/*)'!$" ,%$)+((!"4 /$+( "$' "+)+((&%!.3 !").*/+ '+('!"4 $# &.. ,&%&+'+%(
Copyright  2003 − 2004, Texas Instruments Incorporated
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SLVS456C − OCTOBER 2003 − REVISED OCTOBER 2004
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
TA
OUTPUT VOLTAGE
PACKAGE
PART NUMBER
−40°C to 85°C
Adjustable to 0.891 V
Plastic HTSSOP (PWP)
TPS54350PWP
(1) The PWP package is also available taped and reeled. Add an R suffix to the device type (i.e. TPS54350PWPR).
PACKAGE DISSIPATION RATINGS(1)
PACKAGE
THERMAL IMPEDANCE
JUNCTION-TO-AMBIENT
TA = 25°C
POWER RATING
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
16-Pin PWP with solder(2)
42.1°C/W
2.36
1.31
0.95
16-Pin PWP without solder
151.9°C/W
0.66
(1) See Figure 46 for power dissipation curves.
(2) Test Board Conditions
1. Thickness: 0.062”
2. 3” x 3”
3. 2 oz. Copper traces located on the top and bottom of the PCB for soldering
4. Copper areas located on the top and bottom of the PCB for soldering
5. Power and Ground planes, 1 oz. Copper (0.036 mm thick)
6. Thermal vias, 0.33 mm diameter, 1.5 mm pitch
7. Thermal isolation of power plane
For more information, refer to TI technical brief SLMA002.
0.36
0.26
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
UNIT
Input voltage range, VI
Output voltage range, VO
VIN
−0.3 V to 21.5 V
VSENSE
−0.3 V to 8.0 V
UVLO
−0.3 V to 8.0 V
SYNC
−0.3 V to 4.0 V
ENA
−0.3 V to 4.0 V
BOOT
VI(PH) + 8.0 V
VBIAS
−0.3 to 8.5 V
LSG
−0.3 to 8.5 V
SYNC
−0.3 to 4.0 V
RT
−0.3 to 4.0 V
PWRGD
−0.3 to 6.0 V
COMP
Source current, IO
−1.5 V to 22 V
PH
Internally Limited (A)
LSG (Steady State Current)
10 mA
COMP, VBIAS
3 mA
SYNC
Sink current, IS
Voltage differential
−0.3 to 4.0 V
PH
5 mA
LSG (Steady State Current)
100 mA
PH (Steady State Current)
500 mA
COMP
3 mA
ENA, PWRGD
10 mA
AGND to PGND
±0.3 V
Operating virtual junction temperature range, TJ
−40°C to +150°C
Storage temperature, Tstg
−65°C to +150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
260°C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2
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ELECTROSTATIC DISCHARGE (ESD) PROTECTION
MAX
UNIT
Human body model
MIN
600
V
CDM
1.5
kV
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX
UNIT
Input voltage range, VI
4.5
20
V
Operating junction temperature, TJ
−40
125
°C
ELECTRICAL CHARACTERISTICS
TJ = –40°C to 125°C, VIN = 4.5 V to 20 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
IQ
Quiescent current
Operating Current, PH Pin open,
No external low side MOSFET, RT = Hi-Z
Shutdown, ENA = 0 V
Start threshold voltage
VIN
5
mA
1.0
mA
4.32
Stop threshold voltage
3.69
Hysteresis
4.49
V
3.97
V
350
mV
UNDER VOLTAGE LOCK OUT (UVLO PIN)
Start threshold voltage
UVLO
1.20
Stop threshold voltage
1.02
Hysteresis
1.24
V
1.10
V
100
mV
BIAS VOLTAGE (VBIAS PIN)
VBIAS
Output voltage
IVBIAS = 1 mA, VIN ≥ 12 V
IVBIAS = 1 mA, VIN = 4.5 V
7.5
7.8
8.0
4.4
4.47
4.5
0.888
0.891
0.894
V
0.882
0.891
0.899
V
RT Grounded
200
250
300
RT Open
400
500
600
RT = 100 kΩ (1% resistor to AGND)
425
500
575
kHz
200
500
ns
5
10
ns
V
REFERENCE SYSTEM ACCURACY
Reference voltage
TJ = 25°C
OSCILLATOR (RT PIN)
Internally set PWM switching frequency
Externally set PWM switching frequency
FALLING EDGE TRIGGERED BIDIRECTIONAL SYNC SYSTEM (SYNC PIN)
SYNC out low-to-high rise time (10%/90%) (1)
25 pF to ground
kHz
SYNC out high-to-low fall time (90%/10%) (1)
25 pF to ground
Falling edge delay time (1)
Delay from rising edge to rising edge of
PH pins, see Figure 19
180
°
Minimum input pulsewidth (1)
RT = 100 kΩ
100
ns
Delay (falling edge SYNC to rising edge PH) (1)
RT = 100 kΩ
360
ns
SYNC out high level voltage
50 kΩ resistor to ground, no pullup
resistor
2.5
SYNC out low level voltage
0.6
SYNC in low level threshold
0.8
SYNC in high level threshold
SYNC in frequency range (1)
V
V
2.3
Percentage of programmed frequency
V
−10%
10%
225
770
V
kHz
(1) Ensured by design, not production tested.
3
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SLVS456C − OCTOBER 2003 − REVISED OCTOBER 2004
ELECTRICAL CHARACTERISTICS
TJ = –40°C to 125°C, VIN = 4.5 V to 20 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
FEED− FORWARD MODULATOR (INTERNAL SIGNAL)
Modulator gain
VIN = 12 V, TJ = 25°C
Modulator gain variation
Minimum controllable ON time (1)
Maximum duty factor (1)
8
−25%
180
VIN = 4.5 V
ERROR AMPLIFIER (VSENSE AND COMP PINS)
Error amplifier open loop voltage gain (1)
Error amplifier unity gain bandwidth (1)
80%
ns
86%
60
80
dB
1.0
2.8
MHz
Input bias current, VSENSE pin
COMP
V/V
25%
500
Output voltage slew rate (symmetric) (1)
1.5
nA
V/µs
ENABLE (ENA PIN)
Disable low level input voltage
Internal slow-start time (10% to 90%)
0.5
fs = 250 kHz, RT = ground (1)
fs = 500 kHz, RT = Hi−Z (1)
Pullup current source
Pulldown MOSFET
V
4.6
ms
2.3
1.8
5
II(ENA)=1 mA
0.1
Rising voltage
97%
10
µA
V
POWER GOOD (PWRGD PIN)
Power good threshold
Rising edge delay (1)
Output saturation voltage
PWRGD
fs = 250 kHz
4
fs = 500 kHz
2
Output saturation voltage
Isink = 1 mA, VIN > 4.5 V
Isink = 100 µA, VIN = 0 V
Open drain leakage current
Voltage on PWRGD = 6 V
ms
0.05
V
0.76
V
3
µA
CURRENT LIMIT
Current limit
VIN = 12 V
Current limit Hiccup Time (1)
fs = 500 kHz
3.3
4.5
6.5
A
4.5
ms
165
_C
7
_C
VIN = 4.5 V, Capacitive load = 1000 pF
15
ns
VIN = 12 V
60
ns
VIN = 4.5 V sink/source
7.5
VIN = 12 V sink/source
5
THERMAL SHUTDOWN
Thermal shutdown trip point (1)
Thermal shutdown hysteresis (1)
LOW SIDE MOSFET DRIVER (LSG PIN)
Turn on rise time, (10%/90%) (1)
Deadtime (1)
Driver ON resistance
Ω
OUTPUT POWER MOSFETS (PH PIN)
Phase node voltage when disabled
Voltage drop, low side FET and diode
rDS(ON), high side power MOSFET switch(2)
(1) Ensured by design, not production tested.
(2) Resistance from VIN to PH pins.
4
DC conditions and no load, ENA = 0 V
0.5
V
VIN = 4.5 V, Idc = 100 mA
1.13
1.42
VIN = 12 V, Idc = 100 mA
1.08
1.38
VIN = 4.5 V, BOOT−PH = 4.5 V, IO = 0.5 A
150
300
VIN = 12 V, BOOT−PH = 8 V, IO = 0.5 A
100
200
V
mΩ
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PIN ASSIGNMENTS
PWP PACKAGE
(TOP VIEW)
VIN
VIN
UVLO
PWRGD
RT
SYNC
ENA
COMP
1
2
3
4
5
6
7
8
THERMAL
PAD
16
15
14
13
12
11
10
9
BOOT
PH
PH
LSG
VBIAS
PGND
AGND
VSENSE
NOTE: If there is not a Pin 1 indicator, turn device to enable
reading the symbol from left to right. Pin 1 is at the lower
left corner of the device.
Terminal Functions
TERMINAL
NO.
1, 2
DESCRIPTION
NAME
VIN
Input supply voltage, 4.5 V to 20 V. Must bypass with a low ESR 10-µF ceramic capacitor.
3
UVLO
Undervoltage lockout pin. Connecting an external resistive voltage divider from VIN to the pin will override the internal
default VIN start and stop thresholds.
4
PWRGD
Power good output. Open drain output. A low on the pin indicates that the output is less than the desired output voltage.
There is an internal rising edge filter on the output of the PWRGD comparator.
5
RT
Frequency setting pin. Connect a resistor from RT to AGND to set the switching frequency. Connecting the RT pin to
ground or floating will set the frequency to an internally preselected frequency.
6
SYNC
Bidirectional synchronization I/O pin. SYNC pin is an output when the RT pin is floating or connected low. The output is a
falling edge signal out of phase with the rising edge of PH. SYNC may be used as an input to synchronize to a system clock
by connecting to a falling edge signal when an RT resistor is used. See 180° Out of Phase Synchronization operation in the
Application Information section.
7
ENA
Enable. Below 0.5 V, the device stops switching. Float pin to enable.
8
COMP
Error amplifier output. Connect frequency compensation network from COMP to VSENSE pins.
9
VSENSE
Inverting node error amplifier.
10
AGND
Analog ground—internally connected to the sensitive analog ground circuitry. Connect to PGND and PowerPAD.
11
PGND
Power Ground—Noisy internal ground—Return currents from the LSG driver output return through the PGND pin. Connect to AGND and PowerPAD.
12
VBIAS
Internal 8.0V bias voltage. A 1.0 uF ceramic bypass capacitance is required on the VBIAS pin.
13
LSG
Gate drive for optional low side MOSFET. Connect gate of n-channel MOSFET for a higher efficiency synchronous buck
converter configuration. Otherwise, leave open and connect schottky diode from ground to PH pins.
PH
Phase node—Connect to external L−C filter.
BOOT
Bootstrap capacitor for high side gate driver. Connect 0.1 µF ceramic capacitor from BOOT to PH pins.
PowerPAD
PGND and AGND pins must be connected to the exposed pad for proper operation. See Figure 21 for an example PCB
layout.
14, 15
16
5
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APPLICATION INFORMATION
FUNCTIONAL BLOCK DIAGRAM
BOOT
VIN
PH
320 kΩ
Hiccup
UVLO
UVLO
125 kΩ
SYNC
Current Limit
1.2V
2x Oscillator
RT
Bias + Drive
Regulator
PWM Ramp
(FeedFoward)
VBIAS
PWM
Comparator
COMP
S
Q
Adaptive Deadtime
and
Control Logic
VBIAS
R
VSENSE
LSG
Error
Amplifier
VBIAS2
Thermal
Shutdown
Reference
System
PWRGD
UVLO
5 µA
97% Ref
ENA
Hiccup
Timer
Rising
Edge
Delay
VSENSE
UVLO
Hiccup
TPS54350
POWERPAD
VBIAS
PGND
AGND
DETAILED DESCRIPTION
Undervoltage Lockout (UVLO)
The undervoltage lockout (UVLO) system has an internal
voltage divider from VIN to AGND. The defaults for the
start/stop values are labeled VIN and given in Table 1. The
internal UVLO threshold can be overridden by placing an
external resistor divider from VIN to ground. The internal
divider values are approximately 320 kΩ for the high side
resistor and 125 kΩ for the low side resistor. The divider
ratio (and therefore the default start/stop values) is quite
accurate, but the absolute values of the internal resistors
may vary as much as 15%. If high accuracy is required for
an externally adjusted UVLO threshold, select lower value
external resistors to set the UVLO threshold. Using a 1-kΩ
resistor for the low side resistor (R2 see Figure 1) is
recommended. Under no circumstances should the UVLO
pin be connected directly to VIN.
Table 1. Start/Stop Voltage Threshold
6
START VOLTAGE THRESHOLD
STOP VOLTAGE THRESHOLD
VIN (Default)
4.49
3.69
UVLO
1.24
1.02
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SLVS456C − OCTOBER 2003 − REVISED OCTOBER 2004
Input Voltage Supply
320 kΩ
R1
R2
1 kΩ
125 kΩ
Figure 1. Circuit Using External UVLO Function
The equations for selecting the UVLO resistors are:
Extending Slow Start Time
R1 +
VIN(start)
1 kW
* 1kW
1.24 V
(1)
(R1 ) 1 kW)
1 kW
(2)
VIN(stop) +
1.02 V
For applications which require an undervoltage lock out
(UVLO) threshold greater than 4.49 V, external resistors
may be implemented, see Figure 1, to adjust the start
voltage threshold. For example, an application needing an
UVLO start voltage of approximately 7.8 V using the
equation (1), R1 is calculated to the nearest standard
resistor value of 5.36 kΩ. Using equation (2), the input
voltage stop threshold is calculated as 6.48 V.
Enable (ENA) and Internal Slow Start
Once the ENA pin voltage exceeds 0.5 V, the TPS54350
starts operation. The TPS54350 has an internal digital
slow start that ramps the reference voltage to its final value
in 1150 switching cycles. The internal slow start time (10%
− 90%) is approximated by the following expression:
T
SS_INTERNAL(ms)
+ 1.15k
ƒ
s(kHz)
In applications that use large values of output capacitance
there may be a need to extend the slow start time to
prevent the startup current from tripping the current limit.
The current limit circuit is designed to disable the high side
MOSFET and reset the internal voltage reference for a
short amount of time when the high side MOSFET current
exceeds the current limit threshold. If the output
capacitance and load current cause the startup current to
exceed the current limit threshold, the power supply output
will not reach the desied output voltage. To extend the slow
start time and to reduce the startup current, an external
resistor and capcitor can be added to the ENA pin. The
slow start capacitance is calculated using the following
equation:
CSS(µF) = 5.55e−3 Tss(ms)
The RSS resistor must be 2 kΩ and the slow start capacitor
must be less than 0.47 µF.
Switching Frequency (RT)
(3)
Once the TPS54350 device is in normal regulation, the
ENA pin is high. If the ENA pin is pulled below the stop
threshold of 0.5 V, switching stops and the internal slow
start resets. If an application requires the TPS54350 to be
disabled, use open drain or open collector output logic to
interface to the ENA pin (see Figure 2). The ENA pin has
an internal pullup current source. Do not use external
pullup resistors.
The TPS54350 has an internal oscillator that operates at
twice the PWM switching frequency. The internal oscillator
frequency is controlled by the RT pin. Grounding the RT
pin sets the PWM switching frequency to a default
frequency of 250 kHz. Floating the RT pin sets the PWM
switching frequency to 500 kHz.
Connecting a resistor from RT to AGND sets the frequency
according to the following equation (also see Figure 30).
RT(kW) +
5 µA
Disabled
RSS
CSS
Enabled
Figure 2. Interfacing to the ENA Pin
ƒ
46000
s(kHz)–35.9
(4)
The RT pin controls the SYNC pin functions. If the RT pin
is floating or grounded, SYNC is an output. If the switching
frequency has been programmed using a resistor from RT
to AGND, then SYNC functions as an input.
The internal voltage ramp charging current increases
linearly with the set frequency and keeps the feed forward
modulator constant (Km = 8) regardless of the frequency
set point.
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SLVS456C − OCTOBER 2003 − REVISED OCTOBER 2004
SWITCHING FREQUENCY
SYNC PIN
RT PIN
250 kHz, internally set
Generates SYNC output signal
AGND
500 kHz, internally set
Generates SYNC output signal
Float
Externally set to 250 kHz to 700 kHz
Terminate to quiet ground
with 10-kΩ resistor.
R = 215 kΩ to 69 kΩ
Externally synchronized frequency
Synchronization Signal
Use 110 kΩ when RT floats and 237 kΩ when RT is grounded and
using the sync out signal of another TPS54350. Set RT resistor
equal to 90% to 110% of external synchronization frequency.
1805 Out of Phase Synchronization (SYNC)
The SYNC pin is configurable as an input or as an output,
per the description in the previous section. When
operating as an input, the SYNC pin is a falling-edge
triggered signal (see Figures 3, 4, and 19). When operating
as an output, the signal’s falling edge is approximately
180° out of phase with the rising edge of the PH pins. Thus,
two TPS54350 devices operating in a system can share an
input capacitor and draw ripple current at twice the
frequency of a single unit.
When operating the two TPS54350 devices 180° out of
phase, the total RMS input current is reduced. Thus
reducing the amount of input capacitance needed and
increasing efficiency.
When synchronizing a TPS54350 to an external signal,
the timing resistor on the RT pin must be set so that the
oscillator is programmed to run at 90% to 110% of the
synchronization frequency.
NOTE:
Do not use synchronization input for designs with
output voltages > 10 V.
VI(SYNC)
VO(PH)
Figure 3. SYNC Input Waveform
Internal Oscillator
VO(PH)
VO(SYNC)
Figure 4. SYNC Output Waveform
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Power Good (PWRGD)
The VSENSE pin is compared to an internal reference
signal, if the VSENSE is greater than 97% and no other
faults are present, the PWRGD pin presents a high
impedance. A low on the PWRGD pin indicates a fault. The
PWRGD pin has been designed to provide a weak
pull−down and indicates a fault even when the device is
unpowered. If the TPS54350 has power and has any fault
flag set, the TPS54350 indicates the power is not good by
driving the PWRGD pin low. The following events, singly
or in combination, indicate power is not good:
D
D
D
D
D
D
D
VSENSE pin out of bounds
Overcurrent
Thermal shutdown
UVLO undervoltage
Input voltage not present (weak pull-down)
Slow-starting
VBIAS voltage is low
Once the PWRGD pin presents a high impedance (i.e.,
power is good), a VSENSE pin out of bounds condition
forces PWRGD pin low (i.e., power is bad) after a time
delay. This time delay is a function of the switching
frequency and is calculated using equation 5:
T
delay
+ 1000 ms
ƒ
s(kHz)
(5)
Bias Voltage (VBIAS)
The VBIAS regulator provides a stable supply for the
internal analog circuits and the low side gate driver. Up to
1 mA of current can be drawn for use in an external
application circuit. The VBIAS pin must have a bypass
capacitor value of 1.0 µF. X7R or X5R grade dielectric
ceramic capacitors are recommended because of their
stable characteristics over temperature.
Bootstrap Voltage (BOOT)
The BOOT capacitor obtains its charge cycle by cycle from
the VBIAS capacitor. A capacitor from the BOOT pin to the
PH pins is required for operation. The bootstrap
connection for the high side driver must have a bypass
capacitor of 0.1 µF.
Error Amplifier
The VSENSE pin is the error amplifier inverting input. The
error amplifier is a true voltage amplifier with 1.5 mA of
drive capability with a minimum of 60 dB of open loop
voltage gain and a unity gain bandwidth of 2 MHz.
Voltage Reference
The voltage reference system produces a precision
reference signal by scaling the output of a temperature
stable bandgap circuit. During production testing, the
bandgap and scaling circuits are trimmed to produce
0.891 V at the output of the error amplifier, with the
amplifier connected as a voltage follower. The trim
procedure improves the regulation, since it cancels offset
errors in the scaling and error amplifier circuits.
PWM Control and Feed Forward
Signals from the error amplifier output, oscillator, and
current limit circuit are processed by the PWM control
logic. Referring to the internal block diagram, the control
logic includes the PWM comparator, PWM latch, and the
adaptive dead-time control logic. During steady-state
operation below the current limit threshold, the PWM
comparator output and oscillator pulse train alternately
reset and set the PWM latch.
Once the PWM latch is reset, the low-side driver and
integrated pull-down MOSFET remain on for a minimum
duration set by the oscillator pulse width. During this
period, the PWM ramp discharges rapidly to the valley
voltage. When the ramp begins to charge back up, the
low-side driver turns off and the high-side FET turns on.
The peak PWM ramp voltage varies inversely with input
voltage to maintain a constant modulator and power stage
gain of 8 V/V.
As the PWM ramp voltage exceeds the error amplifier
output voltage, the PWM comparator resets the latch, thus
turning off the high-side FET and turning on the low-side
FET. The low-side driver remains on until the next
oscillator pulse discharges the PWM ramp.
During transient conditions, the error amplifier output can
be below the PWM ramp valley voltage or above the PWM
peak voltage. If the error amplifier is high, the PWM latch
is never reset and the high-side FET remains on until the
oscillator pulse signals the control logic to turn the
high-side FET off and the internal low-side FET and driver
on. The device operates at its maximum duty cycle until the
output voltage rises to the regulation set point, setting
VSENSE to approximately the same voltage as the
internal voltage reference. If the error amplifier output is
low, the PWM latch is continually reset and the high-side
FET does not turn on. The internal low-side FET and low
side driver remain on until the VSENSE voltage decreases
to a range that allows the PWM comparator to change
states. The TPS54350 is capable of sinking current
through the external low side FET until the output voltage
reaches the regulation set point.
The minimum on time is designed to be 180 ns. During the
internal slow-start interval, the internal reference ramps
from 0 V to 0.891 V. During the initial slow-start interval, the
internal reference voltage is very small resulting in a
couple of skipped pulses because the minimum on time
causes the actual output voltage to be slightly greater than
the preset output voltage until the internal reference ramps
up.
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Deadtime Control
Adaptive dead time control prevents shoot through current
from flowing in the integrated high-side MOSFET and the
external low-side MOSFET during the switching
transitions by actively controlling the turn on times of the
drivers. The high-side driver does not turn on until the
voltage at the gate of the low-side MOSFET is below 1 V.
The low-side driver does not turn on until the voltage at the
gate of the high-side MOSFET is below 1 V.
LSG is the output of the low-side gate driver. The 100-mA
MOSFET driver is capable of providing gate drive for most
popular MOSFETs suitable for this application. Use the
SWIFT Designer Software Tool to find the most
appropriate MOSFET for the application. Connect the LSG
pin directly to the gate of the low-side MOSFET. Do not use
a gate resistor as the resulting turn-on time may be too
slow.
Integrated Pulldown MOSFET
The TPS54350 has a diode-MOSFET pair from PH to
PGND. The integrated MOSFET is designed for light−load
continuous−conduction mode operation when only an
external Schottky diode is used. The combination of
devices keeps the inductor current continuous under
conditions where the load current drops below the
inductor’s critical current. Care should be taken in the
selection of inductor in applications using only a low-side
Schottky diode. Since the inductor ripple current flows
through the integrated low-side MOSFET at light loads, the
inductance value should be selected to limit the peak
current to less than 0.3 A during the high-side FET turn off
time. The minimum value of inductance is calculated using
the following equation:
L(H) +
ǒ1 * VO
Ǔ
VI
ƒs
0.6
(6)
Thermal Shutdown
The device uses the thermal shutdown to turn off the
MOSFET drivers and controller if the junction temperature
exceeds 165°C. The device is restarted automatically
when the junction temperature decreases to 7°C below the
thermal shutdown trip point and starts up under control of
the slow-start circuit.
Overcurrent Protection
Overcurrent protection is implemented by sensing the
drain-to-source voltage across the high-side MOSFET
and compared to a voltage level which represents the
overcurrent threshold limit. If the drain-to-source voltage
exceeds the overcurrent threshold limit for more than
10
T
HICCUP(ms)
+ 2250
ƒ
s(kHz)
(7)
Once the hiccup time is complete, the ENA pin is released
and the converter initiates the internal slow-start.
Setting the Output Voltage
Low Side Gate Driver (LSG)
VO
100 ns, the ENA pin is pulled low, the high-side MOSFET
is disabled, and the internal digital slow-start is reset to 0 V.
ENA is held low for approximately the time that is
calculated by the following equation:
The output voltage of the TPS54350 can be set by feeding
back a portion of the output to the VSENSE pin using a
resistor divider network. In the application circuit of Figure
24, this divider network is comprised of resistors R1 and
R2. To calculate the resistor values to generate the
required output voltage use the following equation:
0.891
R2 + R1
V O * 0.891
(8)
Start with a fixed value of R1 and calculate the required R2
value. Assuming a fixed value of 10 kΩ for R1, the
following table gives the appropriate R2 value for several
common output voltages:
OUTPUT VOLTAGE (V)
R2 VALUE (KΩ)
1.2
28.7
1.5
14.7
1.8
9.76
2.5
5.49
3.3
3.74
Output Voltage Limitations
Due to the internal design of the TPS54350 there are both
upper and lower output voltage limits for any given input
voltage. Additionally, the lower boundary of the output
voltage set point range is also dependent on operating
frequency. The upper limit of the output voltage set point
is constrained by the maximum duty cycle of the device
and is shown in Figure 48. The lower limit is constrained
by the minimum controllable on time which may be as high
as 220 ns. The approximate minimum output voltage for a
given input voltage and range of operating frequencies is
shown in Figure 29 while the maximum operating
frequency versus input voltage for some common output
voltages is shown in Figure 30.
The curves shown in these two figures are valid for output
currents greater than 0.5 A. As output currents decrease
towards no load (0 A), the minimum output voltage
decreases. For applications where the load current is less
than 100 mA, the curves shown in Figures 31 and 32 are
applicable. All of the data plotted in these curves are
approximate and take into account a possible 20 percent
deviation in actual operating frequency relative to the
intended set point.
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SLVS456C − OCTOBER 2003 − REVISED OCTOBER 2004
TYPICAL CHARACTERISTICS
LOOP RESPONSE
180
50
150
20
60
30
Gain
0
0
−30
−10
VI = 12 V
VO = 3.3 V
IO = 3 A
fS = 500 kHz
See Figure 24
−30
−40
−50
−60
10
1.5 A
−60
−90
−120
0.1
VI = 6 V
VI = 12 V
0.0
VI = 18 V
−0.1
1k
10k
100k
3A
0.05
0A
0.00
−0.05
See Figure 24
See Figure 24
−150
−180
1M
Output Voltage Change − %
90
−20
0.2
Output Voltage Change − %
30
10
LINE REGULATION
0.10
120
Phase
40
G − Gain − dB
LOAD REGULATION
60
−0.2
0.0
f − Frequency − Hz
−0.10
0.5
1.0
1.5
2.0
2.5
6
3.0
Figure 5
Figure 6
EFFICIENCY
vs
OUTPUT CURRENT
8
10
12
14
16
18
VI − Input Voltage − V
IO − Output Current − A
Figure 7
INPUT RIPPLE VOLTAGE
OUTPUT RIPPLE VOLTAGE
100
VI(Ripple) = 100 mV/div (ac coupled)
95
VO = 20 mV/div (ac)
VI = 6 V
90
VI = 12 V
70
65
See Figure 24
V(PH) = 5V/div
Amplitude
75
Amplitude
80
See Figure 24
V(PH) = 5 V/div
VI = 18 V
VO = 3.3 V
fS = 500 kHz
See Figure 24
60
55
VI = 12 V, VO = 3.3 V, IO = 3 A, fS = 500 kHz
50
0.5
1.0
1.5
2.0
2.5
Time − 1 µs/div
IO − Output Current − A
Figure 8
Time − 1 µs/div
Figure 9
PH PIN VOLTAGE
Load Transient Response − mV
V(PH) = 5 V/div
Figure 10
POWER UP
LOAD TRANSIENT RESPONSE
V(LSG) = 5 V/div
See Figure 24
VI = 12 V, VO = 3.3 V, IO = 3 A, fS = 500 kHz
3.0
VI = 12 V, VO = 3.3 V
IO = 3 A, fS = 500 kHz
See Figure 24
VO = 10 mV/div (ac coupled)
IO = 1 A/div
VI = 5 V/div
Power Up Waveforms − V
0.0
Amplitude
Efficiency − %
85
VO = 2 V/div
V(PWRGD) = 2 V/div
See Figure 24
VI = 12 V, VO = 3.3 V, IO = 3 A, fS = 500 kHz
Time − 1 µs/div
Figure 11
Time − 200 µs/div
Figure 12
Time − 2 ms/div
Figure 13
11
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SLVS456C − OCTOBER 2003 − REVISED OCTOBER 2004
EFFICIENCY
vs
OUTPUT CURRENT
POWER DOWN
100
95
V(PWRGD) = 2 V/div
Continuous Conduction Mode
VI = 6 V
90
85
Efficiency − %
Power Down Waveforms − V
VI = 5 V/div
VO = 2 V/div
CONTINUOUS CONDUCTION MODE
80
75
VI = 12 V
70
VI = 18 V
65
VO = 3.3 V
fS = 500 kHz
See Figure 25
60
See Figure 24
55
V(PH) = 5 V/div
I(Inductor) = 0.5 A/div
See Figure 25
50
Time − 2 ms/div
0.0
0.5
1.0
1.5
2.0
2.5
Time − 1 µs/div
3.0
IO − Output Current − A
Figure 14
Figure 15
DISCONTINUOUS CONDUCTION MODE
Figure 16
INPUT RIPPLE CANCELLATION
SEQUENCING WAVEFORMS
V(PH1) = 10 V/div
Input Ripple Cancellation − V
V(PH) = 5 V/div
Sequencing Waveforms − V
Discontinuous Conduction Mode
VI = 10 V/div
VO1 = 2 V/div
V(PWRGD) = 2 V/div
I(Inductor) = 0.5 A/div
VO2 = 2 V/div
V = 1.8 V, 3.3 V
See Figure 26
See Figure 25
Time − 1 µs/div
Figure 17
Time − 2 ms/div
Time − 1 µs/div
Figure 18
Figure 19
100
95
90
Efficiency − %
85
80
75
70
65
VI = 5 V
VO = −5 V
fS = 250 kHz
See Figure 27
60
55
50
0.5
1.0
1.5
IO − Output Current − A
Figure 20
12
VI(Ripple) = 100 mV/div (ac coupled)
VIN = 12 V, VO1 = 1.8 V,
VO2 = 3.3 V, See Figure 26
EFFICIENCY
vs
OUTPUT CURRENT
0.0
V(PH2) = 10 V/div
2.0
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SLVS456C − OCTOBER 2003 − REVISED OCTOBER 2004
APPLICATION INFORMATION
VIN
GND
VIN
BOOT
VIN
PH
UVLO
PH
PWRGD
LSG
RT
VBIAS
SYNC
PGND
ENA
AGND
COMP
VOUT
GND
VSENSE
VIA to Ground Plane
Figure 21. TPS54350 PCB Layout
PCB LAYOUT
The VIN pins should be connected together on the printed
circuit board (PCB) and bypassed with a low ESR ceramic
bypass capacitor. Care should be taken to minimize the
loop area formed by the bypass capacitor connections, the
VIN pins, and the TPS54350 ground pins. The minimum
recommended bypass capacitance is 10-µF ceramic with
a X5R or X7R dielectric and the optimum placement is
closest to the VIN pins and the AGND and PGND pins. See
Figure 21 for an example of a board layout. The AGND and
PGND pins should be tied to the PCB ground plane at the
pins of the IC. The source of the low-side MOSFET and the
anode of the Schottky diode should be connected directly
to the PCB ground plane. The PH pins should be tied
together and routed to the drain of the low-side MOSFET
or to the cathode of the external Schottky diode. Since the
PH connection is the switching node, the MOSFET (or
diode) should be located very close to the PH pins, and the
area of the PCB conductor minimized to prevent excessive
capacitive coupling. The recommended conductor width
from pins 14 and 15 is 0.050 inch to 0.075 inch of 1-ounce
copper. The length of the copper land pattern should be no
more than 0.2 inch.
For operation at full rated load, the analog ground plane
must provide adequate heat dissipating area. A 3-inch by
3-inch plane of copper is recommended, though not
mandatory, dependent on ambient temperature and
airflow. Most applications have larger areas of internal
ground plane available, and the PowerPAD should be
connected to the largest area available. Additional areas
on the bottom or top layers also help dissipate heat, and
any area available should be used when 3 A or greater
operation is desired. Connection from the exposed area of
the PowerPAD to the analog ground plane layer should be
made using 0.013-inch diameter vias to avoid solder
wicking through the vias. Four vias should be in the
PowerPAD area with four additional vias outside the pad
area and underneath the package. Additional vias beyond
those recommended to enhance thermal performance
should be included in areas not under the device package.
13
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SLVS456C − OCTOBER 2003 − REVISED OCTOBER 2004
j0.0130
8 PL
Minimum recommended thermal vias: 4 x
.013 dia. inside powerpad area and
4 x .013 dia. under device as shown.
Additional .018 dia. vias may be used if top
side Analog Ground area is extended.
Minimum recommended exposed copper
area for powerpad. 5mm stencils may
require 10 percent larger area.
0.0150
0.06
0.0371
0.0400
0.1970
0.1942
0.0570
0.0400
0.0400
0.0256
Connect Pin 10 AGND
and Pin 11 PGND to
Analog Ground plane in
this area for optimum
performance.
0.1700
Minimum recommended top
0.1340
side Analog Ground area.
0.0690
0.0400
Figure 22. Thermal Considerations for PowerPAD Layout
MODEL FOR LOOP RESPONSE
The Figure 23 shows an equivalent model for the
TPS54350 control loop which can be modeled in a circuit
simulation program to check frequency response and
dynamic load response. The error amplifier in the
TPS54350 is a voltage amplifier with 80 dB (10000 V/V) of
open loop gain. The error amplifier can be modeled using
an ideal voltage-controlled current source as shown in
Figure 23 with a resistor and capacitor on the output. The
TPS54350 device has an integrated feed forward
compensation circuit which eliminates the impact of the
input voltage changes to the overall loop transfer function.
The feed forward gain is modeled as an ideal voltagecontrolled voltage source with a gain of 8 V/V. The 1-mV
ac voltage between nodes a and b effectively breaks the
control loop for the frequency response measurements.
Plotting b/c shows the small-signal response of the power
stage. Plotting c/a shows the small-signal response of the
frequency compensation. Plotting a/b shows the smallsignal response of the overall loop. The dynamic load
response can be checked by replacing the RL with a
current source with the appropriate load step amplitude
and step rate in a time domain analysis.
LO
Rdc
a
PH
1 mV
R(switch)
+
+
–
10 MΩ
–
ESR
RL
b
CO
100 mΩ
R5
R1
8 V/V
TPS54350
C8
VSENSE
+
–
20 V/V
–
10 MΩ
+
10 MΩ
–
+
50 pF
50 µA/V
R2
0.891
R3
REF
C7
C6
COMP
c
Figure 23. Model of Control Loop
14
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SLVS456C − OCTOBER 2003 − REVISED OCTOBER 2004
U1
TPS54350PWP
6 V − 18 V
1
2
C1
47 µF
C9
10 µF
3
4
5
6
7
8
VIN
BOOT
VIN
PH
UVLO
PH
LSG
PWRGD
RT
VBIAS
SYNC
PGND
ENA
AGND
COMP
L1
10 µH
C3
0.1 µF
VSENSE
1
16
15
1 2 3 6 7
Q1
14
13
R4
4.7 Ω
4
12
9
+
C2
100 µF
11
10
VOUT 3.3 V @ 3 A
2
C4
1 µF
8
5
C11
3300 pF
PWRPAD
17
C6
82 nF
R3
768 Ω
R1
1 kΩ
C7
1800 pF
Q1: Fairchild Semiconductor FDR6674A
L1: Vishay IHLP-5050CE
C2: Sanyo 6TPC100M
R2
374 Ω
R5
137 Ω
C8
33 nF
Figure 24. Application Circuit, 12 V to 3.3 V
Figure 24 shows the schematic for a typical TPS54350
application. The TPS54350 can provide up to 3-A output
current at a nominal output voltage of 3.3 V. For proper
thermal performance, the exposed PowerPAD underneath
the device must be soldered down to the printed circuit
board.
DESIGN PROCEDURE
The following design procedure can be used to select
component values for the TPS54350. Alternately, the
SWIFT Designer Software may be used to generate a
complete design. The SWIFT Designer Software uses an
iterative design procedure and accesses a comprehensive
database of components when generating a design. This
section presents a simplified discussion of the design
process.
DESIGN PROCEDURE
To begin the design process a few parameters must be
decided upon. The designer needs to know the following:
D
D
D
D
D
D
Input voltage range
Output voltage
For this design example, use the following as the input
parameters:
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage range
6 V to 18 V
Output voltage
3.3 V
Input ripple voltage
300 mV
Output ripple voltage
30 mV
Output current rating
3A
Operating frequency
500 kHz
NOTE: As an additional constraint, the design is set up to be small size
and low component height.
SWITCHING FREQUENCY
The switching frequency is set using the RT pin.
Grounding the RT pin sets the PWM switching frequency
to a default frequency of 250 kHz. Floating the RT pin sets
the PWM switching frequency to 500 kHz. By connecting
a resistor from RT to AGND, any frequency in the range of
250 to 700 kHz can be set. Use equation 8 to determine the
proper value of RT.
RT(kW) +
46000
ƒ s(kHz) * 35.9
(9)
In this example circuit, RT is not connected and the
switching frequency is set at 500 kHz.
Input ripple voltage
Output ripple voltage
Output current rating
Operating frequency
INPUT CAPACITORS
The TPS54350 requires an input decoupling capacitor
and, depending on the application, a bulk input capacitor.
The minimum value for the decoupling capacitor, C9, is
15
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SLVS456C − OCTOBER 2003 − REVISED OCTOBER 2004
10µF. A high quality ceramic type X5R or X7R is
recommended. The voltage rating should be greater than
the maximum input voltage. Additionally some bulk
capacitance may be needed, especially if the TPS54350
circuit is not located within about 2 inches from the input
voltage source. The value for this capacitor is not critical
but it also should be rated to handle the maximum input
voltage including ripple voltage and should filter the output
so that input ripple voltage is acceptable.
For this design example use KIND = 0.2 and the minimum
inductor value is calculated to be 8.98 µH. The next highest
standard value is 10 µH, which is used in this design.
For the output filter inductor it is important that the RMS
current and saturation current ratings not be exceeded.
The RMS inductor current can be found from equation 12:
I
L(RMS)
+
This input ripple voltage can be approximated by equation
9:
DVIN +
I OUT(MAX)
C BULK
0.25
ƒsw
ǒ
) I OUT(MAX)
Ǔ
ESR MAX
(10)
The maximum RMS ripple current also needs to be
checked. For worst case conditions, this can be
approximated by equation 10:
I
CIN
+
OUT(MAX)
2
(11)
In this case the input ripple voltage would be 140 mV and
the RMS ripple current would be 1.5 A. The maximum
voltage across the input capacitors would be VIN max plus
delta VIN/2. The chosen bulk and bypass capacitors are
each rated for 25 V and the combined ripple current
capacity is greater than 3 A, both providing ample margin.
It is very important that the maximum ratings for voltage
and current are not exceeded under any circumstance.
OUTPUT FILTER COMPONENTS
Two components need to be selected for the output filter,
L1 and C2. Since the TPS54350 is an externally
compensated device, a wide range of filter component
types and values can be supported.
Inductor Selection
To calculate the minimum value of the output inductor, use
equation 11:
ǒ
Ǔ
V
* V
OUT(MAX)
IN(MAX)
OUT
L
+
MIN
V
K
I
F
IN(max)
IND
OUT
SW (12)
V
KIND is a coefficient that represents the amount of inductor
ripple current relative to the maximum output current. For
designs using low ESR output capacitors such as
ceramics, use KIND = 0.3. When using higher ESR output
capacitors, KIND = 0.2 yields better results.
16
ǒ
V
V
OUT
ǒVIN(MAX) * VOUTǓ
L
IN(MAX)
OUT
F
SW
0.8
Ǔ
2
(13)
and the peak inductor current can be determined with
equation 13:
Where IOUT(MAX) is the maximum load current, ƒSW is the
switching frequency, CBULK is the bulk capacitor value and
ESRMAX is the maximum series resistance of the bulk
capacitor.
I
Ǹ
1
)
I2
OUT(MAX) 12
V
I L(PK) + I
OUT(MAX)
)
OUT
1.6
ǒVIN(MAX) * VOUTǓ
V IN(MAX)
L
OUT
F
(14)
SW
For this design, the RMS inductor current is 3.01 A and the
peak inductor current is 3.34 A. The chosen inductor is a
Vishay IHLP5050CE-01 10 µH. It has a saturation current
rating of 14 A and a RMS current rating of 7 A, easily
meeting these requirements. A lesser rated inductor could
be used, however this device was chosen because of its
low profile component height. In general, inductor values
for use with the TPS54350 are in the range of 6.8 µH to
47µH.
Capacitor Selection
The important design factors for the output capacitor are
dc voltage rating, ripple current rating, and equivalent
series resistance (ESR). The dc voltage and ripple current
ratings cannot be exceeded. The ESR is important
because along with the inductor current it determines the
amount of output ripple voltage. The actual value of the
output capacitor is not critical, but some practical limits do
exist. Consider the relationship between the desired
closed loop crossover frequency of the design and LC
corner frequency of the output filter. In general, it is
desirable to keep the closed loop crossover frequency at
less than 1/5 of the switching frequency. With high
switching frequencies such as the 500-kHz frequency of
this design, internal circuit limitations of the TPS54350
limit the practical maximum crossover frequency to about
50 kHz. Additionally, to allow for adequate phase gain in
the compensation network, the LC corner frequency
should be about one decade or so below the closed loop
crossover frequency. This limits the minimum capacitor
value for the output filter to:
C
OUT
+
1
LOUT
(2pƒK )
CO
2
(15)
Where K is the frequency multiplier for the spread between
fLC and fCO. K should be between 5 and 15, typically 10 for
one decade difference.For a desired crossover of 50 kHz
and a 10-µH inductor, the minimum value for the output
capacitor is 100 µF. The selected output capacitor must be
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SLVS456C − OCTOBER 2003 − REVISED OCTOBER 2004
rated for a voltage greater than the desired output voltage
plus one half the ripple voltage. Any derating amount must
also be included. The maximum RMS ripple current in the
output capacitor is given by equation 15:
ICOUT(RMS) + 1
Ǹ12
ȡ VOUT ǒVIN(MAX) * VOUTǓ ȣ
ȧVIN(MAX) LOUT FSW NCȧ
Ȣ
Ȥ(16)
where NC is the number of output capacitors in parallel.
The maximum ESR of the output capacitor is
determined by the amount of allowable output ripple as
specified in the initial design parameters. The output
ripple voltage is the inductor ripple current times the
ESR of the output filter so the maximum specified ESR
as listed in the capacitor data sheet is given by equation
16:
ESR MAX + N
ǒ
V IN(MAX)
C
V
OUT
L
OUT
F
SW
0.8
ǒVIN(MAX) * VOUTǓ
Ǔ
DV p*p(MAX)
(17)
Where nVp−p is the desired peak-to-peak output ripple.
For this design example, a single 100-µF output capacitor
is chosen for C2 since the design goal is small size. The
calculated RMS ripple current is 156 mV and the maximum
ESR required is 59 mΩ. A capacitor that meets these
requirements is a Sanyo Poscap 6TPC100M, rated at
6.3 V with a maximum ESR of 45 mΩ and a ripple current
rating of 1.7 A. An additional small 0.1-µF ceramic bypass
capacitor is also used.
Other capacitor types work well with the TPS54350,
depending on the needs of the application.
COMPENSATION COMPONENTS
The external compensation used with the TPS54350
allows for a wide range of output filter configurations. A
large range of capacitor values and types of dielectric are
supported. The design example uses type 3 compensation
consisting of R1, R3, R5, C6, C7 and C8. Additionally, R2
along with R1 forms a voltage divider network that sets the
output voltage. These component reference designators
are the same as those used in the SWIFT Designer
Software. There are a number of different ways to design
a compensation network. This procedure outlines a
relatively simple procedure that produces good results
with most output filter combinations. Use of the SWIFT
Designer Software for designs with unusually high closed
loop crossover frequencies, low value, low ESR output
capacitors such as ceramics or if the designer is unsure
about the design procedure is recommended.
When designing compensation networks for the
TPS54350, a number of factors need to be considered.
The gain of the compensated error amplifier should not be
limited by the open loop amplifier gain characteristics and
should not produce excessive gain at the switching
frequency. Also, the closed loop crossover frequency
should be set less than one fifth of the switching frequency,
and the phase margin at crossover must be greater than
45 degrees. The general procedure outlined here
produces results consistent with these requirements
without going into great detail about the theory of loop
compensation.
First calculate the output filter LC corner frequency using
equation 17:
ƒ
LC
+
Ǹ
2p L
1
C
OUT OUT
(18)
For the design example, fLC = 5033 Hz.
The closed loop crossover frequency should be greater
than fLC and less than one fifth of the switching frequency.
Also, the crossover frequency should not exceed 50 kHz,
as the error amplifier may not provide the desired gain. For
this design, a crossover frequency of 30 kHz was chosen.
This value is chosen for comparatively wide loop
bandwidth while still allowing for adequate phase boost to
insure stability.
Next calculate the R2 resistor value for the output voltage
of 3.3 V using equation 18:
R2 +
R1
V
OUT
0.891
* 0.891
(19)
For any TPS54350 design, start with an R1 value of 1.0 kΩ.
R2 is then 374 Ω.
Now the values for the compensation components that set
the poles and zeros of the compensation network can be
calculated. Assuming that R1 > R5 and C6 > C7, the pole
and zero locations are given by equations 19 through 22:
ƒ
Z1
+
1
2pR3C6
(20)
ƒ
Z2
+
1
2pR1C8
(21)
ƒ
P1
+
1
2pR5C8
(22)
ƒ
P2
+
1
2pR3C7
(23)
Additionally there is a pole at the origin, which has unity
gain with the following frequency:
ƒ
INT
+
1
2pR1C6
(24)
17
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SLVS456C − OCTOBER 2003 − REVISED OCTOBER 2004
This pole is used to set the overall gain of the compensated
error amplifier and determines the closed loop crossover
frequency. Since R1 is given as 1 kΩ and the crossover
frequency is selected as 30 kHz, the desired fINT can be
calculated with equation 24:
ƒ
INT
+
ƒ
10–0.9
CO
2
(25)
And the value for C6 is given by equation 25:
C6 +
1
2pR1ƒ
1
pC6ƒ
(26)
LC
(27)
The second zero, fZ2 , is located at the output filter LC
corner frequency, so C8 can be calculated from:
C8 +
1
2pR1ƒ
LC
(28)
The first pole, fP1, is located to coincide with the output
filter ESR zero frequency. This frequency is given by:
ƒ
ESR
+
2pR
C
ESR OUT
(29)
In this case, the ESR zero frequency is 35.4 kHz, and R5
can be calculated from:
1
2pC8 ƒ
ESR
(30)
The final pole is placed at a frequency above the closed
loop crossover frequency high enough to not cause the
phase to decrease too much at the crossover frequency
while still providing enough attenuation so that there is little
or no gain at the switching frequency. The fP2 pole location
for this circuit is set to 4 times the closed loop crossover
frequency and the last compensation component value C7
can be derived as follows:
C7 +
1
8pR3ƒ
CO
(31)
Note that capacitors are only available in a limited range
of standard values, so the nearest standard value has
been chosen for each capacitor. The measured closed
loop response for this design is shown in Figure 5.
18
The TPS54350 is designed to operate using an external
low-side FET, and the LSG pin provides the gate drive
output. Connect the drain to the PH pin, the source to
PGND, and the gate to LSG. The TPS54350 gate drive
circuitry is designed to accommodate most common
n-channel FETs that are suitable for this application. The
SWIFT Designer Software can be used to calculate all the
design parameters for low-side FET selection. There are
some simplified guidelines that can be applied that
produce an acceptable solution in most designs.
The selected FET must meet the absolute maximum
ratings for the application:
Drain-source voltage (VDS) must be higher than the
maximum voltage at the PH pin, which is VINMAX + 0.5 V.
Gate-source voltage (VGS) must be greater than 8 V.
1
where RESR is the equivalent series resistance of the
output capacitor.
R5 +
Every TPS54350 design requires a bootstrap capacitor,
C3 and a bias capacitor, C4. The bootstrap capacitor must
be 0.1 µF. The bootstrap capacitor is located between the
PH pins and BOOT pin. The bias capacitor is connected
between the VBIAS pin and AGND. The value should be
1.0 µF. Both capacitors should be high quality ceramic
types with X7R or X5R grade dielectric for temperature
stability. They should be placed as close to the device
connection pins as possible.
LOW-SIDE FET
INT
The first zero, fZ1 , is located at one half the output filter LC
corner frequency, so R3 can be calculated from:
R3 +
BIAS AND BOOTSTRAP CAPACITORS
Drain current (ID) must be greater than 1.1 x IOUTMAX.
Drain-source on resistance (rDSON) should be as small as
possible, less than 30 mΩ is desirable. Lower values for
rDSON result in designs with higher efficiencies. It is
important to note that the low-side FET on time is typically
longer than the high-side FET on time, so attention paid to
low-side FET parameters can make a marked
improvement in overall efficiency.
Total gate charge (Qg) must be less than 50 nC. Again,
lower Qg characteristics result in higher efficiencies.
Additionally, check that the device chosen is capable of
dissipating the power losses.
For this design, a Fairchild FDR6674A 30-V n-channel
MOSFET is used as the low-side FET. This particular FET
is specifically designed to be used as a low-side
synchronous rectifier.
POWER GOOD
The TPS54350 is provided with a power good output pin
PWRGD. This output is an open drain output and is
intended to be pulled up to a 3.3-V or 5-V logic supply. A
10-kΩ, pull-up resistor works well in this application. The
absolute maximum voltage is 6 V, so care must be taken
not to connect this pull-up resistor to VIN if the maximum
input voltage exceeds 6 V.
www.ti.com
SLVS456C − OCTOBER 2003 − REVISED OCTOBER 2004
SNUBBER CIRCUIT
R4 and C11 of the application schematic in Figure 24
comprise a snubber circuit. The snubber is included to
reduce over-shoot and ringing on the phase node when the
internal high-side FET turns on. Since the frequency and
U1
TPS54350PWP
6 V − 18 V
1
2
C1
47 µF
C9
3
10 µF
4
5
6
7
8
BOOT
VIN
PH
UVLO
PH
LSG
RT
VBIAS
SYNC
PGND
ENA
AGND
COMP
L1
10 µH
C3
0.1 µF
VIN
PWRGD
amplitude of the ringing depends to a large degree on
parasitic effects, it is best to choose these component
values based on actual measurements of any design
layout. See literature number SLUP100 for more detailed
information on snubber design.
VSENSE
1
16
VOUT 3.3 V @ 3 A
2
15
14
R4
4.7 Ω
13
12
D1
11
10
9
C4
1 µF
+
C2
100 µF
C11
3300 pF
PWRPAD
17
C6
82 nF
R3
768 Ω
R1
1 kΩ
C7
1800 pF
D1: On Semiconductor MBRS340T3
L1: Vishay IHLP-5050CE
C2: Sanyo 6TPC100M
R2
374 Ω
R5
137 Ω
C8
33 nF
Figure 25. 3.3-V Power Supply With Schottky Diode
Figure 25 shows an application where a clamp diode is
used in place of the low-side FET. The TPS54350
incorporates an integrated pull-down FET so that the
circuit remains operating in continuous mode during light
load operation. A 3-A, 40-V Schottky diode such as the
Motorola MBRS340T3 or equivalent is recommended.
19
www.ti.com
SLVS456C − OCTOBER 2003 − REVISED OCTOBER 2004
U1
TPS54350PWP
6 V − 18 V
1
2
+
C1
47 µF
C9
10 µF
3
Power Good 3.3 V 4
5
6
7
VIN
BOOT
VIN
PH
UVLO
PH
PWRGD
LSG
RT
VBIAS
SYNC
PGND
ENA
AGND
8
VSENSE
COMP
PWRPAD
17
C6
R3
82 nF
768 Ω
Pull up to 3.3 V or 5 V
16
L1
10 µH
C3
0.1 µF
2
1
VOUT 3.3 V @ 3 A
1 2 3 6 7
15
Q1
14
13
R10
4.7 Ω
4
12
+
C2
100 µF
11
10
C4
1 µF
9
8 5
C10
3300 pF
R1
1 kΩ
C7
1800 pF
R5
137 Ω
R2
374 Ω
R4
10 kΩ
C8
33 nF
Power Good 1.8 V
U2
TPS54350PWP
1
2
C18
47 µF
C15
10 µF
3
4
5
6
R13
110 kΩ
7
VIN
BOOT
VIN
PH
UVLO
PH
PWRGD
RT
VBIAS
SYNC
PGND
ENA
AGND
8
Easy 1805 Out of Phase
Synchronization
LSG
COMP
VSENSE
PWRPAD
17
C13
R6
82 nF
768 Ω
16
15
1
13
R9
4.7 Ω
+
C11
100 µF
11
9
VOUT 1.8 V @ 3 A
Q2
4
12
10
2
1 2 3 6 7
14
C16
1 µF
8
5
C14
3300 pF
R12
1 kΩ
C17
1800 pF
Q1, Q2: Fairchild Semiconductor FDR6674A
L1, L2: Vishay IHLP-5050CE
C2, C11: Sanyo 6TPC100M
L2
10 µH
C5
0.1 µF
R7
976 Ω
R11
137 Ω
C12
33 nF
Figure 26. 3.3-V/1.8-V Power Supply With Sequencing
Figure 26 is an example of power supply sequencing using
two TPS54350s. U1 is used to generate an output of 3.3
V, while the voltage output of U2 is set at 1.8 V, typical I/O
and core voltages for microprocessors and FPGAs. In the
circuit, the 3.3−V supply is designed to power up first. The
PWRGD pin of U1 is tied to the ENA pin of U2 so that the
1.8-V supply starts to ramp up after the 3.3-V supply is
within regulation. Since the RT pin of U1 is floating, the
20
SYNC pin is an output. This synchronization signal is fed
to the SYNC pin of U2. The RT pin of U2 has a 110-kΩ
resistor to ground, and the SYNC pin for this device acts
as an input. The 1.8-V supply operates synchronously with
the 3.3-V supply and their switching node rising edges are
approximately 180° out of phase allowing for a reduction
in the input voltage ripple. See Figure 19 for this wave
form.
www.ti.com
SLVS456C − OCTOBER 2003 − REVISED OCTOBER 2004
U1
TPS54350PWP
5V
+
1
C2
220 µF
D-Case Alum
C3
10 µF
2
R2
100 kΩ
3
4
R3
43.2 kΩ
5
6
7
8
(1)
VIN
BOOT
VIN
PH
UVLO
VBIAS
SYNC
PGND
C9
(1)
2200 pF
Q1
12
10
C4
220 µF
D-Case Alum
C5
1 µF
9
+
C6
22 µF
3 2 1
R9
130 kΩ
VOUT
–5 V @ 1.5 A
R8
100 kΩ
C10
470 pF
R4
3.09 kΩ
C8
470 pF
C4: Panasonic EEVFK1A221XP
L1: Coilcraft DO3340P-223
Q1: International Rectifier IRF7402
C7
10 µF
4
11
VSENSE
COMP
PWRPAD
17
GND
2
8 7 6 5
13
AGND
ENA
1
14
PH
RT
L1
22 µH
15
LSG
PWRGD
C1
0.1 µF
16
R1
21.5 kΩ
(1) Do not connect to system ground plane.
(1)
Figure 27. Inverting Power Supply, 5 V to −5 V at 1.5 A
In Figure 27 the TPS54350 is configured as an inverting
supply. The −5-V output is at the pins which would normally
be connected to ground. The output junction of the LC
output filter, which is normally the output in a buck
converter, is tied to ground. An additional 10-µF capacitor,
C7, is required from the output to VIN.
U1
TPS54350PWP
1
+12 V
C2
10 µF
16 V
2
3
4
5
6
R1
80.6 kW
7
8
VIN
BOOT
VIN
PH
UVLO
PH
PWRGD
LSG
RT
VBIAS
SYNC
PGND
ENA
AGND
COMP
VSENSE
PWRPAD
17
C7
0.01 µF
16
L1
10 µH
VOUT 5 V @ 3 A
15
14
13
12
11
D1
10
C5
1 µF
9
R2
5.90 kΩ
C9
10 pF
D1: On Semiconductor MBRS340T3
C3: Panasonic EEVFK0J221P
L1: Coilcraft DO3316P-103
C1
0.1 µF
C3 +
220 µF
6.3 V
C4
10 µF
6.3 V
R3
4.64 kΩ
R4
7.50 kΩ
C8
4700 pF
R5
1 kΩ
Figure 28. 12-V to 5-V Using Aluminum Electrolytic for LCD TV
Figure 28 is an example of a 12-V to 5-V converter using economical output filter components.
21
www.ti.com
SLVS456C − OCTOBER 2003 − REVISED OCTOBER 2004
4
700 kHz
3.5
600 kHz
500 kHz
3
2.5
400 kHz
2
1.5
1
300 kHz
0.5
200 kHz
VO = 2.5 V VO = 3.3 V
600
500
400
VO = 1.8 V
300
VO = 1.5 V
200
VO = 0.9 V
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Figure 31
VIN(UVLO) START AND STOP
vs
FREE-AIR TEMPERATURE
TJ = 25°C
4.3
500
400
300
VI − Input Voltage − V
VO = 3.3 V
RT Resistance − kW
Maximum Switching Frequency − kHz
200 kHz
4.5
175
150
125
100
Start
4.1
3.9
Stop
3.7
VO = 1.2 V
75
VO = 1.5 V
IO < 0.1 A
50
200
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
300
400
500
600
3.5
−50 −25
700
Figure 32
0
Figure 33
ENABLED SUPPLY CURRENT
vs
INPUT VOLTAGE
TJ = 25°C
6
5
4
7.5
VBIAS − Bias Voltage − V
Disabled Supply Current − mA
7
100 125 150
8.0
TJ = 25°C
8
75
BIAS VOLTAGE
vs
INPUT VOLTAGE
1.3
TJ = 25°C
fS = 500 kHz
50
Figure 34
DISABLED SUPPLY CURRENT
vs
INPUT VOLTAGE
10
25
TA − Free-Air Temperature − 5C
Switching Frequency − kHz
VI − Input Voltage − V
Enabled Supply Current − mA
1
VI − Input Voltage − V
200
9
2
1.5
VO = 2.5 V
600
0
300 kHz
RT RESISTANCE
vs
SWITCHING FREQUENCY
700
100
3
2.5
0
225
VO = 0.9 V
400 kHz
Figure 30
MAXIMUM SWITCHING FREQUENCY
vs
INPUT VOLTAGE
200
500 kHz
4
3.5
0.5
IO > 0.5 A
Figure 29
VO = 1.8 V
600 kHz
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
VI − Input Voltage − V
VI − Input Voltage − V
1.2
1.1
1.0
7.0
6.5
6.0
5.5
5.0
4.5
3
0
5
10
15
VI − Input Voltage − V
Figure 35
22
VO = 1.2 V
100
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
700 kHz
4.5
0
800
IO = 0 A
5
700
Minimum Output Voltage − V
Minimum Output Voltage − V
Maximum Switching Frequency − kHz
IO > 0.5 A
4.5
0
5.5
800
5.5
5
MINIMUM OUTPUT VOLTAGE
vs
INPUT VOLTAGE
MAXIMUM SWITCHING FREQUENCY
vs
INPUT VOLTAGE
MINIMUM OUTPUT VOLTAGE
vs
INPUT VOLTAGE
20
25
0.9
4.0
0
5
10
15
VI − Input Voltage − V
Figure 36
20
25
0
5
10
15
VI − Input Voltage − V
Figure 37
20
25
www.ti.com
SLVS456C − OCTOBER 2003 − REVISED OCTOBER 2004
POWER GOOD THRESHOLD
vs
JUNCTION TEMPERATURE
6.0
0.8912
97.5
97.0
96.5
96.0
−50 −25
0
25
50
75
0.8910
5.5
0.8908
0.8906
0.8904
0.8902
5.0
4.5
0.8900
4.0
0.8898
−50 −25
100 125 150
TJ = 25°C
VI = 12 V
VIN = 12 V
Current Limit − A
Vref − Internal Voltage Reference − V
PWRGD − Power Good Threshold − %
98.0
TJ − Junction Temperature − 5C
0
25
50
75
5.0
100 125 150
7.5
10.0
TJ − Junction Temperature − 5C
ON RESISTANCE
vs
JUNCTION TEMPERATURE
15.0
17.5
20.0
Figure 40
PH VOLTAGE
vs
SUPPLY CURRENT
SLOW START CAPACITANCE
vs
TIME
2
150
12.5
VI − Input Voltage − V
Figure 39
Figure 38
0.50
VI = 12 V
IO = 0.5 A
Slow Start Capacitance − µ F
0.45
130
1.75
PH Voltage − V
On Resistance − mW
CURRENT LIMIT
vs
INPUT VOLTAGE
INTERNAL VOLTAGE REFERENCE
vs
JUNCTION TEMPERATURE
110
90
VI = 4.5 V
1.50
VI = 12 V
1.25
70
RSS = 2 kΩ
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
50
−50 −25
1
0
25
50
75
0
100
100 125 150
150
250
0
300
Figure 41
5
4
9
4.5
2
1.5
Slow Start Time − ms
Hiccup Time − ms
8
2.5
7
6
5
4
1
3
0.5
0
450
550
650
Switching Frequency − kHz
Figure 44
750
2
250
50
60
70
80
INTERNAL SLOW START TIME
vs
SWITCHING FREQUENCY
10
3
40
Figure 43
HICCUP TIME
vs
SWITCHING FREQUENCY
3.5
30
t − Time − ms
4.5
350
20
Figure 42
POWER GOOD DELAY
vs
SWITCHING FREQUENCY
250
10
I CC − Supply Current − mA
TJ − Junction Temperature − 5C
Power Good Delay − ms
200
4
3.5
3
2.5
2
1.5
350
450
550
650
Switching Frequency − kHz
Figure 45
750
1
250
350
450
550
650
750
Switching Frequency − kHz
Figure 46
23
www.ti.com
SLVS456C − OCTOBER 2003 − REVISED OCTOBER 2004
FREE-AIR TEMPERATURE
vs
MAXIMUM OUTPUT CURRENT
MAXIMUM OUTPUT VOLTAGE
vs
INPUT VOLTAGE
POWER DISSIPATION
vs
FREE-AIR TEMPERATURE
14
140
2.5
100
80
60
40
10
8
6
4
0
0
0.5
1
1.5
2
2.5
I O − Output Current − A
Figure 47
3
3.5
2
θJA = 42.1°C/W
1.5
1
θJA = 191.9°C/W
0.5
2
20
0
24
PD − Power Dissipation − W
12
120
V O − Output Voltage − V
T A − Free-Air Temperature − ° C
TJ= 125°C
0
0
5
10
15
V I − Input Voltage − V
Figure 48
20
25
25
45
65
85
105
TA − Free-Air Temperature − °C
Figure 49
125
www.ti.com
SLVS456C − OCTOBER 2003 − REVISED OCTOBER 2004
THERMAL PAD MECHANICAL DATA
PWP (R−PDSO−G16)
PowerPADt PLASTIC SMALL−OUTLINE
PPTD024
25
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