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SLUS549C − DECEMBER 2002 − REVISED AUGUST 2004
FEATURES
Small 3 mm × 3 mm MLP Package
Charges and Powers Systems from Either AC
DESCRIPTION
The bqTINY-II series are highly integrated and flexible
Li-Ion linear charge and system power management
devices targeted at space limited charger applications.
The bqTINY-II series offer integrated USB-port and
ac-adapter supply management with autonomous
power-source selection, power FET and current
sensor, high-accuracy current and voltage regulation,
charge status, and charge termination, in a single
monolithic device.
Adapter or USB With Autonomous
Power-Source Selection
Integrated USB Control With Selectable
100 mA and 500 mA Charge Rates
Ideal for Low-Dropout Charger Designs for
Single-Cell Li-Ion or Li-Pol Packs in Space
Limited Portable Applications
Integrated Power FET and Current Sensor for
The bqTINY-II automatically selects the USB-Port or
the ac-adapter as the power source for the system. In
the USB configuration, the host can select from the two
preset charge rates of 100 mA and 500 mA. In the
ac−adapter configuration an external resistor sets the
magnitude of the system or charge current.
Up to 1-A Charge Applications From AC
Adapter
Precharge Conditioning With Safety Timer
Power Good (AC Adapter Present) Status
Output
Optional Battery Temperature Monitoring
The bqTINY-II charges the battery in three phases:
conditioning, constant current, and constant voltage.
Charge is terminated based on minimum current. An
internal charge timer provides a backup safety for
charge termination. The bqTINY-II automatically restarts the charge if the battery voltage falls below an
internal threshold. The bqTINY-II automatically enters
sleep mode when both supplies are removed.
Before and During Charge
Automatic Sleep Mode for Low-Power
Consumption
APPLICATIONS
PDAs, MP3 Players
Digital Cameras
Internet Appliances
Smartphones
VDC
AC
ADAPTER
PACK+
bq24020DRC
1
AC
OUT
+
10
GND
VBUS
USB
PORT
GND
BATTERY PACK
SYSTEM
PACK−
2
USB
TS
9
3
STAT1
CE
8
4
STAT2 ISET2
7
5
VSS
6
SYSTEM
INTERFACE
RSET
ISET1
D+
D−
UDG−02184
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
bqTINY is a trademark of Texas Instruments Incorporated.
!"#$%&'(!$" !) *+%%,"( ') $# -+.!*'(!$" /'(,0 %$/+*()
*$"#$%& ($ )-,*!#!*'(!$") -,% (1, (,%&) $# ,2') ")(%+&,"() )('"/'%/ 3'%%'"(40
%$/+*(!$" -%$*,))!"5 /$,) "$( ",*,))'%!.4 !"*.+/, (,)(!"5 $# '.. -'%'&,(,%)0
Copyright 2002, Texas Instruments Incorporated
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SLUS549C − DECEMBER 2002 − REVISED AUGUST 2004
DESCRIPTION (CONTINUED)
In addition to the standard features, different versions of the bqTINY-II offer a multitude of additional features. These include
temperature sensing input for detecting hot or cold battery packs; power good (PG) output indicating the presence of input
power; a TTL-level charge enable input (CE) used to disable or enable the charge process; and a TTL-level timer and
taper−detect enable (TTE) input used to disable or enable the fast-charge timer and charge termination.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOSFET gates.
ORDERING INFORMATION
TJ
CHARGE
REGULATION
VOLTAGE (V)(1)
OPTIONAL
FUNCTIONS(1)
FASTCHARGE
TIMER
(Hours)
TAPER
TIMER
4.2
CE and TS
5
Yes
4.2
PG and CE
5
4.2
CE and TTE
5
4.2
TTE and TS
4.2
CE and TS
−40°C
−40
C to 125
125°C
C
4.2
TE and TS
USB TAPER
THRESHOLD
PART
NUMBER(2)
MARKINGS
10% of ISET1 Level
bq24020DRCR
AZS
Yes
10% of ISET1 Level
bq24022DRCR
AZU
Yes
10% of ISET1 Level
bq24023DRCR
AZV
5
Yes
10% of ISET1 Level
bq24024DRCR
AZW
7
Yes
10% of ISET1 Level
bq24025DRCR
AZX
No
10% of selected
USB charge rate
bq24026DRCR
ANR
7
(1) The DRC package is available taped and reeled only in quantities of 3,000 devices per reel.
DISSIPATION RATINGS
PACKAGE
θJA
TA < 40°C
POWER RATING
DRC(1)
46.87 °C/W
1.5 W
DERATING FACTOR
ABOVE TA = 25°C
0.021 W/°C
(1) This data is based on using the JEDEC High-K board and the exposed die pad is connected to a copper pad on the board. This is connected to the
ground plane by a 2x3 via matrix.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
bq24020, bq24022
bq24023, bq24024
bq24025, bq24026
UNITS
−0.3 to 7.0
V
Input voltage(2)
AC, CE, ISET1, ISET2, OUT, PG, STAT1, STAT2,
TE, TS, TTE, USB
Output sink/source current
STAT1, STAT2, PG
15
mA
Output current
TS
200
µA
Output current
OUT
1.5
A
Operating free−air temperature range, TA
Junction temperature range, TJ
Storage temperature, Tstg
−40 to 125
°C
−65 to 150
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
300
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to VSS.
RECOMMENDED OPERATING CONDITIONS(1)
MIN
2
NOM
MAX
UNIT
Supply voltage (from AC input), VCC
4.5
6.5
V
Supply voltage (from USB input), VCC
4.35
6.5
V
Operating junction temperature range, TJ
−40
125
°C
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SLUS549C − DECEMBER 2002 − REVISED AUGUST 2004
ELECTRICAL CHARACTERISTICS
over 0C ≤ TJ ≤ 125C and recommended supply voltage, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT CURRENT
VCC current, ICC(VCC)
Standby current, ICC(STBY)
VCC > VCC(min)
Sum of currents into OUT pin,
VCC < V(SLP)
CE = High,
0C ≤TJ ≤ 85C
Input current on OUT pin, IIB(OUT)
Charge DONE,
Sleep current, ICC(SLP)
1.2
2.0
2
5
mA
150
VCC > VCC(MIN)
1
5
Input current on CE pin, IIB(CE)
1
Input bias current on TTE pin, IIB(TTE)
1
Input bias current on TE pin, IIB(TE)
1
µA
VOLTAGE REGULATION VO(REG) + V(DO−MAX) ≤ VCC , I(TERM) < IO(OUT) ≤ 1 A
Output voltage, VO(REG)
4.20
TA = 25C
Voltage regulation accuracy
AC dropout voltage (V(AC)−V(OUT)), V(DO)
USB dropout voltage (V(USB) − V(OUT)),
V(DO)
VO(OUT) = VO(REG),
VO(REG) + V(DO−MAX)) ≤ VCC,
VO(OUT) = VO(REG)
VO(REG) + V(DO−MAX)) ≤ VCC,
VO(OUT) = VO(REG)
VO(REG) + V(DO−MAX)) ≤ VCC,
V
−0.35%
0.35%
−1%
1%
IO(OUT) = 1A
ISET2 = High
ISET2 = Low
350
500
350
500
60
100
mV
CURRENT REGULATION
VI(OUT) >V(LOWV), VI(AC) −VI(OUT) >V(DO−MAX),
VCC ≥ 4.5 V,
VCC(MIN) ≥ 4.5 V,
VI(OUT) > V(LOWV),
VUSB − VI(OUT) > V(DO−MAX),
ISET2 = Low
AC output current range, IO(OUT)(1)
USB output current range, IO(OUT)
VCC(MIN) ≥ 4.5 V,
VI(OUT) > V(LOWV),
VUSB − VI(OUT) > V(DO−MAX),
ISET2 = High
Voltage on ISET1 pin, VCC ≥ 4.5 V, VIN ≥ 4.5 V,
VI(OUT) > V(LOWV), VIN − VI(OUT) > V(DO−MAX)
50 mA ≤ IO(OUT) ≤ 1 A
Output current set voltage, V(SET)
Output current set factor, K(SET)
50
1000
80
100
400
500
2.463
2.500
2.538
mA
V
307
322
337
10 mA ≤ IO(OUT) < 50 mA
296
320
346
1 mA ≤ IO(OUT) < 10 mA
246
320
416
2.8
3.0
3.2
V
250
375
500
ms
100
mA
270
mV
PRECHARGE AND SHORT-CIRCUIT CURRENT REGULATION
Precharge to fast-charge transition
threshold, V(LOWV)
Voltage on OUT pin
Deglitch time for fast-charge to precharge
transition
Precharge range, IO(PRECHG)(2)
VCC(MIN) ≥ 4.5 V, tFALL = 100 ns, 10 mV overdrive
VI(OUT) decreasing below threshold
0 V < VI(OUT) < V(LOWV), t < t(PRECHG)
Precharge set voltage, V(PRECHG)
Voltage on ISET1 pin,
0 V < VI(OUT) > V(LOWV),
(1)
IO(OUT) +
ǒK(SET)
(2)
IO(PRECHG) +
VO(REG) = 4.2 V,
t < t(PRECHG)
5
240
255
Ǔ
V(SET)
RSET
ǒK(SET)
Ǔ
V(PRECHG)
RSET
3
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SLUS549C − DECEMBER 2002 − REVISED AUGUST 2004
ELECTRICAL CHARACTERISTICS(continued)
over 0C ≤ TJ ≤ 125C and recommended supply voltage, unless otherwise noted
PARAMETER
TEST CONDITIONS
CHARGE TAPER AND TERMINATION DETECTION
Charge taper detection range, I(TAPER)(3) VI(OUT) > V(RCH),
USB-100 charge taper
detection level
bq24026
USB-500 charge taper
detection level
bq24026
Charge taper detection set voltage,
V(TAPER)
Charge termination detection set voltage,
V(TERM)(4)
MIN
TYP
MAX
t < t(TAPER)
5
VI(OUT) > V(RCH),
ISET2 = Low
6.5
9
11
VI(OUT) > V(RCH),
ISET2 = High
32
44
55
235
250
265
11
18
25
250
375
500
Deglitch time for TAPER detection,
tTPRDET
Voltage on ISET1 pin, VO(REG) = 4.2 V,
VI(OUT) > V(RCH),
t < t(TAPER)
Voltage on ISET pin,
VO(REG) = 4.2 V,
VI(OUT) > V(RCH)
VCC(MIN) ≥ 4.5 V,
tFALL = 100 ns
charging current increasing or decreasing above
and below,
10 mV overdrive
Deglitch time for termination detection,
tTRMDET
VCC(MIN) ≥ 4.5 V,
tFALL = 100 ns
charging current decreasing below,
10 mV overdrive
UNIT
100
mA
mV
ms
250
375
500
Low-voltage threshold, V(LTF)
2.475
2.500
2.525
High-voltage threshold, V(HTF)
0.485
0.500
0.515
Current source, I(TS)
96
102
108
µA
Deglitch time for temperature fault, t(DEGL)
250
375
500
ms
VO(REG)
−0.115
VO(REG)
−0.10
VO(REG)
−0.085
V
250
375
500
ms
IO = 5 mA
ISET2, CHARGE ENABLE (CE), TIMER AND TERMINATION ENABLE (TTE), AND TIMER ENABLE (TE) INPUTS
0.25
V
TEMPERATURE SENSE COMPARATOR
V
BATTERY RECHARGE THRESHOLD
Recharge threshold, VRCH
Deglitch time for recharge detect, t(DEGL)
VCC(MIN) ≥ 4.5 V,
tFALL = 100 ns
decreasing below or increasing above threshold,
10 mV overdrive
STAT1, STAT2, and PG OUTPUTS
Low-level output saturation voltage, VOL
IIL = 10 µA
IIL = 20 µA
Low-level input voltage, VIL
High-level input voltage, VIH
CE, TE or TTE low-level input current, IIL
0
ISET2 high-Z input current, IIH
(3)
IO(TAPER) +
4
ǒK(SET)
−20
Ǔ
µA
40
1
V(TAPER)
R SET
1
IISET2 = 0
IISET2 = VCC
ISET2 high-level input current, IIH
V
−1
CE, TE or TTE high-level input current, IIH
ISET2 low-level input current, IIL
0.4
1.4
V
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SLUS549C − DECEMBER 2002 − REVISED AUGUST 2004
ELECTRICAL CHARACTERISTICS(continued)
over 0C ≤ TJ ≤ 125C and recommended supply voltage, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TIMERS
Precharge time, t(PRECHG)
Taper time, t(TAPER)
Charge time, t(CHG)
1,620
1,800
1,930
bq24020
bq24022
bq24023
bq24024
bq24025
1,620
1,800
1,930
bq24020
bq24022
bq24023
bq24024
16,200
18,000
19,300
bq24025,
bq24026
22,680
25,200
27,720
s
Timer fault recovery current, I(FAULT)
s
µA
200
SLEEP COMPARATOR
Sleep-mode entry threshold voltage,
V(SLP)
Sleep mode exit threshold voltage,
V(SLPEXIT)
VCC ≤ VI(OUT)
+80 mV
2.3 V ≤ VI(OUT) ≤ VO(REG)
2.3 V ≤ VI(OUT) ≤ VO(REG)
AC and USB decreasing below threshold,
tFALL = 100 ns,
10 mV overdrive
Sleep mode deglitch time
VCC ≥ VI(OUT)
+190mV
250
375
500
V
ms
THERMAL SHUTDOWN THRESHOLDS
Thermal trip threshold, T(SHTDWN)
165
Thermal hysteresis
15
°C
UNDERVOLTAGE LOCKOUT
Undervoltage lockout V(UVLO)
Decreasing VCC
Hysteresis
IO(TAPER) +
IO(TERM) +
2.5
27
(3)
(4)
2.4
ǒK(SET)
2.6
V
mV
Ǔ
V(TAPER)
R SET
ǒK(SET)
Ǔ
V(TERM)
RSET
5
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SLUS549C − DECEMBER 2002 − REVISED AUGUST 2004
DRC PACKAGE
(TOP VIEW)
VSS STAT2 STAT1 USB
5
4
3
2
DRC PACKAGE
(TOP VIEW)
VSS STAT2 STAT1 USB
AC
1
5
bq24020DRC
bq24025DRC
6
7
ISET1 ISET2 CE
10
TS
OUT
DRC PACKAGE
(TOP VIEW)
VSS STAT2 STAT1 USB
5
4
3
3
2
1
bq24022DRC
9
8
4
AC
2
6
7
8
ISET1 ISET2 PG
9
10
CE
OUT
DRC PACKAGE
(TOP VIEW)
AC
VSS STAT2 STAT1 USB
1
5
4
3
2
AC
1
bq24023DRC
bq24024DRC
6
7
8
ISET1 ISET2 CE
9
10
6
8
ISET1 ISET2 TTE
TTE OUT
DRC PACKAGE
(TOP VIEW)
VSS STAT2 STAT1 USB
5
4
3
AC
2
1
9
10
TS
OUT
bq24026DRC
6
7
8
ISET1 ISET2 TE
6
7
9
10
TS
OUT
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SLUS549C − DECEMBER 2002 − REVISED AUGUST 2004
TERMINAL FUNCTIONS
TERMINAL
NAME
bq24020
bq24025 bq24022 bq24023 bq24024 bq24026
I/O
DESCRIPTION
AC
1
1
1
1
1
I
AC charge input voltage
CE
8
9
8
−
−
I
Charge enable input (active low)
ISET1
6
6
6
6
6
I
Charge current set point for AC input and precharge and taper set
point for both AC and USB
ISET2
7
7
7
7
7
I
Charge current set point for USB port (high=500 mA, Low=100
mA, hi-z=disable USB charge)
OUT
10
10
10
10
10
O
Charge current output
PG
−
8
−
−
−
O
Powergood status output (active low)
STAT1
3
3
3
3
3
O
Charge status output 1 (open-drain)
STAT2
4
4
4
4
4
O
Charge status output 2 (open-drain)
TE
−
−
−
−
8
I
Timer enable input (active low)
TS
9
−
−
9
9
I
Temperature sense input
TTE
−
−
9
8
−
I
Timer and termination enable input (active low)
USB
2
2
2
2
2
I
USB charge input voltage
VSS
5
5
5
5
5
−
Ground input
−
There is an internal electrical connection between the exposed
thermal pad and VSS pin of the device. The exposed thermal pad
must be connected to the same potential as the Vss pin on the
printed circuit board. Do not use the thermal pad as the primary
ground input for the device. VSS pin must be connected to
ground at all times
Exposed
Thermal
Pad
pad
pad
pad
pad
pad
7
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SLUS549C − DECEMBER 2002 − REVISED AUGUST 2004
FUNCTIONAL BLOCK DIAGRAM
AC
USB
VI(AC)
AC
VI(OUT)
VI(REG)
VI(USB)
VI(OUT)
+
VI(ISET)
sensefet
VI(SET)
REF
BIAS
AND
UVLO
OUT
ISET1
+
USB
AC/USB
V(SET)
VI(ISET-USB)
CHG
ENABLE
AC/USB
sensefet
VO(REG)
sensefet
UVLO
V(HTF)
VI(ISET-USB)
100 mA/500 mA
*
I(TS)
SUSPEND
THERMAL
SHUTDOWN
TS
AC/USB
CHG ENABLE
*
V(LTF)
500 mA/ 100 mA
CE
TTE
OR
TE
VI(OUT)
VI(AC)
*
SLEEP (AC)
VI(OUT)
VI(USB)
*
SLEEP (USB)
VO(REG)
VI(OUT)
RECHARGE
*
VI(OUT)
*
PRECHARGE
VBAT
CHARGE
CONTROL,
TIMER,
AND
DISPLAY
LOGIC
ISET1
PRECHARGE
(C/10)
500 mA/ 100 mA
ISET2
USB CHARGE
PG
VI(SET)
VI(SET)
VI(SET)
*
t(TAPER) TIMER
*
TAPER
STAT1
TERM
STAT2
VSS
* SIGNAL DEGLITCHED
8
UDG−02185
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SLUS549C − DECEMBER 2002 − REVISED AUGUST 2004
TYPICAL CHARACTERISTICS
AC DROPOUT VOLTAGE
vs
JUNCTION TEMPERATURE
450
IO(OUT) = 1000 mA
400
Dropout Voltage − mV
350
IO(OUT) = 750 mA
300
250
IO(OUT) = 500 mA
200
150
IO(OUT) = 250 mA
100
50
0
0
100
50
TJ − Junction Temperature − C
150
Figure 1
The bqTINYII supports a precision Li-Ion, Li-Pol charging system suitable for single-cells. Figure 3 shows a typical charge
profile, application circuit and Figure 4 shows an operational flow chart.
Regulation
Voltage
Pre-Conditioning
Phase
Voltage Regulation
and Charge Termination Phase
Current Regulation
Phase
Regulation
Current
Charge
Voltage
Minimum
Charge
Voltage
Charge
Complete
Charge
Current
Pre-Conditioning
and Taper Detect
t(PRECHG)
t(CHG)
t(TAPER)
Figure 2. Typical Charging Profile
9
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SLUS549C − DECEMBER 2002 − REVISED AUGUST 2004
FUNCTIONAL DESCRIPTION
AC ADAPTER
VDC
bq24023DRC
1
AC
0.1 µF
GND
D+
D−
VBUS
PACK+
OUT 10
PACK−
2
USB
TTE
9
3
STAT1
CE
8
4
STAT2 ISET2 7
5
VSS
SYSTEM
+
SYSTEM
INTERFACE
GND
USB PORT
ISET1 6
RSET
UDG−02184
Figure 3. Typical Application Circuit
10
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SLUS549C − DECEMBER 2002 − REVISED AUGUST 2004
POR
SLEEP MODE
Vcc > VI(OUT)
No
checked at all times
Indicate SLEEP
MODE
Yes
VI(OUT)<V(LOWV)
Regulate
IO(PRECHG)
Reset and Start
t(PRECHG)timer
Yes
Indicate Charge−
In−Progress
No
Reset all timers,
Start t(CHG) timer
Regulate Current
or Voltage
Indicate Charge−
In−Progress
No
VI(OUT)<V(LOWV)
Yes
Yes
t(PRECHG)
Expired?
No
t(CHG) Expired?
Yes
No
Yes
Yes
Fault Condition
VI(OUT)<V(LOWV)
Indicate Fault
No
I(TERM)
detection?
Yes
No
VI(OUT) > V(RCH)?
No
No
t(TAPER)
Expired?
(1)
I(TAPER)
detection?
Enable (FAULT)
I
current
Yes
No
No
Yes
Yes
VI(OUT) > V(RCH)?
Turn off charge
Yes
Yes
Indicate DONE
Disable (FAULT)
I
current
No
VI(OUT) < V(RCH)?
(1) t(TAPER) does not apply to bq24026
Figure 4. Operational Flow Chart
11
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SLUS549C − DECEMBER 2002 − REVISED AUGUST 2004
FUNCTIONAL DESCRIPTION
AUTONOMOUS POWER SOURCE SELECTION
As default the bqTINY-II attempts to charge from the AC input. If AC input is not present, the USB is selected. If both inputs
are available, the AC adapter has the priority. See Figure 5 for details.
AC > BATTERY
AC MODE
USB MODE
AC < BATTERY
USB > BATTERY
UDG−02187
Figure 5. Typical Charging Profile
TEMPERATURE QUALIFICATION (bq24020, bq24024, bq24025, and bq24026 only)
The bqTINY-II continuously monitors battery temperature by measuring the voltage between the TS and VSS pins.
An internal current source provides the bias for most common 10-kΩ negative-temperature coefficient thermistors
(NTC) (see Figure 6). The device compares the voltage on the TS pin against the internal V(LTF) and V(HTF) thresholds
to determine if charging is allowed. Once a temperature outside the V(LTF) and V(HTF) thresholds is detected the
device immediately suspend the charge. The device suspend charge by turning off the powerFET and holding the
timer value (i.e. timers are NOT reset). Charge is resumed when the temperature returns to the normal range.
The allowed temperature range for 103AT type thermistor is 0C to 45C. However the user may modify these
thresholds by adding two external resistors. See Figure 7.
BATTERY PRE-CONDITIONING
During a charge cycle if the battery voltage is below the V(LOWV) threshold, the bqTINY-II applies a precharge current,
Io(PRECHG), to the battery. This feature revives deeply discharged cells. The resistor connected between the ISET1
and Vss, RSET, determines the precharge rate. The V(PRECHG) and K(SET) parameters are specified in the
specifications table. Note that this applies to both AC and USB charging.
I O (PRECHG) +
V(PRECGH)
K(SET)
RSET
(1)
The bqTINY-II activates a safety timer, t(PRECHG), during the conditioning phase. If V(LOWV) threshold is not reached
within the timer period, the bqTINY-II turns off the charger and enunciates FAULT on the STATx pins. Please refer
to the TIMER FAULT RECOVERY section for additional details.
PACK+
bqTINYII
PACK−
ITS
TS
LTF
HTF
9
VLTF
TEMP
+
ITS
BATTERY
PACK
VHTF
LTF
RT1
9
VLTF
RT2
HTF
Figure 6. Temperature Sensing Configuration
PACK−
TS
NTC
UDG−02186
12
PACK+
bqTINYII
+
TEMP
NTC
BATTERY
PACK
VHTF
UDG−02188
Figure 7. Temperature Sensing Thresholds
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SLUS549C − DECEMBER 2002 − REVISED AUGUST 2004
FUNCTIONAL DESCRIPTION
BATTERY CHARGE CURRENT
The bqTINY-II offers on-chip current regulation with programmable set point. The resistor connected between the
ISET1 and VSS, RSET, determines the AC charge rate. The V(SET) and K(SET) parameters are specified in the
specifications table.
V(SET)
I O (OUT) +
K(SET)
RSET
(2)
When charging from a USB port, the host controller has the option of selecting either 100 mA or 500 mA charge rate
using ISET2 pin. A low-level signal sets current at 100 mA and a high level signal sets current at 500 mA. A high-Z
input disables USB charging
BATTERY VOLTAGE REGULATION
The voltage regulation feedback is through the OUT pin. This input is tied directly to the positive side of the battery
pack. The bqTINY-II monitors the battery−pack voltage between the OUT and VSS pins. When the battery voltage
rises to VO(REG) threshold, the voltage regulation phase begins and the charging current begins to taper down.
As a safety backup, the bqTINY-II also monitors the charge time in the charge mode. If charge is not terminated within
this time period, t(CHG), the bqTINY-II turns off the charger and enunciates FAULT on the STATx pins. Please refer
to the TIMER FAULT RECOVERY section for additional details.
CHARGE TAPER DETECTION, TERMINATION AND RECHARGE
The bqTINY-II monitors the charging current during the voltage regulation phase. Once the taper threshold, I(TAPER),
is detected the bqTINY-II initiates the taper timer, t(TAPER). Charge is terminated after the timer expires. The resistor
connected between the ISET1 and VSS, RSET, determines the taper detection level. The V(TAPER) and K(SET)
parameters are specified in the specifications table. Note that this applies to both AC and USB charging.
I (TAPER) +
V(TAPER)
K(SET)
RSET
(3)
The bqTINY-II resets the taper timer in the event that the charge current returns above the taper threshold, I(TAPER).
In addition to the taper current detection, the bqTINY-II terminates charge in the event that the charge current falls
below the I(TERM) threshold. This feature allows for quick recognition of a battery removal condition or insertion of
a fully charged battery. Note that charge timer and taper timer are bypassed for this feature. The resistor connected
between the ISET1 and VSS, RSET, determines the taper detection level. The V(TERM) and K(SET) parameters are
specified in the specifications table. Note that this applies to both AC and USB charging.
I (TERM) +
V(TERM)
K(SET)
R SET
(4)
After charge termination, the bqTINY-II re-starts the charge once the voltage on the OUT pin falls below the V(RCH)
threshold. This feature keeps the battery at full capacity at all times.
NOTE ON bq24026
The bq24026 monitors the charging current during the voltage regulation phase. Once the taper threshold, I(TAPER),
is detected the bq24026 terminates the charge. There is no taper timer, t(TAPER) for this version.
The resistor connected between the ISET1 and VSS, RSET, determines the taper detection level for AC input. For USB
charge, taper level is fixed at 10% of the 100- or 500-mA charge rate.
Also note that there is I(TERM) detection in bq24026.
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SLUS549C − DECEMBER 2002 − REVISED AUGUST 2004
FUNCTIONAL DESCRIPTION
SLEEP MODE
The bqTINY-II enters the low-power sleep mode if both AC and USB are removed from the circuit. This feature
prevents draining the battery during the absence of input supply.
CHARGE STATUS OUTPUTS
The open-drain STAT1 and STAT2 outputs indicate various charger operations as shown in the following table. These
status pins can be used to drive LEDs or communicate to the host processor. Note that OFF indicates the open-drain
transistor is turned off.
Table 1. Status Pins Summary
CHARGE STATE
STAT1
STAT2
Precharge in progress
ON
ON
Fast charge in progress
ON
OFF
Charge done
OFF
ON
Charge suspend (temperature)
OFF
OFF
Timer fault
OFF
OFF
Sleep mode
OFF
OFF
() OFF means the open-drain output transistor on the STAT1 and
STAT2 pins is in an off state.
PG OUTPUT
The open-drain PG (Power Good) indicates when the AC adapter is present. The output turns ON when a valid
voltage is detected. This output is turned off in the sleep mode. The PG pin can be used to drive an LED or
communicate to the host processor.
CE INPUT (CHARGE ENABLE)
The CE digital input is used to disable or enable the charge process. A low-level signal on this pin enables the charge
and a high-level signal disables the charge and places the device in a low-power mode. A high-to-low transition on
this pin also resets all timers and timer fault conditions. Note that this applies to both AC and USB charging.
TTE INPUT (TIMER AND TERMINATION ENABLE)
The TTE digital input is used to disable or enable the fast-charge timer and charge taper detection. A low-level signal
on this pin enables the fast-charge timer and taper timer and a high-level signal disables this feature. Note that this
applies to both AC and USB charging.
THERMAL SHUTDOWN AND PROTECTION
The bqTINY-II monitors the junction temperature, TJ, of the die and suspends charging if TJ exceeds T(SHTDWN).
Charging resumes when TJ falls below T(SHTDWN) by approximately 15C.
TE INPUT (TIMER ENABLED)
The TE digital input is used to disable or enable the fast-charge timer. A low-level signal on this pin enables the
fast-charge timer and a high-level signal disables this feature.
Note that this applies to both AC and USB charging.
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SLUS549C − DECEMBER 2002 − REVISED AUGUST 2004
FUNCTIONAL DESCRIPTION
TIMER FAULT RECOVERY
As shown in Figure 4, bqTINY-II provides a recovery method to deal with timer fault conditions. The following
summarizes this method:
Condition #1: Charge voltage above recharge threshold (V(RCH)) and timeout fault occurs
Recovery method: bqTINY-II waits for the battery voltage to fall below the recharge threshold. This could happen
as a result of a load on the battery, self-discharge or battery removal. Once the battery falls below the recharge
threshold, the bqTINY-II clears the fault and starts a new charge cycle. A POR or CE or TTE toggle also clears the
fault.
Condition #2: Charge voltage below recharge threshold (V(RCH)) and timeout fault occurs
Recovery method: Under this scenario, the bqTINY-II applies the I(FAULT) current. This small current is used to detect
a battery removal condition and remains on as long as the battery voltage stays below the recharge threshold. If the
battery voltage goes above the recharge threshold, then the bqTINY-II disables the I(FAULT) current and executes the
recovery method described for condition #1. Once the battery falls below the recharge threshold, the bqTINY-II clears
the fault and starts a new charge cycle. A POR or CE or TTE toggle also clears the fault.
15
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SLUS549C − DECEMBER 2002 − REVISED AUGUST 2004
APPLICATION INFORMATION
THERMAL CONSIDERATIONS
The bqTINY-II is packaged in a thermally enhanced MLP package. The package includes a thermal pad to provide
an effective thermal contact between the device and the printed circuit board (PCB). Full PCB design guidelines for
this package are provided in the application note entitled, QFN/SON PCB Attachment Application Note (TI Literature
No. SLUA271).
The most common measure of package thermal performance is thermal impedance (θJA) measured (or modeled)
from the device junction to the air surrounding the package surface (ambient). The mathematical expression for θJA
is:
q JA +
TJ * TA
P
(5)
Where:
TJ = device junction temperature
TA = ambient temperature
P = device power dissipation
Factors that can greatly influence the measurement and calculation of θJA include:
whether or not the device is board mounted
trace size, composition, thickness, and geometry
orientation of the device (horizontal or vertical)
volume of the ambient air surrounding the device under test and airflow
whether other surfaces are in close proximity to the device being tested
The device power dissipation, P, is a function of the charge rate and the voltage drop across the internal PowerFET.
It can be calculated from the following equation:
ǒ
Ǔ
P + V IN * V I(BAT)
I O(OUT)
(6)
Due to the charge profile of Li-xx batteries, the maximum power dissipation is typically seen at the beginning of the
charge cycle when the battery voltage is at it’s lowest. See Figure 2.
PCB LAYOUT CONSIDERATIONS
It is important to pay special attention to the PCB layout. The following provides some guidelines:
To obtain optimal performance, the decoupling capacitor from VCC to VSS and the output filter capacitors from
OUT to VSS should be placed as close as possible to the bqTINY, with short trace runs to both signal and VSS
pins.
All low-current VSS connections should be kept separate from the high-current charge or discharge paths from
the battery. Use a single-point ground technique incorporating both the small signal ground path and the power
ground path.
The BAT pin is the voltage feedback to the device and should be connected with its trace as close to the battery
pack as possible.
The high current charge paths into IN and from the OUT pins must be sized appropriately for the maximum charge
current in order to avoid voltage drops in these traces.
The bqTINY-II is packaged in a thermally enhanced MLP package. The package includes a thermal pad to
provide an effective thermal contact between the device and the printed circuit board (PCB). Full PCB design
guidelines for this package are provided in the application note entitled: QFN/SON PCB Attachment Application
Note (TI Literature No. SLUA271).
16
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SLUS549C − DECEMBER 2002 − REVISED AUGUST 2004
DRC (S−PDSO−N10)
CUSTOM DEVICE
PLASTIC SMALL OUTLINE
3,25
2,75
3,25
2,75
PIN 1 INDEX AREA
TOP AND BOTTOM
1,00
0,80
0,20 REF.
0,08
SEATING PLANE
0,05
0,00
2,48
2,23
10
0,50
0,50
0,30
1
5
EXPOSED THERMAL DIE PAD
(SEE NOTE D)
1,74
1,49
10
2,00
6
10
0,30
0,18
0,10
4204102/B 04/02
NOTES:A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Small Outline No-Lead (SON) package configuration.
The package thermal performance may be enhanced by bonding the thermal die pad to an external thermal plane.
17
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