SN65HVD1040-Q1 www.ti.com SLLS753 – FEBRUARY 2007 EMC OPTIMIZED CAN TRANSCEIVER FEATURES APPLICATIONS • • • • • • • • • • • • • • • Qualified for Automotive Applications Customer-Specific Configuration Control Can Be Supported Along With Major-Change Approval Improved Drop-In Replacement for the TJA1040 Meets or Exceeds the Requirements of ISO 11898-5 GIFT / ICT Compliant ESD Protection up to ±8 kV (Human-Body Model) on Bus Pins Low-Current Standby Mode With Bus Wake-Up, <12 µA Max High Electromagnetic Immunity (EMI) Low Electromagnetic Emissions (EME) Bus-Fault Protection of –27 V to 40 V Dominant Time-Out Function Thermal Shutdown Protection Power-Up/Down Glitch-Free Bus Inputs and Outputs – High Input Impedance with Low VCC – Monotonic Outputs During Power Cycling GMW3122 Dual-Wire CAN Physical Layer SAE J2284 High-Speed CAN for Automotive Applications SAE J1939 Standard Data Bus Interface ISO 11783 Standard Data Bus Interface NMEA 2000 Standard Data Bus Interface Industrial Automation – DeviceNet™ Data Buses (Vendor ID #806) • • • • DESCRIPTION The SN65HVD1040 meets or exceeds the specifications of the ISO 11898 standard for use in applications employing a Controller Area Network (CAN). The device is qualified for use in automotive applications. As a CAN transceiver, this device provides differential transmit capability to the bus and differential receive capability to a CAN controller at signaling rates up to 1 megabit per second (Mbps) (1). (1) The signaling rate of a line is the number of voltage transitions that are made per second, expressed in the units bps (bits per second). FUNCTIONAL BLOCK DIAGRAM VCC VCC Dominant Time-Out Temperature Protection 3 VCC/2 5 SPLIT 30 µA TXD Input Logic 1 VCC Driver 7 CANH 10 µA STB RXD 4 6 Standby Mode 8 Output Logic CANL MUX Wake-Up Filter Bus Monitor 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. DeviceNet is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007, Texas Instruments Incorporated SN65HVD1040-Q1 www.ti.com SLLS753 – FEBRUARY 2007 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION (CONTINUED) Designed for operation in especially harsh environments, the SN65HVD1040 features cross-wire, over-voltage, and loss of ground protection from –27 V to 40 V, over-temperature protection, a –12 V to 12 V common-mode range, and withstands voltage transients from –200 V to 200 V, according to ISO 7637. STB (pin 8) provides two different modes of operation: high-speed mode or low-current standby mode. The high-speed mode of operation is selected by connecting STB (pin 8) to ground. If a high logic level is applied to the STB pin of the SN65HVD1040, the device enters a low-current standby mode, while the receiver remains active in a low-power bus-monitor standby mode. In the low-current standby mode, a dominant bit greater than 5 µs on the bus is passed by the bus-monitor circuit to the receiver output. The local protocol controller may then reactivate the device when it needs to transmit to the bus. A dominant-time-out circuit in the SN65HVD1040 prevents the driver from blocking network communication with a hardware or software failure. The time-out circuit is triggered by a falling edge on TXD (pin 1). If no rising edge is seen before the time-out constant of the circuit expires, the driver is disabled. The circuit is then reset by the next rising edge on TXD. SPLIT (pin 5) is available as a VCC/2 common-mode bus voltage bias for a split-termination network (see application information) . The SN65HVD1040 is characterized for operation from –40°C to 125°C. SN65HVD1040 TXD GND VCC RXD 1 8 2 7 3 6 4 5 STB CANH CANL SPLIT ORDERING INFORMATION (1) (1) 2 PART NUMBER PACKAGE MARKED AS ORDERING NUMBER SN65HVD1040-Q1 SOIC-8 H1040Q SN65HVD1040QDRQ1 (reel) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Submit Documentation Feedback SN65HVD1040-Q1 www.ti.com SLLS753 – FEBRUARY 2007 ABSOLUTE MAXIMUM RATINGS (1) (2) VALUE VCC IO Supply voltage –0.3 V to 7 V Voltage range at bus terminals (CANH, CANL, SPLIT) –27 V to 40 V Receiver output current 20 mA pulse (3) VI Voltage input, transient VI Voltage input range (TXD, STB) TJ Junction temperature (1) (2) (3) (CANH, CANL) –200 V to 200 V –0.5 V to 6 V –40°C to 170°C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal. Tested in accordance with ISO 7637, test pulses 1, 2, 3a, 3b, 5, 6, and 7. ELECTROSTATIC DISCHARGE PROTECTION over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS Human-Body Model (2) Electrostatic discharge (1) Charged-Device Model (3) VALUE Bus terminals (CANH, CANL, SPLIT) and GND ±8 kV All pins ±4 kV All pins ±1 kV ±200 V Machine Model (1) (2) (3) All typical values at 25°C. Tested in accordance JEDEC Standard 22, Test Method A114-A. Tested in accordance JEDEC Standard 22, Test Method C101. RECOMMENDED OPERATING CONDITIONS MIN MAX UNIT VCC Supply voltage 4.75 5.25 V VI or VIC Voltage at any bus terminal (separately or common mode) –12 12 V VIH High-level input voltage 2 5.25 V VIL Low-level input voltage 0 0.8 V VID Differential input voltage –6 6 V IOH High-level output current IOL Low-level output current TJ Junction temperature TXD, STB Driver –70 Receiver mA –2 Driver 70 Receiver 2 mA 150 °C TYP MAX UNIT 6 12 50 70 6 10 See Thermal Characteristics table SUPPLY CURRENT over recommended operating conditions (unless otherwise noted) PARAMETER ICC 5-V supply current TEST CONDITIONS Standby mode STB at VCC, VI = VCC Dominant VI = 0 V, 60-Ω load, STB at 0 V Recessive VI = VCC, No load, STB at 0 V Submit Documentation Feedback MIN µA mA 3 SN65HVD1040-Q1 www.ti.com SLLS753 – FEBRUARY 2007 DEVICE SWITCHING CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS td(LOOP1) Total loop delay, driver input to receiver output, recessive to dominant td(LOOP2) Total loop delay, driver input to receiver output, dominant to recessive Figure 9, STB at 0 V MIN MAX 90 230 90 230 UNIT ns DRIVER ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS CANH VI = 0 V, STB at 0 V, RL = 60 Ω, See Figure 1 and Figure 2 VO(D) Bus output voltage (dominant) VO(R) Bus output voltage (recessive) VI = 3 V, STB at 0 V, RL = 60 Ω, See Figure 1 and Figure 2 VO Bus output voltage (standby mode) STB at Vcc, RL = 60 Ω, See Figure 1 and Figure 2 VOD(D) VOD(R) CANL Differential output voltage (dominant) TYP (1) MAX 2.9 3.4 4.5 0.8 1.75 2 –0.1 0.1 V VI = 0 V, RL = 60 Ω, STB at 0 V, See Figure 1, Figure 2, and Figure 3 1.5 3 V VI = 0 V, RL = 45 Ω, STB at 0 V, See Figure 1, Figure 2, and Figure 3 1.4 3 V –0.012 0.012 –0.5 0.05 STB at 0 V, RL = 60 Ω, See Figure 13 VSYM Output symmetry (dominant or recessive) (VO(CANH) + VO(CANL)) VOC(ss) Steady-state common-mode output voltage ∆VOC(ss) Change in steady-state common-mode output voltage IIH High-level input current, TXD input VI at VCC –2 2 IIL Low-level input current, TXD input VI at 0 V –50 –10 IO(off) Power-off TXD output current VCC at 0 V, TXD at 5 V VCC 1.1 VCC V 2 2.3 3 V STB at 0 V, RL = 60 Ω, Figure 8 Short-circuit steady-state output current 30 –120 (1) Output capacitance µA –85 VCANH = 12 V, CANL open, See Figure 11 VCANL = –12 V, CANH open, See Figure 11 mV 1 0.4 1 mA –1 –0.6 VCANL = 12 V, CANH open, See Figure 11 CO V 0.9 VCC VCANH = –12 V, CANL open, See Figure 11 IOS(ss) V V VI = 3 V, STB at 0 V, No Load 2.5 UNIT 3 VI = 3 V, STB at 0 V, RL = 60 Ω, See Figure 1 and Figure 2 Differential output voltage (recessive) MIN 75 120 See receiver input capacitance All typical values are at 25°C with a 5-V supply. DRIVER SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER 4 TEST CONDITIONS MIN TYP MAX tPLH Propagation delay time, low-to-high level output 25 65 120 tPHL Propagation delay time, high-to-low level output 25 45 120 tr Differential output signal rise time tf Differential output signal fall time ten Enable time from standby mode to dominant See Figure 7 t(dom) Dominant time-out ↓VI, See Figure 10 STB at 0 V, See Figure 4 25 UNIT ns 45 Submit Documentation Feedback 300 450 10 µs 700 µs SN65HVD1040-Q1 www.ti.com SLLS753 – FEBRUARY 2007 RECEIVER ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS Positive-going input threshold voltage, high-speed mode VIT+ MIN TYP (1) MAX 800 900 UNIT STB at 0 V, See Table 1 VIT– Negative-going input threshold voltage, high-speed mode Vhys Hysteresis voltage (VIT+ – VIT–) VIT Input threshold voltage, standby mode STB at VCC VOH High-level output voltage IO = –2 mA, See Figure 6 VOL Low-level output voltage IO = 2 mA, See Figure 6 II(off) IO(off) 500 650 100 125 mV 500 1150 4 4.6 V 0.4 V Power-off bus input current CANH = CANL = 5 V, VCC at 0 V, TXD at 0 V 3 µA Power-off RXD leakage current VCC at 0 V, RXD at 5 V 20 µA CI Input capacitance to ground, (CANH or CANL) TXD at 3 V, VI = 0.4 sin (4E6πt) + 2.5 V CID Differential input capacitance TXD at 3 V, VI = 0.4 sin (4E6πt) RID Differential input resistance RIN Input resistance, (CANH or CANL) RI(m) Input resistance matching [1 – (RIN (CANH) / RIN (CANL))] x 100% (1) 0.2 12 pF 2 30 TXD at 3 V, STB at 0 V V(CANH) = V(CANL) 80 15 30 40 –3 0 3 kΩ % All typical values are at 25°C with a 5-V supply. RECEIVER SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS tPLH Propagation delay time, low-to-high-level output tPHL Propagation delay time, high-to-low-level output tr Output signal rise time tf Output signal fall time tBUS Dominant time required on bus for wake-up from standby STB at 0 V , See Figure 6 STB at VCC, See Figure 12 MIN TYP MAX UNIT 60 90 130 ns 45 70 130 ns 8 ns 8 ns 1.5 µs 5 STB PIN CHARACTERISTICS over recommended operating conditions (unless otherwise noted) MIN MAX IIH High-level input current PARAMETER STB at VCC TEST CONDITIONS –10 0 IIL Low-level input current STB at 0 V –10 0 UNIT µA SPLIT PIN CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VO Output voltage –500 µA < IO < 500 µA IO(stb) Leakage current, standby mode STB at 2 V, –12 V ≤ VO ≤ 12 V Submit Documentation Feedback MIN TYP MAX 0.3 VCC 0.5 VCC 0.7 VCC V 5 µA –5 UNIT 5 SN65HVD1040-Q1 www.ti.com SLLS753 – FEBRUARY 2007 THERMAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS θJA Junction-to-air thermal resistance θJB Junction-to-board thermal resistance θJC Junction-to-case thermal resistance MIN 211 High-K thermal resistance 131 mW 170 185 Tested in accordance with the Low-K or High-K thermal metric definitions of EIA/JESD51-3 for leaded surface-mount packages. FUNCTION TABLES DRIVER INPUTS OUTPUTS TXD (1) CANL (1) BUS STATE STB (1) CANH (1) L L H L DOMINANT H X Z Z RECESSIVE Open X Z Z RECESSIVE X H or Open Z Z RECESSIVE H = high level; L = low level; X = irrelevant; ? = indeterminate; Z = high impedance RECEIVER DIFFERENTIAL INPUTS VID = V(CANH) – V(CANL) (1) 6 °C/W 112 VCC = 5.5 V, Tj = 130°C, RL = 45 Ω, STB at 0 V, Input to TXD at 500 kHz, 50% duty cycle square wave, CL at RXD = 15 pF Average power dissipation (1) UNIT 79 Thermal shutdown temperature (1) MAX 53 VCC = 5 V, Tj = 27°C, RL = 60 Ω, STB at 0 V, Input to TXD at 500 kHz, 50% duty cycle square wave, CL at RXD = 15 pF PD TYP Low-K thermal resistance (1) STB OUTPUT RXD (1) BUS STATE VID ≥ 0.9 V L L DOMINANT VID ≥ 1.15 V H or Open L DOMINANT 0.5 V < VID < 0.9 V X ? ? VID ≤ 0.5 V X H RECESSIVE Open X H RECESSIVE H = high level; L = low level; X = irrelevant; ? = indeterminate; Z = high impedance Submit Documentation Feedback °C SN65HVD1040-Q1 www.ti.com SLLS753 – FEBRUARY 2007 PARAMETER MEASUREMENT INFORMATION IO(CANH) VO (CANH) TXD II VOD RL VO(CANH) + VO(CANL) 2 STB VI I I(S) VOC I O(CANL) + VI(S) _ V O(CANL) Figure 1. Driver Voltage, Current, and Test Definition Dominant 3.5 V Recessive VO(CANH) 2.5 V VO(CANL) 1.5 V Figure 2. Bus Logic-State Voltage Definitions CANH 0V TXD VOD 330 W ±1% RL + _ STB CANL –2 V £ VTEST £ 7 V 330 W ±1% Figure 3. Driver VOD Test Circuit CANH VCC VI TXD RL = 60 Ω ±1% VI (See Note A) VCC/2 0V VO tPLH CL = 100 pF (see Note B) VO STB VCC/2 tPHL 0.9 V 10% CANL tr VO(D) 90% tf 0.5 V VO(R) Figure 4. Driver Test Circuit and Voltage Waveforms Submit Documentation Feedback 7 SN65HVD1040-Q1 www.ti.com SLLS753 – FEBRUARY 2007 PARAMETER MEASUREMENT INFORMATION (continued) CANH RXD VI (CANH) IO VID V + VI (CANL) VIC = I (CANH) 2 VO CANL VI (CANL) Figure 5. Receiver Voltage and Current Definitions 3.5 V CANH 2V VI RXD VI IO 1.5 V tPLH CANL (See Note A) 2.4 V 1.5 V STB CL = 15 pF ±20% (See Note B) VO VO tPHL VOH 90% 0.7 V CC 0.3 VCC 10% tf tr A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 125 kHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω. B. CL includes instrumentation and fixture capacitance within ±20%. Figure 6. Receiver Test Circuit and Voltage Waveforms Table 1. Differential Input Voltage Threshold Test INPUT VCANH 8 OUTPUT VCANL |VID| –11.1 V –12 V 900 mV L 12 V 11.1 V 900 mV L –6 V –12 V 6V L 12 V 6V 6V L –11.5 V –12 V 500 mV H 12 V 11.5 V 500 mV H –12 V –6 V 6V H 6V 12 V 6V H Open Open X H Submit Documentation Feedback R VOL VOH VOL SN65HVD1040-Q1 www.ti.com SLLS753 – FEBRUARY 2007 DUT CANH 0V VI TXD CL 60 W ±1% 50 % 0V CANL STB VOH NOTE: C L = 100 pF includes instrumentation and fixture capacitance within ±20% RXD + VO _ VCC VI 50 % VO VOL ten NOTE: All V I input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 6 ns, Pulse Repetition Rate (PRR) = 25 kHz, 50% duty cycle 15 pF ± 20% Figure 7. ten Test Circuit and Waveform CANH TXD VI RL CANL STB VOC = VO(CANL) VO(CANH) + VO(CANL) 2 VOC(SS) VOC VO(CANH) NOTE: All VI input pulses are from 0 V to VCC and supplied by a generator having the following characteristics: tr or tf ≤ 6 ns. Pulse Repetition Rate (PRR) = 125 kHz, 50% duty cycle. Figure 8. Common-Mode Output Voltage Test and Waveforms DUT VCC CANH VI TXD STB CL 60 W ±1% TXD Input 0V + tloop1 tloop2 VOH CANL RXD Output RXD 50% 50% 50% NOTE: CL = 100 pF includes instrumentation and fixture capacitance within ±20% VOL VO _ 15 pF ±20% A. All VI input pulses are from 0 V to VCC and supplied by a generator having the following characteristics: tr or tf ≤ 6 ns. Pulse Repetition Rate (PRR) = 125 kHz, 50% duty cycle. Figure 9. t(LOOP) Test Circuit and Waveform Submit Documentation Feedback 9 SN65HVD1040-Q1 www.ti.com SLLS753 – FEBRUARY 2007 VCC VI TXD RL = 60 W ±1% VI CL (See Note B) 0V VOD VOD (See Note A) STB VOD(D) 900 mV 500 mV CANH 0V tdom A. All VI input pulses are from 0 V to VCC and supplied by a generator having the following characteristics: tr or tf ≤ 6 ns. Pulse Repetition Rate (PRR) = 500 Hz, 50% duty cycle. B. CL = 100 pF includes instrumentation and fixture capacitance within ±20%. Figure 10. Dominant Time-Out Test Circuit and Waveforms | IOS(SS) | | IOS(P) | IOS 200 µs CANH TXD 0V 0 V or V CC 12 V STB CANL VIN -12 V or 12 V Vin 0V or 0V 10 µs Vin -12 V Figure 11. Driver Short-Circuit Current Test and Waveform CANH 3.5 V VCC STB RXD VI (see Note A) CANL 1.5 V IO CL (see Note B) VI 2.65 V 0.7 µs tBUS 1.5 V VOH VO VO 400 mV VOL A. For VI bit width ≤ 0.7 µs, VO = VOH. For VI bit width ≥ 5 µs, VO = VOL. VI input pulses are supplied from a generator with the following characteristics: tr/tf < 6 ns. B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. Figure 12. tBUS Test Circuit and Waveform 10 Submit Documentation Feedback SN65HVD1040-Q1 www.ti.com SLLS753 – FEBRUARY 2007 CANH TXD RL VI VSYM = VO(CANH) + VO(CANL) STB CANL VO(CANL) A. VO(CANH) All VI input pulses are from 0 V to VCC and supplied by a generator having the following characteristics: tr/tf ≤ 6 ns, Pulse Repetition Rate (PRR) = 250 kHz, 50% duty cycle. Figure 13. Driver Output Symmetry Test Circuit Submit Documentation Feedback 11 SN65HVD1040-Q1 www.ti.com SLLS753 – FEBRUARY 2007 Equivalent Input and Output Schematic Diagrams TXD Input VCC RXD Output VCC 15 Ω 4.3 kΩ Output Input 6V 6V CANH Input CANL Input VCC VCC 10 kΩ 10 kΩ Input 20 kΩ Input 10 kΩ 40 V 40 V 10 kΩ CANH and CANL Outputs STB Input VCC VCC 4.3 kΩ Output Input 40 V 6V SPLIT Output VCC 2 kΩ Output 2 kΩ 6V 12 20 kΩ Submit Documentation Feedback SN65HVD1040-Q1 www.ti.com SLLS753 – FEBRUARY 2007 APPLICATION INFORMATION VBATTERY VCC Vreg (e.g., TLxxxx TPIC7xxx) VSUP VCC VCC 3 STB Port x 7 CANH 8 HVD1040 CAN Transceiver MCU (e.g., TMS470) 5 RXD RXD TXD TXD SPLIT 4 1 6 2 CANL GND Figure 14. Typical Application Using Split Termination for Stabilization VCC HVD1040 3 7 VSPLIT = ½V CC in normal mode, floating in other modes 5 6 CANH SPLIT CANL 2 GND Figure 15. Split Pin Stabilization Circuitry and Application Submit Documentation Feedback 13 PACKAGE OPTION ADDENDUM www.ti.com 9-Feb-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing SN65HVD1040QDRQ1 ACTIVE SOIC D Pins Package Eco Plan (2) Qty 8 2500 Green (RoHS & no Sb/Br) Lead/Ball Finish CU NIPDAU MSL Peak Temp (3) Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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