STMICROELECTRONICS STK822

STK822
N-channel 25 V - 0.00175 Ω - 38 A - PolarPAK®
STripFET™ Power MOSFET
Features
Type
VDSS
RDS(on)
max
RDS(on)*Qg
PTOT
STK822
25 V
<0.00215 Ω
58 nC*mΩ
5.2 W
■
Ultra low top and bottom junction to case
thermal resistance
■
Very low on resistance
■
100% Rg tested
■
Fully encapsulated die
■
100% matte tin finish (in compliance with the
2002/95/EC european directive)
■
PolarPAK® is a registered trademark of
VISHAY
PolarPAK®
Figure 1.
Internal schematic diagram
Application
■
Switching applications
Description
This Power MOSFET is the latest development of
STMicroelectronics unique “single feature size”
strip-based process. The resulting transistor
shows extremely high packing density for low onresistance, moreover the double sides cooling
package with ultra low junction to case thermal
resistance allows to handle higher levels of
current.
Table 1.
Bottom View
Top View
Device summary
Order code
Marking
Package
Packaging
STK822
K822
PolarPAK®
Tape & reel
February 2008
Rev 5
1/15
www.st.com
15
Contents
STK822
Contents
1
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Electrical characteristics (curves)
............................. 6
3
Test circuits
4
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2/15
.............................................. 8
STK822
1
Electrical ratings
Electrical ratings
Table 2.
Absolute maximum ratings
Symbol
VDS
Parameter
Drain-source voltage (VGS = 0)
Value
Unit
25
V
VGS (1)
Gate-source voltage
± 16
V
VGS(2)
Gate-source voltage
± 18
V
ID (4)
Drain current (continuous) at TA = 25 °C
38
A
ID (4)
Drain current (continuous) at TA = 100 °C
23.75
A
Drain current (pulsed)
152
A
Total dissipation at TA = 25 °C
5.2
W
0.0416
W/°C
IDM (3)
PTOT (4)
Derating factor
EAS (5)
Single pulse avalanche energy
500
mJ
Tj
Operating junction temperature
Storage temperature
-55 to 150
°C
Tstg
1. Continuous mode
2. Guaranteed for test time ≤ 15 ms
3. Pulse width limited by package
4. When mounted on FR-4 board of 1inch2 , 2 oz Cu and ≤ 10 sec
5. Starting Tj = 25 °C, ID = 19 A, VDD = 25 V
Table 3.
Thermal data
Symbol
Typ.
Max.
Unit
Thermal resistance junction-amb
20
24
°C/W
Rthj-c(2)
Thermal resistance junction-case (top drain)
0.8
1
°C/W
Rthj-c(3)
Thermal resistance junction-case (source)
2.2
2.7
°C/W
Rthj-amb(1)
Parameter
1. When mounted on FR-4 board of 1inch2 , 2 oz Cu and ≤10 sec
2. Steady state
3.
Measured at Source pin when the device is mounted on FR-4 board in steady state
3/15
Electrical characteristics
2
STK822
Electrical characteristics
(TCASE=25 °C unless otherwise specified)
Table 4.
Symbol
V(BR)DSS
Parameter
Drain-source breakdown
voltage
Test conditions
ID = 1 mA, VGS= 0
Zero gate voltage drain
current (VGS = 0)
IGSS
Gate body leakage current
(VDS = 0)
VGS = ±16 V
VGS(th)
Gate threshold voltage
VDS= VGS, ID = 250 µA
RDS(on)
Static drain-source on
resistance
VGS= 10 V, ID= 19 A
Symbol
Min.
Typ.
Max.
25
VDS = 20 V, Tc = 125 °C
1
1
10
µA
µA
±100
nA
2.5
V
0.00175 0.00215
0.0022
0.003
VGS= 4.5 V, ID= 19 A
Unit
V
VDS = 20 V
IDSS
Table 5.
Ω
Ω
Dynamic
Parameter
Test conditions
Min.
Typ.
Max.
Unit
Ciss
Coss
Crss
Input capacitance
Output capacitance
Reverse transfer
capacitance
VDS = 25 V, f=1 MHz, VGS=0
6060
1366
136
pF
pF
pF
Qg
Qgs
Qgd
Total gate charge
Gate-source charge
Gate-drain charge
VDD=12.5 V, ID = 38 A
VGS = 4.5 V
(see Figure 14)
33
13.2
11.3
nC
nC
nC
Qgs1
Pre Vth gate-to-source
charge
Post Vth gate-to-source
charge
VDD=12.5 V, ID = 12 A
VGS = 4.5 V
(see Figure 19)
8
nC
5.2
nC
Gate input resistance
f=1 MHz Gate DC Bias = 0
Test signal level = 20 mV
open drain
1.1
Ω
Qgs2
RG
4/15
On/off
STK822
Electrical characteristics
Table 6.
Switching times
Symbol
Parameter
td(on)
tr
td(off)
tf
Table 7.
Symbol
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Test conditions
VDD= 12.5 V, ID = 19 A,
RG = 4.7 Ω, VGS = 4.5 V
(see Figure 16)
VDD=15 V, ID= 19 A,
RG = 4.7 Ω, VGS= 4.5 V
(see Figure 16)
Parameter
Test conditions
ISDM (1)
VSD (2)
Forward on voltage
ISD= 19 A, VGS=0
Reverse recovery time
Reverse recovery charge
Reverse recovery current
ISD= 38 A, di/dt = 100 A/µs,
VDD= 20 V, Tj = 150 °C
trr
Qrr
IRRM
Typ.
Max.
Unit
30.7
60
ns
ns
43.5
13
ns
ns
Source drain diode
Source-drain current
Source-drain current
(pulsed)
ISD
Min.
(see Figure 15)
Min.
Typ.
41
45
2.2
Max.
Unit
38
152
A
A
1.2
V
ns
nC
A
1. Pulse width limited by package
2. Pulsed: pulse duration = 300µs, duty cycle 1.5%
5/15
Electrical characteristics
STK822
2.1
Electrical characteristics (curves)
Figure 2.
Safe operating area
Figure 3.
Thermal impedance
Figure 4.
Output characteristics
Figure 5.
Transfer characteristics
Figure 6.
Normalized BVDSS vs. temperature
Figure 7.
Static drain-source on resistance
HV41090
RDS(on)
(mΩ)
4
3
2
1
6/15
5
10
15
20
25
30
35
ID(A)
STK822
Figure 8.
Electrical characteristics
Gate charge vs gate-source voltage Figure 9.
Figure 10. Normalized gate threshold voltage
vs temperature
Capacitance variations
Figure 11. Normalized on resistance vs
temperature
Figure 12. Source-drain diode forward
characteristics
7/15
Test circuits
3
STK822
Test circuits
Figure 13. Switching times test circuit for
resistive load
Figure 14. Gate charge test circuit
Figure 15. Test circuit for inductive load
Figure 16. Unclamped inductive load test
switching and diode recovery times
circuit
Figure 17. Unclamped inductive waveform
8/15
Figure 18. Switching time waveform
STK822
Test circuits
Figure 19. Gate charge waveform
Id
Vds
Vgs
Vgs(th)
Qgs1 Qgs2
Qgd
9/15
Package mechanical data
4
STK822
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com
10/15
STK822
Package mechanical data
Table 8.
PolarPAK® (option “L”) mechanical data
mm
inch
Ref.
A
Min.
Typ.
Max.
Min.
Typ.
Max.
0.75
0.80
0.85
0.030
0.031
0.033
A1
0.05
0.002
b1
0.48
0.58
0.68
0.019
0.023
0.027
b2
0.41
0.51
0.61
0.016
0.020
0.024
b3
2.19
2.29
2.39
0.086
0.090
0.094
b4
0.89
1.04
1.19
0.035
0.041
0.047
b5
0.23
0.33
0.43
0.009
0.013
0.017
c
0.20
0.25
0.30
0.008
0.010
0.012
D
6
6.15
6.30
0.236
0.242
0.248
D1
5.74
5.89
6.04
0.226
0.232
0.238
E
5.01
5.16
5.31
0.197
0.203
0.209
E1
4.75
4.90
5.05
0.187
0.193
0.199
H1
0.23
H2
0.45
H3
0.31
H4
0.45
K1
4.22
K2
1.08
K3
1.37
0.054
K4
0.24
0.009
M1
4.30
4.50
4.70
M2
3.43
3.58
3.73
M3
0.22
0.009
M4
0.05
0.002
P1
0.15
0.20
0.25
T1
3.48
3.64
T2
0.56
0.76
T3
1.20
0.047
T4
3.90
0.154
T5
<
0°
0.009
0.56
0.018
0.51
0.012
0.56
0.018
4.37
4.52
0.166
0.172
0.178
1.13
1.18
0.043
0.044
0.046
0.169
0.177
0.185
0.135
0.141
0.147
0.006
0.008
0.010
4.10
0.137
0.143
0.161
0.95
0.022
0.030
0.037
0.007
0.014
10°
12°
0.41
0.18
0.36
10°
12°
0°
0.022
0.016
0.020
0.022
11/15
Package mechanical data
Figure 20. PolarPAK® (option “L”) drawings
12/15
STK822
STK822
Package mechanical data
Figure 21. Recommended PAD layout
13/15
Revision history
5
STK822
Revision history
Table 9.
14/15
Document revision history
Date
Revision
Changes
14-May-2007
1
First version
22-Jun-2007
2
VDSS value changed on all document
03-Sep-2007
3
Updated mechanical data
13-Dec-2007
4
Document status promoted from preliminary data to datasheet.
14-Feb-2008
5
Updated Table 8, Figure 20 and Figure 21
STK822
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