TI TPS71025P

TPS71025
LOW-DROPOUT VOLTAGE REGULATOR
SLVS162A – MAY 1997 – REVISED MAY 1998
D
D
D
D
D
D
D
D
D OR P PACKAGE
(TOP VIEW)
2.5-V Fixed-Output Regulator
Very Low-Dropout (LDO) Voltage . . . 57 mV
Typical at IO = 100 mA
Very Low Quiescent Current, Independent
of Load . . . 292 µA Typ
Extremely Low Sleep-State Current,
0.5 µA Max
2% Tolerance Over Specified Conditions
Output Current Range . . . 0 mA to 500 mA
Available in Space Saving 8-Pin SOIC and
20-Pin TSSOP Packages
0°C to 125°C Operating Junction
Temperature Range
GND
EN
IN
IN
1
8
2
7
3
6
4
5
NC
SENSE
OUT
OUT
PW PACKAGE
(TOP VIEW)
GND
GND
GND
NC
NC
EN
NC
IN
IN
IN
description
The TPS71025 low-dropout regulator offers an
order of magnitude reduction in both dropout
voltage and quiescent current over conventional
LDO performance. The improvement results from
replacing the typical pnp pass transistor with a
PMOS device.
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
NC
NC
NC
NC
NC
SENSE
OUT
OUT
NC
NC
NC – No internal connection
Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (maximum of 95 mV
at an output current of 100 mA) and is directly proportional to the output current (see Figure 1). Additionally,
since the PMOS pass element is a voltage-driven device, the quiescent current is very low and remains
independent of output loading (typically 292 µA over the full range of output current, 0 mA to 500 mA). These
two key specifications yield a significant improvement in operating life for battery-powered systems. The
TPS71025 also features a sleep mode; applying a TTL high signal to EN (enable) shuts down the regulator,
reducing the quiescent current to 0.5 µA maximum at TJ = 25°C.
AVAILABLE OPTIONS
TJ
0°C to 125°C
OUTPUT VOLTAGE
(V)
PACKAGED DEVICES
MIN
TYP
MAX
SMALL OUTLINE
(D)
2.45
2.5
2.55
TPS71025D
PLASTIC DIP
(P)
TSSOP
(PW)
TPS71025P
TPS71025PWLE
CHIP FORM
(Y)
TPS71025Y
The D package is availabe taped and reeled. Add R suffix to device type (e.g., TPS71025DR). The PW package is only available left-end taped
and reeled and is indicated by the LE suffix on the device type.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
TPS71025
LOW-DROPOUT VOLTAGE REGULATOR
SLVS162A – MAY 1997 – REVISED MAY 1998
0.5
TA = 25°C
Dropout Voltage – V
0.4
0.3
0.2
0.1
0
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
IO – Output Current – A
Figure 1. Dropout Voltage Versus Output Current
functional block diagram
IN
†
†
EN
_
+
OUT
Vref = 1.182 V
SENSE
260 kΩ
233 kΩ
GND
† Switch positions are shown with EN low (active).
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS71025
LOW-DROPOUT VOLTAGE REGULATOR
SLVS162A – MAY 1997 – REVISED MAY 1998
Terminal Functions
TERMINAL
NAME
DESCRIPTION
NO.
D or P
PW
EN
2
6
GND
1
1–3
Ground
IN
3, 4
8–10
Input supply voltage
OUT
5, 6
13, 14
Output voltage
7
15
SENSE
Enable input. Logic low enables output
Output voltage sense input
TPS71025Y chip information
These chips, when properly assembled, display characteristics similar to those of the TPS71025. Thermal
compression or ultrasonic bonding may be used on the doped aluminum bonding pads. The chips may be
mounted with conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
(3)
(5)
(4)
(5)
IN
SENSE
TPS71025
EN
(2)
(4)
OUT
(1)
GND
CHIP THICKNESS: 15 MILS TYPICAL
80
BONDING PADS: 4 × 4 MILS MINIMUM
TJmax = 150°C
TOLERANCES ARE ± 10%.
ALL DIMENSIONS ARE IN MILS.
(3)
(1) (2)
92
POST OFFICE BOX 655303
NOTE A: For most applications, OUT and SENSE should
be tied together as close as possible to the device;
for other implementations, refer to SENSE-pin
connection discussion in the Application
Information section of this data sheet.
• DALLAS, TEXAS 75265
3
TPS71025
LOW-DROPOUT VOLTAGE REGULATOR
SLVS162A – MAY 1997 – REVISED MAY 1998
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Input voltage range, VI, EN (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 11 V
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 A
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Tables 1 and 2
Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0°C to 150°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND
DISSIPATION RATING TABLE 1 – FREE-AIR TEMPERATURE‡
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 125°C
POWER RATING
D
725 mW
5.8 mW/°C
464 mW
145 mW
P
1175 mW
9.4 mW/°C
752 mW
235 mW
PW
700 mW
5.6 mW/°C
448 mW
140 mW
DISSIPATION RATING TABLE 2 – CASE TEMPERATURE‡
PACKAGE
TC ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TC = 25°C
TC = 70°C
POWER RATING
TC = 125°C
POWER RATING
D
2188 mW
17.5 mW/°C
1400 mW
438 mW
P
2738 mW
21.9 mW/°C
1752 mW
548 mW
PW
4025 mW
32.2 mW/°C
2576 mW
805 mW
‡ Dissipation rating tables and figures are provided for maintenance of junction temperature at or below
absolute maximum temperature of 150°C. For guidelines on maintaining junction temperature within
recommended operating range, see the Thermal Information section.
recommended operating conditions
Input voltage, VI
MIN
MAX
2.97
10
UNIT
V
High-level input voltage at EN, VIH
2
Low-level input voltage at EN, VIL
0
0.5
V
Output current range, IO
0
500
mA
Operating virtual junction temperature range, TJ
0
125
°C
4
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V
TPS71025
LOW-DROPOUT VOLTAGE REGULATOR
SLVS162A – MAY 1997 – REVISED MAY 1998
electrical characteristics over recommended operating junction temperature range, VI(IN) = 3.5 V,
IO = 10 mA, EN = 0 V, Co = 4.7 µF/CSR† = 1 Ω, SENSE shorted to OUT (unless otherwise noted)
TEST CONDITIONS‡
PARAMETER
Output voltage
3 5 V ≤ VI ≤ 10 V
3.5
IO = 10 mA
mA,
Dropout voltage
45 V
VI = 2
2.45
IO = 100 mA
mA,
VI = 2
2.45
45 V
IO = 500 mA
mA,
VI = 2
2.45
45 V
Output regulation
MIN
0°C to 125°C
2.45
25°C
5.7
0°C to 125°C
57
0°C to 125°C
25°C
330
0°C to 125°C
IO = 50 µ
µA to 500 mA,
3.5 V ≤ VI ≤ 10 V
0°C to 125°C
f = 120 Hz
Hz,
Output noise-spectral density
f = 120 Hz
Output noise voltage
10 Hz ≤ f ≤ 100 kHz
kHz,
CSR = 1 Ω
IO = 500 mA
29
18
38
24
25°C
43
0°C to 125°C
40
25°C
39
0°C to 125°C
36
274
25°C
228
Co = 100 µF
25°C
159
25°C
292
Output current limit
VO = 0
0,
VI = 10 V
Pass-element leakage
g current in standbyy
mode
EN = VI,
2 7 V ≤ VI ≤ 10 V
2.7
0°C to 125°C
Output voltage temperature coefficient
18
0°C to 125°C
1.07
0°C to 125°C
390
475
2
2
25°C
0.223
0°C to 125°C
0.5
1
0°C to 125°C
61
Thermal shutdown junction temperature
75
25°C
6 V ≤ VI ≤ 10 V
0°C to 125°C
2 7 V ≤ VI ≤ 10 V
2.7
Hysteresis voltage, EN
2
0 V ≤ VI ≤ 10 V
25°C
0.5
0°C to 125°C
0.5
50
25°C
– 0.5
0.5
– 0.5
0.5
0°C to 125°C
A
µA
ppm/°C
2
V
mV
0°C to 125°C
25°C
Input voltage,
g , minimum for active pass
element
nA
V
2.7
0°C to 125°C
µA
°C
165
2.5 V ≤ VI ≤ 6 V
mV
µVrms
1900
25°C
mV
µV/√Hz
540
25°C
mV
dB
51
25°C
2 7 V ≤ VI ≤ 10 V
2.7
Ω
53
Co = 10 µF
EN = VI,
60
120
Co = 4.7 µF
Supply current (standby mode)
Input current,
current EN
23
2
EN ≤ 0.5 V,,
0 mA ≤ IO ≤ 500 mA
Logic low input voltage (active mode)
mode), EN
7
12.7
25°C
Quiescent current (active mode)
0.9
75
25°C
Ripple rejection
mV
450
1
25°C
IO = 50 µA
95
500
0.66
25°C
IO = 5 mA to 500 mA,
3.5 V ≤ VI ≤ 10 V
V
7.5
105
0°C to 125°C
0°C to 125°C
UNIT
10
25°C
VI = 3.5 V to 10 V,
50 µA ≤ IO ≤ 500 mA
MAX
2.55
0°C to 125°C
f = 120 Hz
Hz,
Logic high input voltage (standby mode)
mode), EN
TYP
2.5
25°C
Pass element series resistance
Pass-element
Input regulation
TJ
25°C
2.5
2.5
µA
V
† CSR (compensation series resistance) refers to the total series resistance, including the equivalent series resistance (ESR) of the capacitor, any
series resistance added externally, and PWB trace resistance to Co.
‡ Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
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5
TPS71025
LOW-DROPOUT VOLTAGE REGULATOR
SLVS162A – MAY 1997 – REVISED MAY 1998
electrical characteristics at TJ = 25°C, VI(IN) = 3.5 V, IO = 10 mA, EN = 0 V, Co = 4.7 µF/CSR† = 1 Ω,
SENSE shorted to OUT (unless otherwise noted)
TEST CONDITIONS‡
PARAMETER
Output voltage
3.5 V ≤ VI ≤ 10 V
Dropout voltage
IO = 10 mA,
IO = 100 mA,
VI = 2.45 V
VI = 2.45 V
IO = 500 mA,
VI = 2.45 V
TPS71025Y
MIN
Output regulation
Ripple rejection
Output noise voltage
Quiescent current (active mode)
EN = 0 V,
0 mA ≤ IO ≤ 500 mA
Supply current (standby mode)
EN = VI,
Output current limit
VO = 0,
EN = VI,
mV
18
mV
24
mV
dB
51
µV/√Hz
2
Co = 4.7 µF
274
Co = 10 µF
228
Co = 100 µF
159
µVrms
292
µA
2.7 V ≤ VI ≤ 10 V
18
nA
VI = 10 V
2.7 V ≤ VI ≤ 10 V
1.07
A
0.223
µA
Thermal shutdown junction temperature
2.5 V ≤ VI ≤ 6 V
2
6 V ≤ VI ≤ 10 V
2.7
61
ppm/°C
165
°C
V
2.7 V ≤ VI ≤ 10 V
Hysteresis voltage, EN
Input current, EN
Ω
7
53
Output voltage temperature coefficient
Logic low input voltage (active mode), EN
mV
330
IO = 50 µA to 500 mA
f = 120 Hz,
IO = 50 µA
f = 120 Hz,
IO = 500 mA
10 Hz
H ≤ f ≤ 100 kHz,
kH
CSR = 1 Ω
Logic high inp
inputt voltage
oltage (standb
(standby mode)
mode), EN
V
57
VI = 3.5 V to 10 V
IO = 5 mA to 500 mA
f = 120 Hz
UNIT
5.7
0.66
Output noise-spectral density
Pass-element leakage current in standby mode
MAX
2.5
Pass-element series resistance
Input regulation
TYP
0 V ≤ VI ≤ 10 V
0.5
V
50
mV
0
µA
Input voltage, minimum for active pass element
2
V
† CSR (compensation series resistance) refers to the total series resistance, including the equivalent series resistance (ESR) of the capacitor ,
any series resistance added externally, and PWB trace resistance to Co.
‡ Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
6
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TPS71025
LOW-DROPOUT VOLTAGE REGULATOR
SLVS162A – MAY 1997 – REVISED MAY 1998
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
DROPOUT VOLTAGE
vs
FREE-AIR TEMPERATURE
2.55
0.4
VI = 3.5 V
2.54
VI = 2.45 V
0.35
IO = 500 mA
0.3
2.52
Drpoout Voltage – V
VO – Output Voltage – V
2.53
2.51
2.5
IO = 10 mA
2.49
2.48
IO = 500 mA
2.47
0.25
0.2
0.15
0.1
IO = 100 mA
2.46
0.05
2.45
0
0
100
25
50
75
TA – Free-Air Temperature – °C
125
IO = 10 mA
100
25
50
75
TA – Free-Air Temperature – °C
0
Figure 2
Figure 3
OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
OUTPUT VOLTAGE
vs
INPUT VOLTAGE
2.55
2.55
IO = 5 mA
2.54
2.54
2.53
TA = 25°C
IO = 500 mA
2.53
VO – Output Voltage – V
VO – Output Voltage – V
125
2.52
2.51
2.5
2.49
2.48
2.52
2.51
2.5
2.49
2.48
2.47
2.47
2.46
2.46
2.45
0
100
25
50
75
TA – Free-Air Temperature – °C
125
2.45
3.5 4 4.5 5 5.5 6 6.5 7 7.5 8 8.5 9 9.5 10
VI – Input Voltage – V
Figure 4
Figure 5
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• DALLAS, TEXAS 75265
7
TPS71025
LOW-DROPOUT VOLTAGE REGULATOR
SLVS162A – MAY 1997 – REVISED MAY 1998
TYPICAL CHARACTERISTICS
TYPICAL REGIONS OF STABILITY
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
COMPENSATION SERIES RESISTANCE
vs
OUTPUT CURRENT
2.55
CSR – Compensation Series Resistance – Ω
100
2.54
VO – Output Voltage – V
2.53
2.52
2.51
2.5
VI = 10 V
2.49
VI = 3.5 V
2.48
2.47
2.46
2.45
0
100
400
200
300
IO – Output Current – mA
VI = 3.5 V
No Input Capacitance
Co = 4.7 µF
No Added Ceramic Capacitance
TA = 25°C
Region of Instability
10
1
Region of Instability
0.1
500
0
50 100 150 200 250 300 350 400 450 500
IO – Output Current – mA
Figure 7
Figure 6
TYPICAL REGIONS OF STABILITY
TYPICAL REGIONS OF STABILITY
COMPENSATION SERIES RESISTANCE
vs
OUTPUT CURRENT
COMPENSATION SERIES RESISTANCE
vs
ADDED CERAMIC CAPACITANCE
100
VI = 3.5 V
No Input Capacitance
Co = 4.7 µF + 0.5 µF of
Ceramic Capacitance
TA = 25°C
10
Region of Instability
1
Region of Instability
CSR – Compensation Series Resistance – Ω
CSR – Compensation Series Resistance – Ω
100
VI = 3.5 V
No Input Capacitance
IO= 100 mA
Co = 4.7 µF
TA = 25°C
10
Region of Instability
1
Region of Instability
0.1
0.1
0
50 100 150 200 250 300 350 400 450 500
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Added Ceramic Capacitance – µF
IO – Output Current – mA
Figure 9
Figure 8
8
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• DALLAS, TEXAS 75265
1
TPS71025
LOW-DROPOUT VOLTAGE REGULATOR
SLVS162A – MAY 1997 – REVISED MAY 1998
TYPICAL CHARACTERISTICS
TYPICAL REGIONS OF STABILITY
TYPICAL REGIONS OF STABILITY †
COMPENSATION SERIES RESISTANCE
vs
ADDED CERAMIC CAPACITANCE
COMPENSATION SERIES RESISTANCE
vs
OUTPUT CURRENT
100
VI = 3.5 V
No Input Capacitance
IO= 500 mA
Co = 4.7 µF
TA = 25°C
10
CSR – Compensation Series Resistance – Ω
CSR – Compensation Series Resistance – Ω
100
Region of Instability
1
Region of Instability
0.1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Region of Instability
10
1
0.1
1
0
50 100 150 200 250 300 350 400 450 500
Added Ceramic Capacitance – µF
IO – Output Current – mA
Figure 10
Figure 11
TYPICAL REGIONS OF STABILITY†
TYPICAL REGIONS OF STABILITY †
COMPENSATION SERIES RESISTANCE
vs
OUTPUT CURRENT
COMPENSATION SERIES RESISTANCE
vs
ADDED CERAMIC CAPACITANCE
100
VI = 3.5 V
No Input Capacitance
Co = 10 µF + 0.5 µF of
Added Ceramic Capacitance
TA = 25°C
CSR – Compensation Series Resistance – Ω
CSR – Compensation Series Resistance – Ω
100
VI = 3.5 V
No Input Capacitance
Co = 10 µF
No Ceramic Capacitance
TA = 25°C
10
Region of Instability
1
0.1
VI = 3.5 V
No Input Capacitance
Co = 10 µF
IO = 100 mA
TA = 25°C
10
Region of Instability
1
0.1
0
50 100 150 200 250 300 350 400 450 500
IO – Output Current – mA
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
Added Ceramic Capacitance – µF
Figure 12
Figure 13
† CSR values below 0.1 Ω are not recommended.
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9
TPS71025
LOW-DROPOUT VOLTAGE REGULATOR
SLVS162A – MAY 1997 – REVISED MAY 1998
TYPICAL CHARACTERISTICS
TYPICAL REGIONS OF STABILITY †
COMPENSATION SERIES RESISTANCE
vs
ADDED CERAMIC CAPACITANCE
CSR – Compensation Series Resistance – Ω
100
VI = 3.5 V
No Input Capacitance
Co = 10 µF
IO = 500 mA
TA = 25°C
10
Region of Instability
1
0.1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
Added Ceramic Capacitance – µF
† CSR values below 0.1 Ω are not recommended.
Figure 14
VI
To Load
IN
OUT
SENSE
EN
+
Co
GND
Ccer
(see Note A)
RL
CSR
NOTE A: Ceramic capacitor
Figure 15. Test Circuit for Typical Regions of Stability (Figures 7 through 14)
10
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TPS71025
LOW-DROPOUT VOLTAGE REGULATOR
SLVS162A – MAY 1997 – REVISED MAY 1998
THERMAL INFORMATION
In response to system-miniaturization trends, integrated circuits are being offered in low-profile and fine-pitch
surface-mount packages. Implementation of many of today’s high-performance devices in these packages
requires special attention to power dissipation. Many system-dependent issues such as thermal coupling,
airflow, added heat sinks and convection surfaces, and the presence of other heat-generating components
affect the power-dissipation limits of a given component.
Three basic approaches for enhancing thermal performance are illustrated in this discussion:
D Improving the power-dissipation capability of the PWB design
D Improving the thermal coupling of the component to the PWB
D Introducing airflow in the system
Figure 16 is an example of a thermally enhanced PWB layout for the 20-lead TSSOP package. This layout
involves adding copper on the PWB to conduct heat away from the device. The RθJA for this component / board
system is illustrated in Figure 17. The family of curves illustrates the effect of increasing the size of the
copper-heat-sink surface area. The PWB is a standard FR4 board (L × W × H = 3.2 inch × 3.2 inch × 0.062 inch);
the board traces and heat sink area are 1-oz (per square foot) copper.
Copper Heat Sink
1 oz Copper
Figure 16. Thermally Enhanced PWB Layout (Not to Scale) for the 20-Pin TSSOP
Figure 18 shows the thermal resistance for the same system with the addition of a thermally conductive
compound between the body of the TSSOP package and the PWB copper routed directly beneath the device.
The thermal conductivity for the compound used in this analysis is 0.815 W/m × °C.
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11
TPS71025
LOW-DROPOUT VOLTAGE REGULATOR
SLVS162A – MAY 1997 – REVISED MAY 1998
THERMAL RESISTANCE, JUNCTION-TO-AMBIENT
vs
AIR FLOW
190
THERMAL RESISTANCE, JUNCTION-TO-AMBIENT
vs
AIR FLOW
RθJA – Thermal Resistance, Junction-to-Ambient – °C/W
RθJA – Thermal Resistance, Junction-to-Ambient – °C/W
THERMAL INFORMATION
Component /Board System
20-Lead TSSOP
0 cm2
170
1 cm2
150
2 cm2
130
110
90
4 cm2
8 cm2
70
50
0
50
100
150
200
Air Flow – ft /min
250
300
190
Component /Board System
20-Lead TSSOP
Includes Thermally Conductive
Compound Between Body and Board
170
150
0 cm2
130
8 cm2
110
4 cm2
2 cm2
90
1 cm2
70
50
0
Figure 17
50
100
150
200
Air Flow – ft /min
250
300
Figure 18
Using these figures to determine the system RθJA allows the maximum power-dissipation PD(max) limit to be
calculated with the equation:
+ RJ(max)
D(max)
T
P
* TA
qJA(system)
Where
TJ(max) is the maximum allowable junction temperature (i.e., 150°C absolute maximum or
125°C maximum recommended operating temperature for specified operation).
This limit should then be applied to the internal power dissipated by the TPS71025 regulator. The equation for
calculating total internal power dissipation of the device is:
P
D(total)
ǒ
Ǔ
ǒ
Ǔ
+ VI * VO
I
O
)
ǒ
V
I
I
Ǔ
Q
Because the quiescent current is very low, the second term is negligible, further simplifying the equation to:
P
12
D(total)
+ VI * VO
I
O
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TPS71025
LOW-DROPOUT VOLTAGE REGULATOR
SLVS162A – MAY 1997 – REVISED MAY 1998
THERMAL INFORMATION
For a 20-lead TSSOP / FR4 board system with thermally conductive compound between the board and the
device body, where TA = 55°C, airflow = 100 ft /min, and copper heat sink area = 1 cm2, the maximum
power-dissipation limit can be calculated. As indicated in Figure 18, the system RθJA is 94°C/W; therefore, the
maximum power-dissipation limit is:
+ RJ(max)
D(max)
T
P
* TA
qJA(system)
+ 12594° C° C*ń W55°C + 745 mW
If the system implements a TPS71025 regulator where VI = 3.3 V and IO = 385 mA, the internal power dissipation
is:
P
D(total)
ǒ
Ǔ
+ VI * VO
I
O
+ (3.3 * 2.5)
0.385
+ 308 mW
Comparing PD(total) with PD(max) reveals that the power dissipation in this example does not exceed the
maximum limit. When it does, one of two corrective actions can be taken. The power-dissipation limit can be
raised by increasing the airflow or the heat-sink area. Alternatively, the internal power dissipation of the regulator
can be lowered by reducing the input voltage or the load current. In either case, the above calculations should
be repeated with the new system parameters.
POST OFFICE BOX 655303
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13
TPS71025
LOW-DROPOUT VOLTAGE REGULATOR
SLVS162A – MAY 1997 – REVISED MAY 1998
APPLICATION INFORMATION
TPS71025†
VI
8
9
10
C1
0.1 µF
50 V
6
IN
SENSE
IN
OUT
IN
EN
OUT
15
14
VO
13
+ C
o
10 µF
GND
1
2
3
CSR
† Capacitor selection is nontrivial. See external capacitor requirements section.
Figure 19. Typical Application Circuit
The TPS71025 low-dropout (LDO) regulator overcomes many of the shortcomings of earlier-generation LDOs,
while adding features such as a power-saving shutdown mode.
device operation
The TPS71025, unlike many other LDOs, features very low quiescent current that remains virtually constant
even with varying loads. Conventional LDO regulators use a pnp-pass element, the base current of which is
directly proportional to the load current through the regulator (IB = IC/β). Examination of the data sheets reveals
that those devices are typically specified under near no-load conditions; actual operating currents are much
higher as evidenced by typical quiescent current versus load current curves. The TPS71025 uses a PMOS
transistor to pass current; because the gate of the PMOS element is voltage driven, operating currents are low
and stable over the full load range. The TPS71025 specifications reflect actual performance under load.
Another pitfall associated with the pnp-pass element is its tendency to saturate when the device goes into
dropout. The resulting drop in β forces an increase in IB to maintain the load. During power up, this translates
to large start-up currents. Systems with limited supply current may fail to start up. In battery-powered systems,
it means rapid battery discharge when the voltage decays below the minimum required for regulation. The
TPS71025 quiescent current remains low even when the regulator drops out, eliminating both problems.
The TPS71025 also features a shutdown mode that places the output in the high-impedance state (essentially
equal to the feedback-divider resistance) and reduces quiescent current to under 2 µA. If the shutdown feature
is not used, EN should be tied to ground. Response to an enable transition is quick; regulated output voltage
is reestablished in typically 120 µs.
minimum load requirements
The TPS71025 family is stable even at zero load; no minimum load is required for operation.
SENSE-pin connection
The SENSE pin must be connected to the regulator output for proper functioning of the regulator. Normally, this
connection should be as short as possible; however, the connection can be made near a critical circuit (remote
sense) to improve performance at that point. Internally, SENSE connects to a high-impedance wide-bandwidth
amplifier through a resistor-divider network, and noise pickup feeds through to the regulator output. Routing the
SENSE connection to minimize/avoid noise pickup is essential. Adding an RC network between SENSE and
OUT to filter noise is not recommended because it can cause the regulator to oscillate.
14
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS71025
LOW-DROPOUT VOLTAGE REGULATOR
SLVS162A – MAY 1997 – REVISED MAY 1998
APPLICATION INFORMATION
external capacitor requirements
An input capacitor is not required; however, a ceramic bypass capacitor (0.047 pF to 0.1 µF) improves load
transient response and noise rejection if the TPS71025 is located more than a few inches from the power supply.
A higher-capacitance electrolytic capacitor may be necessary if large (hundreds of milliamps) load transients
with fast rise times are anticipated.
As with most LDO regulators, the TPS71025 requires an output capacitor for stability. A low-ESR 10-µF
solid-tantalum capacitor connected from the regulator output to ground is sufficient to ensure stability over the
full load range (see Figure 11). Adding high-frequency ceramic or film capacitors (such as power-supply bypass
capacitors for digital or analog ICs) can cause the regulator to become unstable unless the ESR of the tantalum
capacitor is less than 1.2 Ω over temperature. Capacitors with published ESR specifications such as the
AVX TPSD106K035R0300 and the Sprague 593D106X0035D2W work well because the maximum ESR at
25°C is 300 mΩ (typically, the ESR in solid-tantalum capacitors increases by a factor of 2 or less when the
temperature drops from 25°C to – 40°C). Where component height and/or mounting area is a problem,
physically smaller, 10-µF devices can be screened for ESR. Figure 7 through Figure 14 show the stable regions
of operation using different values of output capacitance with various values of ceramic load capacitance.
In applications with little or no high-frequency bypass capacitance (< 0.2 µF), the output capacitance can be
reduced to 4.7 µF, provided ESR is maintained between 0.7 and 2.5 Ω. Because minimum capacitor ESR is
seldom if ever specified, it may be necessary to add a 0.5-Ω to 1-Ω resistor in series with the capacitor and limit
ESR to 1.5 Ω maximum. As shown in the ESR graphs (Figure 7 through Figure 14), minimum ESR is not a
problem when using 10-µF or larger output capacitors.
Below is a partial listing of surface-mount capacitors usable with the TPS71025. This information (along with
the ESR graphs, Figure 7 through Figure 14) is included to assist in selection of suitable capacitance for the
application. When necessary to achieve low height requirements along with high output current and/or high
ceramic load capacitance, several higher ESR capacitors can be used in parallel to meet the guidelines above.
POST OFFICE BOX 655303
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15
TPS71025
LOW-DROPOUT VOLTAGE REGULATOR
SLVS162A – MAY 1997 – REVISED MAY 1998
APPLICATION INFORMATION
external capacitor requirements (continued)
All load and temperature conditions with up to 1 µF of added ceramic load capacitance:
PART NO.
MFR.
VALUE
MAX ESR†
SIZE (H × L × W)†
T421C226M010AS
Kemet
22 µF, 10 V
0.5
2.8 × 6 × 3.2
593D156X0025D2W
Sprague 15 µF, 25 V
0.3
2.8 × 7.3 × 4.3
593D106X0035D2W
Sprague 10 µF, 35 V
0.3
2.8 × 7.3 × 4.3
10 µF, 35 V
0.3
2.8 × 7.3 × 4.3
TPSD106M035R0300 AVX
Load < 200 mA, ceramic load capacitance < 0.2 µF, full temperature range:
PART NO.
MFR.
VALUE
MAX ESR†
SIZE (H × L × W)†
592D156X0020R2T
Sprague 15 µF, 20 V
1.1
1.2 × 7.2 × 6
595D156X0025C2T
Sprague 15 µF, 25 V
1
2.5 × 7.1 × 3.2
595D106X0025C2T
Sprague 10 µF, 25 V
1.2
2.5 × 7.1 × 3.2
293D226X0016D2W
Sprague 22 µF, 16 V
1.1
2.8 × 7.3 × 4.3
Load < 100 mA, ceramic load capacitance < 0.2 µF, full temperature range:
PART NO.
MFR.
VALUE
MAX ESR†
SIZE (H × L × W)†
195D106X06R3V2T
Sprague 10 µF, 6.3 V
1.5
1.3 × 3.5 × 2.7
195D106X0016X2T
Sprague 10 µF, 16 V
1.5
1.3 × 7 × 2.7
595D156X0016B2T
Sprague 15 µF, 16 V
1.8
1.6 × 3.8 × 2.6
695D226X0015F2T
Sprague 22 µF, 15 V
1.4
1.8 × 6.5 × 3.4
695D156X0020F2T
Sprague 15 µF, 20 V
1.5
1.8 × 6.5 × 3.4
695D106X0035G2T
Sprague 10 µF, 35 V
1.3
2.5 × 7.6 × 2.5
† Size is in mm. ESR is maximum resistance at 100 kHz and TA = 25°C. Listings are sorted by height.
16
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS71025
LOW-DROPOUT VOLTAGE REGULATOR
SLVS162A – MAY 1997 – REVISED MAY 1998
MECHANICAL DATA
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
PINS **
0.050 (1,27)
8
14
16
A MAX
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
A MIN
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
DIM
0.020 (0,51)
0.014 (0,35)
14
0.010 (0,25) M
8
0.244 (6,20)
0.228 (5,80)
0.008 (0,20) NOM
0.157 (4,00)
0.150 (3,81)
1
Gage Plane
7
A
0.010 (0,25)
0°– 8°
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.069 (1,75) MAX
0.010 (0,25)
0.004 (0,10)
0.004 (0,10)
4040047 / D 10/96
NOTES: A.
B.
C.
D.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
Falls within JEDEC MS-012
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
17
TPS71025
LOW-DROPOUT VOLTAGE REGULATOR
SLVS162A – MAY 1997 – REVISED MAY 1998
MECHANICAL DATA
P (R-PDIP-T8)
PLASTIC DUAL-IN-LINE PACKAGE
0.400 (10,60)
0.355 (9,02)
8
5
0.260 (6,60)
0.240 (6,10)
1
4
0.070 (1,78) MAX
0.310 (7,87)
0.290 (7,37)
0.020 (0,51) MIN
0.200 (5,08) MAX
Seating Plane
0.125 (3,18) MIN
0.100 (2,54)
0.021 (0,53)
0.015 (0,38)
0°– 15°
0.010 (0,25) M
0.010 (0,25) NOM
4040082 / B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
18
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS71025
LOW-DROPOUT VOLTAGE REGULATOR
SLVS162A – MAY 1997 – REVISED MAY 1998
MECHANICAL DATA
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
0,75
0,50
A
Seating Plane
1,20 MAX
0,10
0,05 MIN
PINS **
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064 / E 08/96
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
19
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