IG N TSA1002 10-BIT, 50MSPS, 50mW A/D CONVERTER P P E Temperature Range 0 C to +70 C TQFP48 Tray SA1002C 0 C to +70 C TQFP48 Tape & Reel SA1002C TSA1002IF -40 C to +85 C TQFP48 Tray SA1002I TSA1002IFT -40 C to +85 C TQFP48 Tape & Reel SA1002I EVAL1002/AA Evaluation board PIN CONNECTIONS (top view) R O F T 38 37 36 NC IPOL 1 2 VREFM 3 34 NC AGND 4 33 D0 (LSB) VIN 5 32 D1 35 NC 31 D2 AGND 6 VINB 7 AGND 8 29 D4 INCM 9 28 D5 AGND 10 27 D6 AVCC 11 26 D7 AVCC 12 30 D3 TSA1002 25 D8 16 17 18 19 20 21 22 23 24 NC GNDB GNDB VCCB OR D9 (MSB) 14 15 DGND 13 DGND O 39 CLK N 40 NC 41 DR P e let VCCB 42 GNDB NC ro VCCB 44 43 NC OEB s b O DFSB t e l o 45 DGND r P e 47 46 c u d ) s t( VREFP DVCC u d o 48 so b O - AVCC index corner DVCC ) s ( ct Marking TSA1002CFT AVCC The TSA1002 is a 10-bit, 50Msps sampling frequency Analog to Digital converter using a CMOS technology combining high performances and very low power consumption. The TSA1002 is based on a pipeline structure and digital error correction to provide excellent static linearity and guarantee 9.6 effective bits at Fs=40Msps, and Fin=24MHz. A voltage reference is integrated in the circuit to simplify the design and minimize external components. It is nevertheless possible to use the circuit with an external reference. Especially designed for high speed, low power applications, the TSA1002 only dissipates 50mW at 50Msps. A tri-state capability, available on the output buffers, enables to address several slave ADCs by a unique master. The output data can be coded into two different formats. A Data Ready signal is raised as the data is valid on the output and can be used for synchronization purposes. The TSA1002 is available in commercial (0 to +70 C) and extended (-40 to +85 C) temperature range, in a small 48 pins TQFP package. Conditioning TSA1002CF AGND DESCRIPTION Package D Part Number W P P ORDER CODE E P P P P 10-bit A/D converter in deep submicron CMOS technology Single supply voltage: 2.5V Input range: 2Vpp differential 50Msps sampling frequency Ultra low power consumption: 50mW @ 50Msps ENOB=9.6 @ 40Msps, Fin=24MHz SFDR typically up to 72dB @ 50Msps, Fin=5MHz Built-in reference voltage with external bias capability Pinout compatibility with TSA0801, TSA1001 and TSA1201 N P S NOT FOR NEW DESIGN PACKAGE 7 x 7 mm TQFP48 APPLICATIONS P P P P P Medical imaging and ultrasound Portable instrumentation Cable Modem Receivers High resolution fax and scanners High speed DSP interface April 2004 1/20 TSA1002 ABSOLUTE MAXIMUM RATINGS IDout Tstg ESD 1) V 0 to 3.3 1) Digital buffer Supply voltage Digital output current Storage temperature Electrical Static Discharge - HBM V 0 to 3.3 V -100 to 100 +150 mA C 2 KV 1.5 KV D - CDM-JEDEC Standard Latch-up 0 to 3.3 IG VCCB Analog Supply voltage 1) Digital Supply voltage Unit S DVCC Values E AVCC Parameter N Symbol Class2) A 1) All voltages values, except differential voltage, are with respect to network ground terminal. The magnitude of input and output voltages must never exceed -0.3V or VCC+0V W 2) Corporate ST Microelectronics procedure number 0018695 E OPERATING CONDITIONS Parameter N Symbol Min Typ 2.25 2.5 AVCC Analog Supply voltage DVCC Digital Supply voltage VCCB Digital buffer Supply voltage 2.25 VREFP Forced top reference voltage 1) VREFM Forced bottom reference voltage1) R O so T 1)Condition VRefP-VRefM>0.3V O BLOCK DIAGRAM N u d o r P e VIN INCM t e l o bs O ) s ( ct +2.5V stage 1 VINB V 2.7 V 2.5 2.7 V 0.5 1 1.8 V 0 0 0.5 V 0.2 0.5 1.1 V 2.25 Forced input common mode voltage stage 2 Pr od 2.5 b O - VREFP GNDA stage n Reference circuit IPOL VREFM DFSB Sequencer-phase shifting OEB CLK Timing Digital data correction DR DO Buffers TO D9 OR GND 2/20 uc Unit 2.7 e t le F INCM ) s t( Max TSA1002 39 38 37 1 36 NC 2 35 NC VREFM 3 34 NC AGND 4 33 D0 (LSB) VIN 5 AGND 6 E S IPOL VREFP D 32 D1 VINB AGND 8 29 D4 INCM 9 28 D5 AGND 10 AVCC 11 AVCC 12 25 D8 21 22 23 24 GNDB VCCB OR R O Observation Analog bias current input Top voltage reference 1V VREFM Bottom voltage reference 0V 4 AGND Analog ground 0V Analog input 1Vpp VIN O 6 T VREFP 3 AGND Analog ground VINB Inverted analog input 8 AGND Analog ground 9 INCM Input common mode 10 AGND Analog ground 11 AVCC 12 AVCC N 7 14 15 bs 16 17 (s) t c u 0V 1Vpp D8 Digital output Digital output CMOS output (2.5V) 28 D5 Digital output CMOS output (2.5V) 29 D4 Digital output CMOS output (2.5V) 30 D3 Digital output CMOS output (2.5V) 31 D2 Digital output CMOS output (2.5V) Digital output CMOS output (2.5V) Least Significant Bit output CMOS output (2.5V) D1 33 D0(LSB) 0V 34 NC Non connected Analog power supply 2.5V 35 NC Non connected Analog power supply 2.5V 36 NC Non connected 2.5V 37 NC Non connected Digital power supply DVCC Digital power supply 2.5V 38 DR DGND Digital ground 0V 39 VCCB CLK CMOS output (2.5V) D7 D6 32 r P e Observation CMOS output (2.5V) 27 DVCC DGND Description Digital output 0.5V od ) s t( o r P 0V t e l o 13 b O 26 Name c u d e t le so Pin No 25 2 5 O Description F IPOL D9 (MSB) 20 GNDB N 26 D7 18 19 NC Name 1 30 D3 27 D6 DGND 17 DGND DGND DVCC 16 CLK 14 15 E W TSA1002 DVCC Pin No 31 D2 7 13 PIN DESCRIPTION IG VCCB 41 40 NC GNDB 42 DR NC 44 43 VCCB 45 NC DFSB 48 OEB AVCC 47 46 AVCC AGND index corner N PIN CONNECTIONS (top view) Data Ready output CMOS output (2.5V) Digital Buffer power supply 2.5V Clock input 2.5V compatible CMOS input 40 GNDB Digital Buffer ground 0V Digital ground 0V 41 VCCB Digital Buffer power supply 2.5V 42 NC Non connected 0V 43 NC Non connected 18 NC Non connected 19 DGND Digital ground 20 GNDB Digital buffer ground 0V 44 OEB Output Enable input 21 GNDB Digital buffer ground 0V 45 DFSB Data Format Select input 2.5V compatible CMOS input 22 VCCB Digital buffer power supply 2.5V 46 AVCC Analog power supply 2.5V 23 OR 24 D9(MSB) 2.5V compatible CMOS input Out Of Range output CMOS output (2.5V) 47 AVCC Analog power supply 2.5V Most Significant Bit output CMOS output (2.5V) 48 AGND Analog ground 0V 3/20 TSA1002 IG N ELECTRICAL CHARACTERISTICS AVCC = DVCC = VCCB = 2.5V, Fs= 40Msps,Fin= 1MHz, Vin@ -1.0dBFS, VREFM= 0V Tamb = 25 C (unless otherwise specified) TIMING CHARACTERISTICS Parameter Test conditions Sampling Frequency DC Clock Duty Cycle TC1 Clock pulse width (high) TC2 Clock pulse width (low) Tod Data Output Delay (Fall of Clock 10pF load capacitance to Data Valid) Tpd Data Pipeline delay Ton Falling edge of OEB to digital output valid data Toff Rising edge of OEB to digital output tri-state CLK N r P e OEB t e l o N-7 D ns 9 10 ns 5 ns 5.5 cycles N-5 ns uc N+6 o s b O - N+7 N+8 Tpd + Tod Ton N-4 N-3 N-2 N+1 N-1 s b O DR HZ state 4/20 ) s t( P e let Toff N-6 % d o r Tod DATA OUT 60 10 W u d o Msps 9 E ) s ( ct 50 50 N N+1 N Unit 40 1 R O F N+2 Max 1 N+3 O T N-1 Typ 0.5 E FS TIMING DIAGRAM Min S Symbol N+2 ns TSA1002 N CONDITIONS AVCC = DVCC = VCCB = 2.5V, Fs= 40Msps,Fin= 1MHz, Vin@ -1.0dBFS, VREFM= 0V Tamb = 25 C (unless otherwise specified) Symbol Parameter IG ANALOG INPUTS Test conditions Min S VIN-VINB Full scale reference voltage Typ Equivalent input resistance Cin Input capacitance BW Analog Input Bandwidth ERB Effective Resolution Bandwidth 1) E Req D Vin@ Full scale, FS=50Msps Max Unit 2.0 Vpp 13 kΩ 5.0 pF 1000 MHz 60 MHz W 1) See parameters definition for more information REFERENCE VOLTAGE VREFP Test conditions E Parameter Top internal reference voltage N Symbol Analog bias voltage O Vpol R Tmin= -40 C to Tmax= 85 C Ipol Analog bias current Shutdown mode F Normal operating mode T 0.91 1.03 0.88 o s b O - Tmin= -40 C to Tmax= 85 C1) 1.18 50 0.47 0.46 1.27 70 ) s t( Max uc d o r P e let Tmin= -40 C to Tmax= 85 C1) Analog bias current Input common mode voltage Typ 1.20 Ipol VINCM 1) Min 1.14 V 1.16 V 1.35 V 1.36 V 100 µA 0 0.57 Unit µA 0.68 V 0.66 V 1) Not fully tested over the temperature range. Guaranteed by sampling. O ) s ( ct N u d o r P e t e l o s b O 5/20 TSA1002 N CONDITIONS AVCC = DVCC = VCCB = 2.5V, Fs= 40Msps,Fin= 1MHz, Vin@ -1.0dBFS, VREFP=1V, VREFM= 0V Tamb = 25 C (unless otherwise specified) Parameter Test conditions Min 1) ICCA Analog Supply current E Tmin= -40 C to Tmax= 85 C2) 1) Digital Supply Current PdZ Power consumption in High Impedance mode Rthja Junction-ambient thermal resistor (TQFP48) 1) 1) 1) ) s ( ct Logic "0" voltage N Digital inputs Logic "1" voltage VIH o r P e Digital Outputs VOL o s b O Test conditions du Logic "0" voltage 21 mA 2 mA 2 mA 5 mA 5 mA 40 100 µA 48 60 mW t e l o uc Min od 43 ) s t( 62 mW 48 mW 80 Typ C/W Max Unit 0.8 V V Iol=10µA 0.4 Logic "1" voltage IOZ High Impedance leakage current OEB set to VIH bs mA 2.0 VOH CL r P e t le R O F Parameter O T DIGITAL INPUTS AND OUTPUTS VIL 18 Tmin= -40 C to Tmax= 85 C2) 1) Rpol= 18KΩ. Equivalent load: Rload= 470Ω and Cload= 6pF 2) Not fully tested over the temperature range. Guaranteed by sampling. Symbol 15.6 Tmin= -40 C to Tmax= 85 C2) W Digital Buffer Supply Current in High Impedance Mode Power consumption in normal operation mode Pd Unit 2.5 E Digital Buffer Supply Current N ICCBZ Max Tmin= -40 C to Tmax= 85 C2) 1) ICCB Typ 1.3 D ICCD S Symbol IG POWER CONSUMPTION Ioh=-10µA 2.4 V V -1.5 Output Load Capacitance 1.5 µA 15 pF O ACCURACY Symbol Parameter Test conditions Min Typ Max Unit OE Offset Error Fin= 2MHz, VIN@+1dBFS -40 -2 40 mV DNL Differential Non Linearity Fin= 2MHz, VIN@+1dBFS -0.7 ±0.2 +0.7 LSB INL Integral Non Linearity Fin= 2MHz, VIN@+1dBFS -0.8 ±0.3 +0.8 LSB 6/20 Monotonicity and no missing codes Guaranteed CONDITIONS AVCC = DVCC = 2.5V, Fs= 40Msps Vin@ -1.0dBFS, VREFP=1V, VREFM= 0V Tamb = 25 C (unless otherwise specified) Symbol Parameter IG DYNAMIC CHARACTERISTICS Test conditions Min 1) E SFDR S Fin= 5MHz Fin= 10MHz Fin= 24MHz Spurious Free Dynamic Range 2) W Fin= 5MHz SNR 1) E Fin= 10MHz Fin= 24MHz Signal to Noise Ratio Fin= 5MHz N Fin= 10MHz Fin= 24MHz 2) R O T O SINAD Signal to Noise and Distortion Ratio ct N u d o r P e t e l o ENOB s b O (s) so 2) 1) Fin= 5MHz -63.4 dBc dBc 58.5 59.5 58.3 59.4 57.4 59.0 dB uc d o r ) s t( -77.8 -63.5 -76 -67.4 -68.1 -62.5 dB dB -62.3 -60.7 dB -57.6 58.5 59.4 58.2 59.3 57.0 58.5 dB 57.8 2) 56.9 dB 55.3 Fin= 5MHz Fin= 10MHz Fin= 24MHz -68.5 -69 Unit -58.5 P e let 1) b O - Fin= 10MHz Fin= 24MHz -77 -62.8 55.9 Fin= 5MHz Fin= 10MHz Fin= 24MHz -65.5 57.1 Fin= 5MHz Fin= 10MHz Fin= 24MHz -79.2 57.9 Total Harmonic Distortion F THD Max -61.5 Fin= 5MHz Fin= 10MHz Fin= 24MHz Typ D Fin= 5MHz Fin= 10MHz Fin= 24MHz N TSA1002 1) 9.6 9.76 9.5 9.71 9.3 9.60 bits Effective Number of Bits Fin= 5MHz Fin= 10MHz Fin= 24MHz 9.4 2) 9.3 bits 9 1) Rpol= 18KΩ. Equivalent load: Rload= 470Ω and Cload= 6pF 2) Tmin= -40 C to Tmax= 85 C. Not fully tested over the temperature range. Guaranteed by sampling. 7/20 TSA1002 Signal to Noise Ratio (SNR) The ratio of the rms value of the fundamental component to the rms sum of all other spectral components in the Nyquist band (fs/2) excluding DC, fundamental and the first five harmonics. SNR is reported in dB. Differential Non Linearity (DNL) The average deviation of any output code width from the ideal code width of 1 LSB. S Similar ratio as for SNR but including the harmonic distortion components in the noise figure (not DC signal). It is expressed in dB. From the SINAD, the Effective Number of Bits (ENOB) can easily be deduced using the formula: SINAD= 6.02 × ENOB + 1.76 dB. When the applied signal is not Full Scale (FS), but has an A0 amplitude, the SINAD expression becomes: SINAD2Ao=SINADFull Scale+ 20 log (2A0/FS) SINAD2Ao=6.02 × ENOB + 1.76 dB + 20 log (2A0/ FS) The ENOB is expressed in bits. W Integral Non linearity (INL) Signal to Noise and Distortion Ratio (SINAD) E Static measurements are performed through method of histograms on a 2MHz input signal, sampled at 40Msps, which is high enough to fully characterize the test frequency response. The input level is +1dBFS to saturate the signal. D STATIC PARAMETERS IG N DEFINITIONS OF SPECIFIED PARAMETERS N E An ideal converter presents a transfer function as being the straight line from the starting code to the ending code. The INL is the deviation for each transition from this ideal curve. DYNAMIC PARAMETERS O R Dynamic measurements are performed by spectral analysis, applied to an input sine wave of various frequencies and sampled at 40Msps. T F The input level is -1dBFS to measure the linear behavior of the converter. All the parameters are given without correction for the full scale amplitude performance except the calculated ENOB parameter. Spurious Free Dynamic Range (SFDR) O ) s ( ct N u d o Total Harmonic Distortion (THD) The ratio of the rms sum of the first five harmonic distortion components to the rms value of the fundamental line. It is expressed in dB. t e l o s b O 8/20 o r P Analog Input Bandwidth The maximum analog input frequency at which the spectral response of a full power signal is reduced by 3dB. Higher values can be achieved with smaller input levels. e t le o s b O - The ratio between the power of the worst spurious signal (not always an harmonic) and the amplitude of fundamental tone (signal power) over the full Nyquist band. It is expressed in dBc. r P e c u d ) s t( Effective Resolution Bandwidth (ERB) The band of input signal frequencies that the ADC is intended to convert without loosing linearity i.e. the maximum analog input frequency at which the SINAD is decreased by 3dB or the ENOB by 1/2 bit. Pipeline delay Delay between the initial sample of the analog input and the availability of the corresponding digital data output, on the output bus. Also called data latency. It is expressed as a number of clock cycles. TSA1002 N Static parameter: Integral Non Linearity Fs=50MSPS; Fin=1MHz; Icc=20mA; N=131072pts IG 0 .8 0 .6 S 0 .2 0 E INL (LSBs) 0 .4 - 0 .2 D - 0 .4 - 0 .6 0 200 400 W - 0 .8 600 800 1000 E O u tp u t C o d e N Static parameter: Differential Non Linearity c u d 0 .5 R 0 .4 e t le O 0 -0 .1 -0 .2 T -0 .3 -0 .4 (s) 0 200 N O -0 .5 d o r P e Linearity vs. Fs Fin=5MHz; Rpol adjustment t e l o 100 Dynamic parameters (dB) 400 t c u 90 s b O 8 70 7 SNR 60 6 SINAD 5 40 30 4 25 35 45 Fs (MHz) 55 800 1000 Distortion vs. Fs Fin=5MHz; Rpol adjustment -30 9 80 50 600 O u tp u t C o d e 10 ENOB o r P o s b O - Dynamic parameters (dB) 0 .1 ENOB (bits) 0 .2 F DNL (LSBs) 0 .3 ) s t( Fs=50MSPS; Fin=1MHz; Icc=20mA;N=131072pts -40 -50 -60 THD -70 -80 SFDR -90 -100 -110 -120 25 35 45 55 Fs (MHz) 9/20 10 8 70 SNR 7 SINAD 6 60 50 40 5 30 4 35 45 E ENOB (bits) 8.5 8 F 7.5 7 SINAD 6.5 50 6 5.5 (s) 5 O 40 0 20 40 60 N d o r P e t e l o Dynamic Parameters (dB) s b O 65 SNR 55 SINAD 50 45 -40 10 Temperature ( C) 10/20 60 55 e t le -50 -60 -70 c u d ) s t( o r P THD SFDR -80 -90 -100 0 20 40 60 Fin (MHz) Distortion vs. Temperature Fs=50MSPS; Icca=20mA; Fin=5MHz; 10 9.8 9.6 9.4 9.2 9 8.8 8.6 8.4 8.2 8 ENOB 60 -40 t c u Fin (MHz) Linearity vs.Temperature Fs=50MSPS; Icca=20mA; Fin=5MHz 70 45 Fs (MHz) o s b O - 90 Dynamic Parameters (dB) 45 Dynamic parameters (dB) R O 9 T Dynamic parameters (dB) 55 35 -30 9.5 SNR 60 -110 Distortion vs. Fin Fs=50MSPS; Icca=20mA 10 65 -90 -100 25 80 70 SFDR -80 -120 N Linearity vs. Fin Fs=50MSPS; Icca=20mA ENOB THD -70 55 Fs (MHz) 75 -60 W 25 -50 S 80 -40 E 9 D ENOB Dynamic parameters (dB) 90 -30 ENOB (bits) Dynamic parameters (dB) 100 IG Distortion vs. Fs Fin=15MHz; Rpol adjustment Linearity vs. Fs Fin=15MHz; Rpol adjustment N TSA1002 85 80 SFDR 75 70 THD 65 60 55 50 45 -40 10 Temperature ( C) 60 TSA1002 62 9.7 61 9.6 ENOB 9.5 60 9.4 SNR 59 58 9.3 SINAD 9.2 57 9.1 56 2.25 9 2.45 2.55 2.65 E N Linearity vs. DVcc Fs=50MSPS; Icca=20mA; Fin=1MHz F 9.7 9.6 SINAD 52 9.5 (t s) 9.4 2.35 2.45 DVCC (V) N O 50 2.25 o r P e 2.55 2.65 c u d t e l o s b O 66 9.8 9.7 9.5 62 9.4 SNR 9.3 58 SINAD 9.2 56 54 2.25 9.1 9 2.35 2.45 VCCB (V) -95 2.35 2.45 2.55 2.65 2.55 2.65 AVCC (V) c u d -50 e t le -60 -70 -80 ) s t( o r P SFDR THD -90 2.35 2.45 2.55 2.65 -40 9.9 9.6 60 -90 Distortion vs. VccB Fs=50MSPS; Icca=20mA; Fin=1MHz 10 ENOB 64 THD DVCC (V) ENOB (bits) Dynamic parameters (dB) 68 -85 -100 2.25 Linearity vs. VccB Fs=50MSPS; Icca=20mA; Fin=1MHz 70 -80 o s b O - Dynamic Parameters (dB) 54 Dynamic parameters (dB) R ENOB 56 9.8 ENOB (bits) 58 -75 -40 9.9 O 60 SFDR -70 Distortion vs. DVcc Fs=50MSPS; Icca=20mA; Fin=1MHz 10 T Dynamic parameters (dB) 64 SNR -65 -100 2.25 AVCC (V) 62 -60 W 2.35 -55 S 9.8 IG -50 E 63 9.9 D 10 Dynamic Parameters (dB) 64 N Distortion vs. AVcc Fs=50MSPS; Icca=20mA; Fin=1MHz ENOB (bits) Dynamic parameters (dB) Linearity vs. AVcc Fs=50MSPS; Icca=20mA; Fin=1MHz -50 -60 -70 THD -80 SFDR -90 -100 2.25 2.35 2.45 2.55 2.65 VCCB (V) 11/20 IG N TSA1002 APPLICATION NOTE couple for each stage. The corrected data are outputted through the digital buffers. Input signal is sampled on the rising edge of the clock while digital outputs are delivered on the falling edge of the Data Ready signal. The advantages of such a converter reside in the combination of pipeline architecture and the most advanced technologies. The highest dynamic performances are achieved while consumption remains at the lowest level. Some functionalities have been added in order to simplify as much as possible the application board. These operational modes are described in the following table. The TSA1002 is pin to pin compatible with the 8bits/40Msps TSA0801, the 10bits/25Msps TSA1001 and the 12bits/50Msps TSA1201. This ensures a conformity within the product family and above all, an easy upgrade of the application. DETAILED INFORMATION E W D E S The TSA1002 is a high speed analog to digital converter based on a pipeline architecture and the latest deep submicron CMOS process to achieve the best performances in terms of linearity and power consumption. The pipeline structure consists of 9 internal conversion stages in which the analog signal is fed and sequentially converted into digital data. Each 8 first stages consists of an Analog to Digital converter, a Digital to Analog converter, a Sample and Hold and a gain of 2 amplifier. A 1.5bit conversion resolution is achieved in each stage. The latest stage simply is a comparator. Each resulting LSB-MSB couple is then time shifted to recover from the conversion delay. Digital data correction completes the processing by recovering from the redundancy of the (LSB-MSB) R N c u d O e t le OPERATIONAL MODES DESCRIPTION DFSB OEB OR DR Most Significant Bit (MSB) H H H L L L X L L L L L L H H H L H H L HZ CLK CLK CLK CLK CLK CLK HZ D9 D9 D9 Complemented D9 Complemented D9 Complemented D9 HZ F > > (VIN-VINB) > > (VIN-VINB) X N O T (VIN-VINB) -RANGE RANGE> (VIN-VINB) -RANGE RANGE> RANGE (VIN-VINB) >-RANGE RANGE (VIN-VINB) >-RANGE ) s ( ct r P e u d o b O - Data Format Select (DFSB) t e l o When set to low level (VIL), the digital input DFSB provides a twoís complement digital output MSB. This can be of interest when performing some further signal processing. When set to high level (VIH), DFSB provides a standard binary output coding. s b O Output Enable (OEB) When set to low level (VIL), all digital outputs remain active and are in low impedance state. When set to high level (VIH), all digital outputs buffers are in high impedance state. This results in lower consumption while the converter goes on sampling. 12/20 o r P so Inputs Analog input differential level ) s t( Outputs When OEB is set to low level again, the data is then valid on the output with a very short Ton delay. The timing diagram page 4 summarizes this operating cycle. Out of Range (OR) This function is implemented on the output stage in order to set up an "Out of Range" flag whenever the digital data is over the full scale range. Typically, there is a detection of all the data being at í0í or all the data being at í1í. This ends up with an output signal OR which is in low level state (VOL) when the data stay within the range, or in high level state (VOH) when the data are out of the range. TSA1002 N IG In case of analog dynamic lower than 2Vpp, the best linearity and distortion performance is achieved while increasing the VREFM voltage instead of lowering the VREFP one. The INCM is the mid voltage of the analog input signal. E The Data Ready output is an image of the clock being synchronized on the output data (D0 to D9). This is a very helpful signal that simplifies the synchronization of the measurement equipment or the controlling DSP. As digital output, DR goes in high impedance state when OEB is asserted to High level as described in the timing diagram page 4. The VREFP, VREFM voltages set the analog dynamic at the input of the converter that has a full scale amplitude of 2*(VREFP-VREFM). S Data Ready (DR) It is possible to use an external reference voltage device for specific applications requiring even better linearity, accuracy or enhanced temperature behavior. D REFERENCES AND COMMON MODE CONNECTION Using the STMicroelectronics TS821 or TS4041-1.2 Vref leads to optimum performances when configured as shown on Figure 2. W VREFM must be always connected externally. Internal reference and common mode Figure 2 : External reference setting c u d O R N E In the default configuration, the ADC operates with its own reference and common mode voltages generated by its internal bandgap. VREFM pin is connected externally to the Analog Ground while VREFP (respectively INCM) is set to its internal voltage of 1.03V (respectively 0.57V). It is recommended to decouple the VREFP in order to minimize low and high frequency noise (refer to Figure 1) F Figure 1 : Internal reference and common mode setting T 1.03V O VIN 330pF 10nF TSA1002 VINB ) s ( ct 0.57V INCM 330pF 10nF VREFM N 4.7uF VREFP 4.7uF External reference and common mode t e l o Each of the voltages VREFM, VREFP and INCM can be fixed externally to better fit to the application needs (Refer to Table íOPERATING CONDITIONSí p2 for min and max values). s b O 13/20 o r P VCCA VREFP VIN e t le TSA1002 VINB o s b O - u d o r P e 1kΩ VREFM ) s t( 330pF 10nF 4.7uF TS821 TS4041 external reference At 15Msps sampling frequency, 1MHz input frequency and -1dBFS amplitude signal, performances can be improved up to 2dB on SFDR and 0.3dB on SINAD. At 50Msps sampling frequency, 1MHz input frequency and -1dBFS amplitude signal, performances can be improved up to 1dBc on SFDR and 0.6dB on SINAD. This can be very helpful for example for multichannel application to keep a good matching among the sampling frequency range. TSA1002 Figure 3 : Differential input configuration with transformer Figure 5 : DC-coupled 2Vpp differential analog input W ADT1-1 1:1 VIN 100pF O F T O N r P e t e l o Figure 4 : AC-coupled differential input 50Ω VIN 10nF 100kΩ 33pF common mode 50Ω INCM 100kΩ 10nF TSA1002 VINB d o r 330pF 10nF 4.7uF P e let VREFP-VREFM = 1 V o s b O - The common mode voltage of the ADC (INCM) is connected to the center-tap of the secondary of the transformer in order to bias the input signal around this common voltage, internally set to 0.57V. The INCM is decoupled to maintain a low noise level on this node. Our evaluation board is mounted with a 1:1 ADT1-1WT transformer from Minicircuits. You might also use a higher impedance ratio (1:2 or 1:4) to reduce the driving requirement on the analog signal source. For example, with internal references, each analog input can drive a 1Vpp amplitude input signal, so the resultant differential amplitude is 2Vpp. u d o uc VREFM INCM 4.7uF ) s ( ct ) s t( TSA1002 VINB DC R 10nF VREFP VIN analog N 330pF INCM AC+DC DC TSA1002 VINB s b O analog E 50Ω IG D Figure 3 describes the schematics. The input signal is fed to the primary of the transformer, while the secondary drives both ADC inputs. Figure 5 shows a DC-coupled configuration with forced INCM to the DC analog input (mid-voltage) while VREFM is connected to ground and VREFP is let internal (1V); we achieve a 2Vpp differential amplitude. S The TSA1002 has been designed to obtain optimum performances when being differentially driven. An RF transformer is a good way to achieve such performances. E Differential inputs Analog source Figure 4 represents the biasing of a differential input signal in AC-coupled differential input configuration. Both inputs VIN and VINB are centered around the common mode voltage, that can be let internal or fixed externally. N DRIVING THE ANALOG INPUT Single-ended input configuration The single-ended input configuration of the TSA1002 requires particular biasing and driving. The structure being fully differential, care has to be taken in order to properly bias the inputs in single ended mode. Figure 6 summarizes the link from the differential configuration to the single-ended one; a wrong configuration is also presented. - With differential driving, both inputs are centered around the INCM voltage. - The transition to single-ended configuration implies to connect the unused input (VINB for instance) to the DC component of the single input (Vin) and also to the input common mode in order to be well balanced. The mid-code is achieved at the crossing between VIN and VINB, therefore inputs are conveniently biased. - Unlikely other structures of converters in which the unused input can be grounded; in our case it will end with unbalanced inputs and saturation of the internal amplifiers leading to a non respect of the output codes. 14/20 TSA1002 Figure 6 : Input dynamic range for the various configurations Single-ended configuration: balanced inputs Single-ended configuration: unbalanced inputs N Differential configuration +FS: code 1023 +FS + offset: code > 1023 IG +FS: code 1023 VIN - VINB VIN - VINB VIN - VINB VIN VIN 0: code 511 VINB INCM S VINB INCM E INCM VIN D 0: code 511 -FS: code 0 Ao + ac VINB VINB INCM Ao R O F T O ) s ( ct Figure 7 : AC-coupled Single-ended input N u d o r P e 10nF 50Ω 33pF t e l o common mode 100kΩ VIN INCM o r P Figure 8 : DC-coupled 2Vpp analog input e t le Analog AC+DC VREFP VIN DC TSA1002 VINB VREFM INCM 330pF 10nF Figure 9 : DC-coupled 1Vpp analog input Analog AC+DC VIN DC TSA1002 VINB VINB Figure 9 describes a configuration for a 1Vpp analog signal with a 0.5V DC input. In this case, while VREFP is kept internally at 1V, VREFM is connected to VINB and INCM externally to 0.5V; the dynamic is then 1Vpp (VREFP-VREFM=0.5V). 4.7uF VREFP-VREFM = 1 V 100kΩ s b O 15/20 c u d TSA1002 In the case of DC-coupled analog input with 1V DC signal, the DC component of the analog input set the common mode voltage. As an example figure 8, INCM is set to the 1V DC analog input while VREFM is connected to ground and VREFP let internal; we achieve a 2Vpp differential amplitude. ) s t( INCM Ao Wrong configuration! o s b O - In the case of AC-coupled analog input, the analog inputs Vin and Vinb are biased to the same voltage that is the common mode voltage of the circuit (INCM). The INCM and reference voltages may remain at their internal level but can also be fixed externally. VIN VINB INCM Ao The applications requiring single-ended inputs can be configured like reported on Figure 7 for an AC-coupled input or on Figure 8 and 9 for a DC-coupled input. Signal source Ao + ac VIN E VIN N Ao + ac W Ao + ac -FS + offset: code > 0 -FS: code 0 0.5V power supply 330pF 10nF VREFM INCM 4.7uF VREFP-VREFM = 0.5 V Dynamic characteristics, while not being as remarkable as for differential configuration, are still of very good quality. Measurements done at 50Msps, 2MHz input frequency, -1dBFS input level sum up these performances. An SFDR of -64.5dBc, a SNR of 57.8dB and an ENOB Full Scale of 9.3bits are achieved. TSA1002 ICCA O 10 2 0 65 75 O T Linearity, distortion performance towards Clock Duty Cycle variation (s) r P e 9 SNR 8 SINAD 7 40 6 IccA 30 5 20 4 10 0 3 30 40 50 Duty Cycle (%) 60 70 ENOB (bits) Dynamic parameters (dB), analog current cons. (mA) 70 50 IG IccA (mA) S E 20 IccA 10 40 50 60 70 Duty Cycle (%) ) s t( c u d o r P ENOB 75 70 e t le 65 10 9.5 9 8.5 SNR 60 so 55 50 8 7.5 SINAD 7 45 6.5 40 6 35 5.5 30 5 40 45 50 55 60 Distortion vs. Duty cycle Fs=50MSPS; Icca=20mA; Fin=10MHz 0 10 ENOB 60 30 Duty Cycle (%) Dynamic Parameters (dB) N u d o Linearity vs. Duty cycle Fs=50MSPS; consumption optimized; Fin=1MHz O N ct bs 40 SFDR -110 b O - The TSA1002 has an outstanding behaviour towards clock duty cycle variation and it may be also reinforced with adjustment of analog current consumption. t e l o -90 -100 80 4 F 55 6 Fs (MHz) 80 -80 50 THD ENOB (bits) 8 20 45 -70 60 Linearity vs. Duty cycle Fs=50MSPS; Icca=20mA; Fin=10MHz Dynamic parameters (dB) 10 35 -60 W E N Rpol (kOhms) 12 30 R Icca (mA) 14 40 25 70 18 16 0 -50 30 20 RPOL 50 -40 -120 Figure 10 : Analog Current consumption vs. Fs According value of Rpol polarization resistance 60 -30 D The internal architecture of the TSA1002 enables to optimize the power consumption according to the sampling frequency of the application. For this purpose, a resistor is placed between IPOL and the analog Ground pins. The figure 10 sums up the relevant data. The TSA1002 will combine highest performances and lowest consumption at 50Msps when Rpol is in the range of 12kΩ to 20kΩ. At lower sampling frequency, this value of resistor may be changed and the consumption will decrease as well. Distortion vs. Duty cycle Fs=50MSPS; consumption optimized; Fin=1MHz Dynamic Parameters (dB) Power consumption -10 -20 -30 -40 -50 THD -60 -70 SFDR -80 -90 -100 40 45 50 55 60 Duty Cycle (%) 16/20 TSA1002 It is recommended to keep the circuit clocked, to avoid random states, before applying the supply voltages. N IG - To keep the capacitive loading as low as possible at digital outputs, short lead lengths of routing are essential to minimize currents when the output changes. To minimize this output capacitance, buffers or latches close to the output pins will relax this constraint. - Choose component sizes as small as possible (SMD). W Layout precautions S The clock power supplies must be separated from the ADC output ones to avoid digital noise modulation at the output. E The quality of your converter is very dependant on your clock input accuracy, in terms of aperture jitter; the use of low jitter crystal controlled oscillator is recommended. - Proper termination of all inputs and outputs is needed; with output termination resistors, the amplifier load will be only resistive and the stability of the amplifier will be improved. All leads must be wide and as short as possible especially for the analog input in order to decrease parasitic capacitance and inductance. D Clock input E To use the ADC circuits in the best manner at high frequencies, some precautions have to be taken for power supplies: R N - First of all, the implementation of 4 separate proper supplies and ground planes (analog, digital, internal and external buffer ones) on the PCB is recommended for high speed circuit applications to provide low inductance and low resistance common return. F O The separation of the analog signal from the digital part is essential to prevent noise from coupling onto the input signal. T O c u d o r P The dataready signal is the acquisition clock of the logic analyzer. e t le The ADC digital outputs are latched by the 74LCX573 octal buffers. All characterization measurement has been made with an input amplitude of +0.2dB for static parameters and -0.5dB for dynamic parameters. Figure 11 : Analog to Digital Converter characterization bench N u d o r P e t e l o HP8644 s b O 17/20 Sine Wave Generator Data Vin ADC evaluation board Logic Analyzer Clk Clk HP8133 Pulse Generator HP8644 Sine Wave Generator ) s t( The characterization of the board has been made with a fully ADC devoted test bench as shown on Figure 11. The analog signal must be filtered to be very pure. o s b O - - Power supply bypass capacitors must be placed as close as possible to the IC pins in order to improve high frequency bypassing and reduce harmonic distortion. ) s ( ct EVAL1002 evaluation board PC 1BCCV 1 2 1BccV 81J µ74 53C µ01 42C Fn074 91C Fn01 4 3 81C Fp033 TW1-1TA-2T 1T 71C Fµ01 92C 1 1 2 CCVA CCVA DNGA MCNI DNGA BNIV DNGA niV DNGA MferV PferV lopI BMS/JLC 4J 3R 6 05 2 24 23 22 21 20 19 18 17 16 15 14 13 D O 52. NG NG GD NC GD CL GD VD VD VDDN NKNC C CC UB UB D D D C C UBF FF FF F 2001AST CDA stib41-8 2 2 VC5. NG VC5. AAA BC DB BC ODVVG D0 R UFF UFF UFF NC NC BE BFS CC CC DN 21D 13 R 11D 01D 9D 8D 7D 6D 5D 4D 3D 2D 1D D 37 38 39 40 41 42 43 44 45 46 47 48 Fp033 41C Fn01 K74 31R K74 21R K74 01R 11R K74 9J BSFD CCVD 51J 3C Fn01 Fn074 Fp033 03C 21C 31C 4C Fn01 Fn074 12 µ01 11C Fp033 2C Fp033 02C 12C Fp033 22C Fn01 32C Fn074 µ74 63C 2NOC 61J 21 11 01 9 8 7 6 5 4 3 2 1 K1 2R K74 1jaR Fn01 13C Fn074 23C CCVA 5C Fp033 8C Fp033 Fp001 1C Fµ01 14C 6C 7C Fn01 Fn074 9C 01C Fn01 Fn074 2 6 Fµ74 24C 2T TW1-1TA-2T 4 + N 01 9 8 7 6 5 4 3 2 1 52 62 72 82 92 03 13 23 33 43 53 63 1U O R Fp033 33C Fn01 04C Fn074 83C 375XCL47 EL DNG 7Q 7D 6Q 6D 5Q 5D 4Q 4D 3Q 3D 2Q 3U 2D 1Q 1D 0Q 0D CCV BEO 01 9 8 7 6 5 4 3 2 1 Fp033 F 11 21 31 41 51 61 71 81 91 02 E 375XCL47 EL DNG 7Q 7D 6Q 6D 5Q 5D 4Q 2U 4D 3Q 3D 2Q 2D 1Q 1D 0Q 0D CCV BEO K74 K74 K74 K74 K74 K74 91R 81R 71R 61R 51R 41R 52C Fn01 2 1 51C Fn074 01J BEO 72C Fn074 2 1 CCVA 61C 21 11J T W D E S RO 31D 21D 11D 01D 9D 8D 7D 6D 5D 4D 3D 11 21 31 41 51 61 71 81 91 02 Fp033 62C Fn01 + 1BCCV 82C 21 s b O t e l o 2D 1D OD RD 31J O IG 23 13 03 92 82 72 62 52 42 32 22 12 02 91 81 71 61 51 41 31 21 11 01 9 8 7 6 5 4 3 2 1 93C Fn074 73C µ74 43C 71J V3FFUBDDV r P e + NIP23 6J 2BCCV 21 u d o o r P e t le + c u d ) s t( + o s b O - ) s ( ct N N TSA1002 Figure 12: TSA1002 Evaluation board schematic 1BdnG 2 1 22J 2BdnG 2 1 12J DNGD 2 1 02J DNGA 2 1 91J 1J niV CCVA 1 2 21J edoM moc seM 2 1 8J edom moc lgeR 2 1 7J 3 05 1R 1 MferV 2 1 5J PferV 2 1 2J 18/20 TSA1002 E W D E S IG N Figure 13: Printed circuit of evaluation board R N c u d T F O e t le ) s ( ct O Printed circuit board - List of components P art D e sign F o o t print T ype at o r P a rt D esign F o o tprint 10 uF C24 1210 3 30 pF C 33 10 uF C23 1210 3 30 pF C 20 10 uF C41 1210 3 30 pF N T ype at o r 10 uF C29 10 0pF C1 10 nF C 12 10 nF C39 10 nF C 15 10 nF C40 10 nF 10 nF o r P e ) s t( o r P o s b O P a rt D es ign F o o t print P art D es ign F o o t print T ype a to r T ype at o r 60 3 470 nF C7 8 05 A VC C J12 60 3 470 nF C 16 8 05 C LJ / S M B J4 SM B / H C8 60 3 470 nF C 19 8 05 A GN D J19 F IC H E 2M M F IC H E 2M M du F IC H E 2M M 1210 3 30 pF C2 60 3 470 nF C3 8 05 D F SB J9 60 3 3 30 pF C5 60 3 47K Ω R 12 6 03 D GN D J2 0 F IC H E 2M M 60 3 3 30 pF C 11 60 3 47K Ω R 14 6 03 D VC C J15 F IC H E 2M M 60 3 3 30 pF C 30 60 3 47K Ω R 11 6 03 G ndB 1 J2 2 F IC H E 2M M 60 3 3 30 pF C 17 60 3 47K Ω R aj1 VR5 G ndB 2 J2 1 60 3 3 30 pF C 14 60 3 47K Ω R 10 6 03 M e s c o m mo de J8 F IC H E 2M M C27 60 3 4 7uF C 36 CAP 47K Ω R 19 6 03 OEB F IC H E 2M M C4 60 3 4 7uF C 34 CAP 47K Ω R 13 6 03 R egl co m m o de J7 F IC H E 2M M 10 nF C21 60 3 4 7uF C 35 CAP 47K Ω R 15 6 03 T 2- A T 1- 1WT T2 AD T 10 nF C31 60 3 4 7uF C 42 CAP 47K Ω R 16 6 03 T 2- A T 1- 1WT T1 AD T 10 nF C6 60 3 4 70 nF C 22 80 5 47K Ω R 17 6 03 V cc B 1 J18 F IC H E 2M M 10 nF C9 60 3 4 70 nF C 32 80 5 47K Ω R 18 6 03 V D D B UF F 3V J17 F IC H E 2M M 10 nF C 18 60 3 4 70 nF C 37 80 5 50 Ω R3 6 03 V in J1 SM B / H 1K Ω R2 60 3 4 70 nF C 38 80 5 50 Ω R1 6 03 V ref M J5 F IC H E 2M M 3 2P IN J6 ID C 32 4 70 nF C 13 80 5 74LC X 57 3 U3 T S S O P 20 V ref P J2 F IC H E 2M M 3 30pF C25 60 3 4 70 nF C 28 80 5 74LC X 57 3 U2 T S S O P 20 T S A 100 2 U1 T Q F P 48 3 30pF C26 60 3 4 70 nF C 10 80 5 CON 2 S IP 2 t e l o s b O 19/20 J 16 J10 F IC H E 2M M TSA1002 N PACKAGE MECHANICAL DATA 48 PINS - PLASTIC PACKAGE A1 37 12 25 S 36 N O T A A1 A2 B C D D1 D3 e E E1 E3 L L1 K s b O 0.45 1.40 0.22 ) s ( ct u d o r P e t e l o Typ. 0.05 1.35 0.17 0.09 D L N R O Min. c 9.00 7.00 5.50 0.50 9.00 7.00 5.50 0.60 1.00 Max. e t le 1.60 0.15 1.45 0.27 0.20 0.002 0.053 0.007 0.004 o s b O - 0.75 Min. 0.018 c u d ) s t( o r P 0,25 mm .010 inch GAGE PLANE K Millimeters F Dim. L1 24 D3 D1 D E 13 W E3 E1 E E 1 0,10 mm .004 inch SEATING PLANE B e 48 IG A A2 Inches Typ. 0.055 0.009 0.354 0.276 0.216 0.0197 0.354 0.276 0.216 0.024 0.039 Max. 0.063 0.006 0.057 0.011 0.008 0.030 0 (min.), 7 (max.) Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. © The ST logo is a registered trademark of STMicroelectronics © 2002 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States © http://www.st.com 20/20