TCM3105DWL, TCM3105JE, TCM3105JL TCM3105NE, TCM3105NL FSK MODEM SCTS019C – NOVEMBER 1985 – REVISED MAY 1994 • • • • • • • • • • • J OR N PACKAGE (TOP VIEW) Single-Chip Frequency-Shift-Keying (FSK) Modem Meet Both Bell 202 and CCITT V23 Specifications Transmit Modulation at 75, 150, 600, and 1200 Baud Receive Demodulation at 5, 75, 150, 600, and 1200 Baud Half-Duplex Operation Up to 1200 Baud Transmit and Receive Full-Duplex Operation Up to 1200 Baud Transmit and 150 Baud Receive On-Chip Group Equalization and Transmit/Receive Filtering Carrier-Detect-Level Adjustment and Carrier-Fail Output Single 5-V Power Supply Low Power Consumption Reliable CMOS Silicon-Gate Technology VDD CLK CDT RXA TRS NC RXB RXD 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 OSC2 OSC1 TXD TXR1 TXR2 TXA CDL VCC DW PACKAGE (TOP VIEW) VDD CLK CDT NC RXA NC TRS NC RXT NC RXB RXD description The TCM3105 is a single-chip asynchronous frequency-shift-keying (FSK) voice-band modem that uses silicon-gate CMOS technology to implement a switched-capacitor architecture. It is pin selectable (TXR1, TXR2, and TRS) for a wide range of transmit /receive baud rates and is compatible with the applicable BELL 202 or CCITT V23 standards. Operation is fully reversible, thereby allowing both forward and backward channels to be used simultaneously. 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 OSC2 OSC1 TXD NC TXR1 NC NC TXR2 TXA NC CDL VSS NC – No internal connection D package are available taped and reeled. Add the R suffix to device type (e.g., YCM3105DWLR). The transmitter is a programmable frequency synthesizer that provides two output frequencies (on TXA), representing the marks and spaces of the digital signal present on TXD. The receive section is responsible for the demodulation of the analog signal appearing at the RXA input and is based on the principle of frequency-to-voltage conversion. This section contains a group delay equalizer (to correct phase distortion), automatic gain control, carrier-detect-level adjustment, and bias-distortion adjustment, thereby optimizing performance and giving the lowest possible bit error rate. Carrier-detect information is given to the system by means of the carrier-detect circuits, which set a flag on the CDT output if the level of received in-band energy falls below a value set on the CDL input for a specified minimum duration. The TCM3105JE and TCM3105NE are characterized for operation from – 40°C to 85°C.The TCM3105DWL, TCM3105JL, and TCM3105NL are characterized for operation from 0°C to 70°C. Caution. These devices have limited built-in protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Copyright 1994, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. • DALLAS, TEXAS 75265 • HOUSTON, TEXAS 77251–1443 POST OFFICE BOX 655303 POST OFFICE BOX 1443 1 TCM3105DWL, TCM3105JE, TCM3105JL TCM3105NE, TCM3105NL FSK MODEM SCTS019C – NOVEMBER 1985 – REVISED MAY 1994 Terminal Functions TERMINAL NAME NO. DESCRIPTION DW J OR N CDL 14 10 CDT 3 3 Carrier-detect output. A low-level output indicates carrier failure CLK 2 2 Output for a continuous clock signal at 16 times the highest selected (transmit or receive) bit rate NC 4, 6, 8, 10, 15, 18, 19, 21 6 No internal connection OSC1, OSC2 23, 24 15, 16 Carrier-detect-level adjust for external adjustment of carrier-detect threshold Oscillator connections. The crystal (typically 4.4336 MHz) is connected to OSC1 AND OSC2. If an external clock is used, OSC2 is left open and the clock is connected to OSC1. RXA 5 4 Receive analog input to which the received line signal must be ac coupled RXB 11 7 Receive bias adjust for external adjustment of the decision threshold of the comparator to minimize bias distortion RXD 12 8 Receiver digital output for the demodulated received data in positive logic. The high logic level is a mark and the low logic level is a space. RXT 9 – Receive test access. Output of limiter is available on RXT. (DW only) TRS 7 5 Transmit /receive standard select input, which with TXR1 and TXR2, sets the standard bit rates and mark/space frequencies TXA 16 11 Transmit analog output for the modulation signal, which must be ac coupled TXD 22 14 Transmit digital input for data to the transmitter in positive logic. The high logic level is a mark, and the low logic level is a space. The data can be accepted at any speed from zero to the selected speed and may be totally asynchronous. TXR1 20 13 Bit-rate select 1 input which along with TXR2 and TRS, sets the bit rates and mark/space frequencies TXR2 17 12 Bit rate select 2 input, which along with TXR1 and TRS, sets the bit rates and mark/space frequencies VDD VSS 1 1 Positive supply voltage 13 9 Most negative supply voltage (normally ground); connected to substrate 2 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 • TCM3105DWL, TCM3105JE, TCM3105JL TCM3105NE, TCM3105NL FSK MODEM SCTS019C – NOVEMBER 1985 – REVISED MAY 1994 functional block diagram Transmit Digital Input Receive Bias Adjust Receive Analog Input FSK Modulator TXD Digitalto-Analog Converter XMT Filter Low-Pass Filter Transmit TXA Analog Output Comparator Receive RXD Digital Output RXB Low-Pass Filter RXA Automatic Gain Control Receive Filter and Group Delay Equalizer Comparator Offset Compensation Carrier Detector Carrier-Detect Level Adjust FSK Demodulator DW Package Only Receive RXT Test Access CarrierDetect Delay CarrierCDT Detect Output Timing and Control CLK Clock CDL Oscillator Connection OSC1 Bit-Rate Select TXE1 4.4336-MHz Oscillator OSC2 Transmit/Receive Standard Select TXE2 TRS timing diagram RXA Input (amplitude of received signal) Off/On Threshold On/Off Threshold t CDT Output td(on-off) td(off-on) t • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 • 3 TCM3105DWL, TCM3105JE, TCM3105JL TCM3105NE, TCM3105NL FSK MODEM SCTS019C – NOVEMBER 1985 – REVISED MAY 1994 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 10 V Input voltage range, VI (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VDD Operating free-air temperature range, TA: TCM3105DWL, TCM3105JL,TCM3105NL . . . . . . – 10°C to 70°C TCM3105JE, TCM3105NE . . . . . . . . . . . . . . . . . . . . – 55°C to 85°C Storage temperature range: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: DW or N package . . . . . . . . . . . . . . . 260°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: J package . . . . . . . . . . . . . . . . . . . . . 300°C NOTE 1: Voltage values are with respect to VSS. recommended operating conditions TCM3105DWL TCM3105JL TCM3105NL TCM3105JE TCM3105NE UNIT MIN NOM MAX MIN NOM MAX Supply voltage, VDD 4 5 5.5 4 5 5.5 V High-level input voltage, VIH 2 VDD 0.8 V 0 VDD 0.8 2 Low-level input voltage, VIL 0.3 0.78 V 4.4336 4.4338 Analog input level, peak to peak (ac coupled) Clock frequency, fclock 4.4334 Analog load impedance at TXA 0.78 4.4336 4.4338 50 Operating free-air temperature range, TA 4 0.3 – 40 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 • 0 4.4334 50 85 0 V MHz kΩ 70 °C TCM3105DWL, TCM3105JE, TCM3105JL TCM3105NE, TCM3105NL FSK MODEM SCTS019C – NOVEMBER 1985 – REVISED MAY 1994 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS TCM3105JE TCM3105NE MIN VOH High-level output voltage RXD, CDT, CLK IOH = – 100 µA VOL Low-level output voltage RXD, CDT, CLK IOL = 1.6 mA Analog output voltage level, peak to peak TXA VDD = 4 V VDD = 5 V VDD = 5.5 V Adjust voltage RXB Analog output dc offset TXA Digital input current TXD, TRS, TRX1, TRX2 Analog input current RXA Bias input current RXB, CDL MAX VDD 2.4 VDD V VSS 0.4 VSS 0.4 V 2.3 1.4 2.3 V 1.4 1.55 1.9 1.9 2.1 2.1 2.3 2.7 3.1 2.3 2.7 3.1 2.8 3.3 3.9 2.8 3.3 3.9 VDD/2 VDD/2 VI = 0 to VDD ±1 µA ± 15 ± 15 µA ± 150 µA 6 3 5 5 10 5 8 8 16 8 12 S pply current Supply VDD = 5 V VDD = 5.5 V Ci Input capacitance, all inputs f = 1 MHz 10 Co Output capacitance, all inputs f = 1 MHz 10 10 200 – 45.5 – 48 2.5 µs ± 15% – 43 – 45.5 – 45.5 – 48 2.8 pF 200 ± 15% Bias distortion‡ mA A pF 10 Phase jitter Carrier-detect hysteresis V 3 IDD V ±1 ± 150 VI = 3 V VDD = 4 V Carrier-detect threshold, off/on§ Carrier-detect threshold, on/off§ UNIT 2.4 1.55 kΩ RL = 50 kΩ, RL = 100 pF VDD = 5 V CDL TYP† TCM3105DWL TCM3105JL TCM3105NL MIN TYP† MAX 2.5 – 43 dBm – 45.5 dBm 2.8 dBm switching characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS TCM3105JE TCM3105NE MIN td(off d(off-on) on) Carrier-detect off-to-on delay time td(on d(on-off) off) Carrier detect on-to-off Carrier-detect on to off delay time Transmit frequency deviation from assignment (see Table 1) TYP† MAX TCM3105DWL TCM3105JL TCM3105NL MIN TYP† MAX RX = 600 or 1200 b/s 12 25 12 25 RX = 5, 75, or 150 b/s 48 80 48 80 RX = 600 or 1200 b/s 12 20 12 20 RX = 5, 75, or 150 b/s 48 75 48 75 fclock = 4.4336 MHz ±1 ±1 UNIT ms ms Hz † All typical are at VCC = 5 V, TA = 25°C. ‡ Bias distortion is the departure from a 50% duty cycle when a series of alternating mark and space tones is received. § This is the threshold with the CDL input properly adjusted. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 • 5 TCM3105DWL, TCM3105JE, TCM3105JL TCM3105NE, TCM3105NL FSK MODEM SCTS019C – NOVEMBER 1985 – REVISED MAY 1994 PRINCIPLES OF OPERATION The TCM3105 FSK modem is made up of four functional circuits. The circuits are the transmitter, the receiver, a carrier detector, and control and timing (see Figure 1). Bias Adjust RXB Analog Input RXA Level Adjust CDL TXR1, TXR2, TRS Master Clock (internal) Digital Input TXD Receiver RXD Digital Output Carrier Detector CDT Detect Output Timing and Control CLK Clock Output Transmitter TXA Analog Output Figure 1. TCM3105 System Partitioning transmitter The transmitter comprises a phase-coherent FSK modulator, a transmit filter, and a transmit amplifier. The modulator is a programmable frequency synthesizer that drives the output frequencies by variable division of the oscillator frequency (4.4336 MHz). The division ratio is set by the states of the transmit/receive standard input (TRS), the bit-rate select inputs (TXR1 and TXR2), and the digital data input (TXD). A switched-capacitor low-pass filter limits the harmonics and noise outside the transmit band, and the characteristics of this filter are set by the frequency-select inputs as previously described. The harmonics introduced by the transmit filter clock are removed by a continuous low-pass filter. The transmitter output level varies with power supply voltage and so must be compensated in the 2-wire to 4-wire converter to give a constant output level to the line. receiver A continuous low-pass antialiasing filter is followed by the receiver amplifier, which automatically controls the gain to give a constant output level from the receiver filter. The receiver filter limits the bandwidth of the signal presented to the demodulator reducing out-of-band interference and has very high rejection of the transmit channel frequencies. These are typically present at much higher levels than the received signal. The group delay equalizer is a switched-capacitor network that compensates the delay introduced by the receiver filter and the network. The output from the equalizer is then limited to give an FSK modulated squarewave that is presented to the demodulator. The demodulator is an edge-triggered multivibrator that triggers off positive- and negative-going edges. The output of the demodulator is a stream of constant-length pulses at a frequency that is double the frequency of the limited input signal. The dc component of this signal is proportional to the received frequency and is extracted by a switched-capacitor, low-pass, post-demodulator filter. The variation of dc level with received frequency is presented to a comparator that slices at a level externally fixed by the RXB bias-adjustment pin. This voltage depends on received bit rate and internal offsets. The comparator output is then the received data at RXD. 6 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 • TCM3105DWL, TCM3105JE, TCM3105JL TCM3105NE, TCM3105NL FSK MODEM SCTS019C – NOVEMBER 1985 – REVISED MAY 1994 carrier detect The carrier-detect circuits comprise an energy detector and digital delay. The energy detector compares the total signal level at the output of the receive filter to an externally set threshold level on the CDL input. The comparator has a 2.5-dB hysteresis and a delay to allow for momentary signal loss and to prevent oscillation. The output detector is available on CDT where a high level indicates that a carrier is present. The data output is clamped to a mark condition when the carrier-detect output switches off at the end of transmission. control and timing An on-chip oscillator runs from an external 4.4336-MHz crystal connected between OSC1 and OSC2 or an external signal driving OSC1. A clock signal equal to 16 times the highest selected bit rate (transmit or receive) is available on the CLK output. The single-supply rail means that all analog functions are referenced to an internally generated reference. All analog inputs and outputs must be ac coupled. transmit and receive modes The various modes of operation of the TCM3105 are given in Table 1. The data convention is that a logic high is a mark and a logic low is a space. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 • 7 TCM3105DWL, TCM3105JE, TCM3105JL TCM3105NE, TCM3105NL FSK MODEM SCTS019C – NOVEMBER 1985 – REVISED MAY 1994 Table 1. Modes of Operation STANDARD CCITT V.23 V 23 BELL 202 RECEIVED BAUD RATE TRANSMIT FREQUENCY ASSIGNMENTS (Hz) CLK FREQUENCY (kHz) TRS TXR1 TXR2 L L L 1200 1200 M S 1300 2100 M S 1300 2100 19.11 H L L 1200 75 M S 1300 2100 M S 390 450 19.11 L L H 600 75 M S 1300 1700 M S 390 450 9.56 H L H 600 600 M S 1300 1700 M S 1300 1700 9.56 L H L 75 1200 M S 390 450 M S 1300 2100 19.11 H H L 75 600 M S 390 450 M S 1300 1700 9.56 L H H 75 75 M S 390 450 M S 390 450 1.19 CLK L L 1200 1200 M S 1200 2200 M S 1200 2200 19.11 CLK/8 L H 1200 150 M S 1200 2200 M S 387 487 19.11 CLK/8 L H 1200 5 M S 1200 2200 M S 387 0 19.11 CLK H L 150 1200 M S 387 487 M S 1200 2200 19.11 CLK H H 150 150 M S 387 487 M S 387 487 2.39 CLK† H† H† H† L† H† 5 1200 M 387 S 0 M S 1200 2200 19 11 19.11 H H H Transmit Disabled M S 1200 2200 19.11 Transmit Disabled 1200 H = high level, L = low level † In these modes, the modulation is controlled by TRS and TXR2. TXD is tied high. 8 RECEIVE FREQUENCY ASSIGNMENTS (Hz) TRANSMITTED BAUD RATE • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 • TCM3105DWL, TCM3105JE, TCM3105JL TCM3105NE, TCM3105NL FSK MODEM SCTS019C – NOVEMBER 1985 – REVISED MAY 1994 APPLICATION INFORMATION VDD VDD 7 RXB 5 VDD, VSS, or CLK 11 Line Signaling Line Termination 10 CDL VDD TRS 1 TXA TXD 2-Wire to 4-Wire Converter 14 TCM3105 FSK MODEM 4 VDD UART RXD Microprocessor 8 RXA CLK TXR1 TXR2 CDT 2 13 12 3 OSC1 OSC2 VSS 15 16 9 Pin numbers shown are for the J and N packages. Figure 2. Typical System Configuration • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 • 9 TCM3105DWL, TCM3105JE, TCM3105JL TCM3105NE, TCM3105NL FSK MODEM SCTS019C – NOVEMBER 1985 – REVISED MAY 1994 APPLICATION INFORMATION 30 pF 30 pF 16 OSC1 Receive Data 8 Transmit Data 14 RXD 15 OSC2 RXB VDD 5V 100 kΩ Select Mode (bit rate and standard) 3 5 13 12 2 100 kΩ 1 ZT = 300 Ω 2 5V TX Gain Adj 0.1 µF 11 100 kΩ TRS 100 kΩ 250 kΩ + _U1A CDT + U1B _ TXR1 ZL ⇒ ZT = 300 Ω 2 100 kΩ ZT′ A R A TXR2 ZL′ CLK VSS RXA 9 4 A 50 kΩ RX Gain Adj A 100 kΩ 100 kΩ 0.1 µF 250 kΩ 100 kΩ + U1D_ + _ U1C 100 kΩ 5V A 47 kΩ 100 kΩ A 47 kΩ 10 µF U1 = LM124 Pin numbers shown are for the J and N packages. Figure 3. Telephone Line Interface Circuit 10 1:1 T CDL TXA Carrier Detect 7 TXD TCM3105 10 5V • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 • ZT ZT′ = ZL ZL′ TCM3105DWL, TCM3105JE, TCM3105JL TCM3105NE, TCM3105NL FSK MODEM SCTS019C – NOVEMBER 1985 – REVISED MAY 1994 APPLICATION INFORMATION 30 pF 30 pF 15 OSC1 5V 16 OSC2 TXA 7 100 kΩ ZL ⇒ 0.1 µF 11 + _U1A 100 kΩ RXB ZT = 600 Ω VDD 100 kΩ 10 1 5V ZL′ CDL Transmit Data Standard and Bit Rate Carrier Detect Clock 8 RXD 14 TXD 13 TXR1 12 TXR2 5 TRS 47 kΩ A RXA 0.1 µF 4 47 kΩ + U1B _ 10 µF 100 kΩ 3 CDT 2 5V A TCM3105 Receive Data R ZT′ A 5V T A 100 kΩ 100 kΩ ZT ZT′ = ZL ZL′ CLK VSS U1 = 1/2LM124 9 Figure 4. Simplified Telephone Line Interface Circuit • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 • 11 IMPORTANT NOTICE Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. TI warrants performance of its semiconductor products and related software to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. 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