TI SN74LVC86AD

SN54LVC86A, SN74LVC86A
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SCAS288I – JANUARY 1993 – REVISED OCTOBER 1998
D
D
D
D
D
D
EPIC  (Enhanced-Performance Implanted
CMOS) Submicron Process
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
> 2 V at VCC = 3.3 V, TA = 25°C
Inputs Accept Voltages to 5.5 V
Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), Thin Very Small-Outline (DGV), and
Thin Shrink Small-Outline (PW) Packages,
Ceramic Flat (W) Package, Ceramic Chip
Carriers (FK), and DIPs (J)
SN54LVC86A . . . J OR W PACKAGE
SN74LVC86A . . . D, DB, DGV, OR PW PACKAGE
(TOP VIEW)
1A
1B
1Y
2A
2B
2Y
GND
1
14
2
13
3
12
4
11
5
10
6
9
7
8
VCC
4B
4A
4Y
3B
3A
3Y
SN54LVC86A . . . FK PACKAGE
(TOP VIEW)
1B
1A
NC
VCC
4B
D
1Y
NC
2A
NC
2B
description
3
2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
4A
NC
4Y
NC
3B
2Y
GND
NC
3Y
3A
The
SN54LVC86A
quadruple
2-input
exclusive- OR gate is designed for 2.7-V to 3.6-V
VCC operation and the SN74LVC86A quadruple
2-input exclusive - OR gate is designed for 1.65-V
to 3.6-V VCC operation.
4
NC – No internal connection
The ’LVC86A devices perform the Boolean
function Y = A ⊕ B or Y = AB + AB in positive logic.
A common application is as a true/complement element. If one of the inputs is low, the other input is reproduced
in true form at the output. If one of the inputs is high, the signal on the other input is reproduced inverted at
the output.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
The SN54LVC86A is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74LVC86A is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each gate)
INPUTS
A
B
OUTPUT
Y
L
L
L
L
H
H
H
L
H
H
H
L
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright  1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
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1
SN54LVC86A, SN74LVC86A
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SCAS288I – JANUARY 1993 – REVISED OCTOBER 1998
logic symbol†
1A
1B
2A
2B
3A
3B
4A
4B
1
=1
3
2
4
6
5
1Y
2Y
9
8
10
3Y
12
11
13
4Y
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, DB, DGV, J, PW, and W packages.
exclusive-OR logic
An exclusive-OR gate has many applications, some of which can be represented better by alternative logic
symbols.
EXCLUSIVE OR
=1
These five equivalent exclusive-OR symbols are valid for an SN74LVC86A gate in positive logic; negation may be shown at any two ports.
LOGIC-IDENTITY ELEMENT
=
The output is active (low) if
all inputs stand at the same
logic level (i.e., A = B).
EVEN-PARITY ELEMENT
2k
The output is active (low) if
an even number of inputs
(i.e., 0 or 2) are active.
ODD-PARITY ELEMENT
2k + 1
The output is active (high) if
an odd number of inputs
(i.e., only 1 of the 2) are
active.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The value of VCC is provided in the recommended operating conditions table.
3. The package thermal impedance is calculated in accordance with JESD 51.
2
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SN54LVC86A, SN74LVC86A
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SCAS288I – JANUARY 1993 – REVISED OCTOBER 1998
recommended operating conditions (see Note 4)
SN54LVC86A
VCC
VIH
Supply voltage
High-level input voltage
Operating
Data retention only
VIL
VI
VO
IOH
Low-level input voltage
MAX
MIN
MAX
2
3.6
1.65
3.6
1.5
1.5
UNIT
V
0.65 × VCC
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 1.65 V to 1.95 V
SN74LVC86A
MIN
V
1.7
2
2
0.35 × VCC
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
0.7
0.8
V
0.8
Input voltage
0
5.5
0
5.5
V
Output voltage
0
VCC
0
VCC
–4
V
High level output current
High-level
IOL
Low level output current
Low-level
∆t/∆v
Input transition rise or fall rate
VCC = 1.65 V
VCC = 2.3 V
–8
VCC = 2.7 V
VCC = 3 V
–12
–12
–24
–24
VCC = 1.65 V
VCC = 2.3 V
mA
4
8
VCC = 2.7 V
VCC = 3 V
12
12
24
0
9
mA
24
0
9
ns/V
TA
Operating free-air temperature
–55
125
–40
85
°C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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SN54LVC86A, SN74LVC86A
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SCAS288I – JANUARY 1993 – REVISED OCTOBER 1998
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
2.7 V to 3.6 V
IOH = –4 mA
IOH = –8 mA
1.2
V
1.7
2.7 V
2.2
2.2
3V
2.4
2.4
3V
2.2
2.2
0.2
2.7 V to 3.6 V
0.2
IOL = 4 mA
IOL = 8 mA
1.65 V
0.45
2.3 V
0.7
IOL = 12 mA
IOL = 24 mA
2.7 V
0.4
0.4
VI = 5.5 V or GND
VI = VCC or GND,
∆ICC
VCC–0.2
1.65 V to 3.6 V
IOL = 100 µA
IO = 0
One input at VCC – 0.6 V,
Other inputs at VCC or GND
V
3V
0.55
0.55
3.6 V
±5
±5
µA
3.6 V
10
10
µA
500
500
µA
2.7 V to 3.6 V
Ci
VI = VCC or GND
† All typical values are at VCC = 3.3 V, TA = 25°C.
UNIT
VCC–0.2
2.3 V
IOH = –24 mA
II
ICC
SN74LVC86A
TYP†
MAX
MIN
1.65 V
IOH = –12
12 mA
VOL
MIN
1.65 V to 3.6 V
IOH = –100
100 µA
VOH
SN54LVC86A
TYP†
MAX
VCC
3.3 V
5
5
pF
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 3)
SN54LVC86A
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
A
Y
VCC = 2.7 V
MIN
VCC = 3.3 V
± 0.3 V
MAX
MIN
MAX
5.6
1
4.6
UNIT
ns
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 through 3)
SN74LVC86A
PARAMETER
tpd
FROM
(INPUT)
TO
(OUTPUT)
A
Y
VCC = 1.8 V
VCC = 2.5 V
± 0.2 V
TYP
MIN
MAX
13.6
1
7.6
VCC = 2.7 V
MIN
VCC = 3.3 V
± 0.3 V
UNIT
MAX
MIN
MAX
5.6
1
4.6
ns
1
ns
tsk(o)‡
‡ Skew between any two outputs of the same package switching in the same direction
operating characteristics, TA = 25°C
Cpd
4
PARAMETER
TEST
CONDITIONS
Power dissipation capacitance per gate
f = 10 MHz
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VCC = 1.8 V
TYP
• DALLAS, TEXAS 75265
6.5
VCC = 2.5 V
TYP
7.5
VCC = 3.3 V
TYP
8.5
UNIT
pF
SN54LVC86A, SN74LVC86A
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SCAS288I – JANUARY 1993 – REVISED OCTOBER 1998
PARAMETER MEASUREMENT INFORMATION
VCC = 1.8 V ± 0.15 V
2 × VCC
S1
1 kΩ
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
1 kΩ
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
Open
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
VCC/2
VOL
Output
Waveform 2
S1 at Open
(see Note B)
VOL + 0.15 V
VOL
tPHZ
tPZH
VOH
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
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SN54LVC86A, SN74LVC86A
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SCAS288I – JANUARY 1993 – REVISED OCTOBER 1998
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V ± 0.2 V
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
VCC/2
VOL
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
tPZH
VOH
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54LVC86A, SN74LVC86A
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SCAS288I – JANUARY 1993 – REVISED OCTOBER 1998
PARAMETER MEASUREMENT INFORMATION
VCC = 2.7 V AND 3.3 V ± 0.3 V
6V
S1
500 Ω
From Output
Under Test
GND
CL = 50 pF
(see Note A)
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
6V
GND
Open
500 Ω
tw
LOAD CIRCUIT
2.7 V
2.7 V
Timing
Input
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
th
2.7 V
Data
Input
1.5 V
1.5 V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V
Output
Control
(low-level
enabling)
2.7 V
1.5 V
1.5 V
0V
tPLH
VOH
1.5 V
Output
Waveform 1
S1 at 6 V
(see Note B)
1.5 V
VOL
tPLZ
3V
1.5 V
tPZH
tPHL
1.5 V
0V
tPZL
2.7 V
Output
Input
1.5 V
1.5 V
tsu
Input
1.5 V
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
1.5 V
VOH
VOH – 0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms
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