FREESCALE MC68HC705K1P

Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
MC68HC705K1/D
Rev. 2.0
HC 5
MC68HC705K1
HCMOS Microcontroller Unit
TECHNICAL DATA
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Technical Data
Technical Data
MC68HC705K1 — Rev. 2.0
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Technical Data — MC68HC705K1
List of Sections
Section 1. General Description . . . . . . . . . . . . . . . . . . . . 15
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Section 2. Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Section 3. Central Processor Unit (CPU) . . . . . . . . . . . . 31
Section 4. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Section 5. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Section 6. Low-Power Modes. . . . . . . . . . . . . . . . . . . . . . 57
Section 7. Parallel Input/Output (I/O). . . . . . . . . . . . . . . . 63
Section 8. Multifunction Timer . . . . . . . . . . . . . . . . . . . . . 75
Section 9. EPROM/OTPROM . . . . . . . . . . . . . . . . . . . . . . 83
Section 10. Personality EPROM (PEPROM) . . . . . . . . . . 91
Section 11. Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . 99
Section 12. Electrical Specifications . . . . . . . . . . . . . . . 117
Section 13. Mechanical Specifications . . . . . . . . . . . . . 133
Section 13. Ordering Information . . . . . . . . . . . . . . . . . 137
MC68HC705K1 — Rev. 2.0
Technical Data
List of Sections
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List of Sections
Technical Data
MC68HC705K1 — Rev. 2.0
List of Sections
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Technical Data — MC68HC705K1
Table of Contents
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Section 1. General Description
1.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
1.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
1.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
1.4
Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
1.5
MCU Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
1.6
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
1.6.1
VDD and VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
1.6.2
OSC1 and OSC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
1.6.2.1
Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
1.6.2.2
Ceramic Resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
1.6.2.3
2-Pin RC Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
1.6.2.4
3-Pin RC Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
1.6.2.5
External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
1.6.3
RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
1.6.4
IRQ/VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
1.6.5
PA7–PA0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
1.6.6
PB1/OSC3 and PB0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Section 2. Memory
2.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
2.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
2.3
Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
2.4
Input/Output Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
2.5
Random-Access Memory (RAM) . . . . . . . . . . . . . . . . . . . . . . .26
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2.6
EPROM/OTPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
2.7
Personality EPROM/OTPROM . . . . . . . . . . . . . . . . . . . . . . . . .30
Section 3. Central Processor Unit (CPU)
3.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
3.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
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3.3
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
3.3.1
Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
3.3.2
Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
3.3.3
Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
3.3.4
Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
3.3.5
Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . .36
3.4
Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Section 4. Interrupts
4.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
4.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
4.3
Interrupt Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
4.3.1
Software Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
4.3.2
External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
4.3.2.1
IRQ/VPP Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
4.3.2.2
PA3–PA0 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
4.3.2.3
IRQ Status and Control Register . . . . . . . . . . . . . . . . . . .45
4.3.3
Timer Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
4.3.3.1
Timer Overflow Interrupt . . . . . . . . . . . . . . . . . . . . . . . . .46
4.3.3.2
Real-Time Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
4.4
Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Section 5. Resets
5.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
5.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
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5.3
Reset Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
5.3.1
Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
5.3.2
External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
5.3.3
Computer Operating Properly (COP) Reset . . . . . . . . . . . . .54
5.3.4
Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
5.3.5
Low-Voltage Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
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5.4
Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
5.4.1
CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
5.4.2
I/O Port Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
5.4.3
Multifunction Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
5.4.4
COP Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Section 6. Low-Power Modes
6.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
6.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
6.3
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
6.4
Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
6.5
Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
6.6
Data-Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Section 7. Parallel Input/Output (I/O)
7.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
7.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
7.3
I/O Port Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
7.4
Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
7.4.1
Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
7.4.2
Data Direction Register A. . . . . . . . . . . . . . . . . . . . . . . . . . .65
7.4.3
Pulldown Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
7.4.4
Port A External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . .67
7.4.5
Port A Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
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7.5
Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
7.5.1
Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
7.5.2
Data Direction Register B. . . . . . . . . . . . . . . . . . . . . . . . . . .70
7.5.3
Pulldown Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
7.5.4
Port B Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
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Section 8. Multifunction Timer
8.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
8.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
8.3
Timer Status and Control Register . . . . . . . . . . . . . . . . . . . . . .77
8.4
Timer Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
8.5
COP Watchdog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
Section 9. EPROM/OTPROM
9.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
9.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
9.3
EPROM Programming Register . . . . . . . . . . . . . . . . . . . . . . . .84
9.4
EPROM/OTPROM Programming . . . . . . . . . . . . . . . . . . . . . . .85
9.5
EPROM Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
9.6
Mask Option Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Section 10. Personality EPROM (PEPROM)
10.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
10.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
10.3 PEPROM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
10.3.1 PEPROM Bit Select Register . . . . . . . . . . . . . . . . . . . . . . . .93
10.3.2 PEPROM Status and Control Register. . . . . . . . . . . . . . . . .95
10.4
PEPROM Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
10.5
PEPROM Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
10.6
PEPROM Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
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Section 11. Instruction Set
11.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
11.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
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11.3 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
11.3.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
11.3.2 Immediate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
11.3.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
11.3.4 Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
11.3.5 Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
11.3.6 Indexed, 8-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
11.3.7 Indexed, 16-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
11.3.8 Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
11.4 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
11.4.1 Register/Memory Instructions. . . . . . . . . . . . . . . . . . . . . . .104
11.4.2 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . .105
11.4.3 Jump/Branch Instructions. . . . . . . . . . . . . . . . . . . . . . . . . .106
11.4.4 Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . .108
11.4.5 Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
11.5
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
11.6
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
Section 12. Electrical Specifications
12.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
12.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
12.3
Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
12.4
Operating Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .118
12.5
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
12.6
Power Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
12.7
Equivalent Pin Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
12.8
5.0-Volt DC Electrical Characteristics. . . . . . . . . . . . . . . . . . .121
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12.9
3.3-Volt DC Electrical Characteristics. . . . . . . . . . . . . . . . . . .122
12.10 5.0-Volt Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
12.11 3.3-Volt Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
12.12 Typical Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . .130
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Section 13. Mechanical Specifications
13.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
13.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
13.3
Plastic Dual In-Line Package (Case 648) . . . . . . . . . . . . . . . .134
13.4
Small Outline Integrated Circuit (Case 751) . . . . . . . . . . . . . .134
13.5
Ceramic Dual In-Line Package (Case 620) . . . . . . . . . . . . . .135
Section 13. Ordering Information
13.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
13.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
13.3
MCU Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
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List of Figures
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Figure
Title
Page
1-1
1-2
1-3
1-4
1-5
1-6
1-7
1-8
1-9
MC68HC705K1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . .18
Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Bypassing Layout Recommendation . . . . . . . . . . . . . . . . . . .19
Crystal Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
2-Pin Ceramic Resonator Connections . . . . . . . . . . . . . . . . .21
3-Pin Ceramic Resonator Connections . . . . . . . . . . . . . . . . .22
2-Pin RC Oscillator Connections . . . . . . . . . . . . . . . . . . . . . .22
3-Pin RC Oscillator Connections . . . . . . . . . . . . . . . . . . . . . .23
External Clock Connections . . . . . . . . . . . . . . . . . . . . . . . . . .24
2-1
2-2
Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
3-1
3-2
3-3
3-4
3-5
3-6
Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Index Register (X). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . . .36
4-1
4-2
4-3
4-4
External Interrupt Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
IRQ Status and Control Register (ISCR) . . . . . . . . . . . . . . . .45
Interrupt Stacking Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Interrupt Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
5-1
5-2
Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
COP Register (COPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
6-1
Stop/Wait/Halt Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
MC68HC705K1 — Rev. 2.0
Technical Data
List of Figures
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List of Figures
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Figure
Title
Page
7-1
7-2
7-3
7-4
7-5
7-6
7-7
7-8
Port A Data Register (PORTA). . . . . . . . . . . . . . . . . . . . . . . .64
Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . . . .65
Pulldown Register A (PDRA) . . . . . . . . . . . . . . . . . . . . . . . . .66
Port A I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Port B Data Register (PORTB). . . . . . . . . . . . . . . . . . . . . . . .69
Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . . .70
Pulldown Register B (PDRB) . . . . . . . . . . . . . . . . . . . . . . . . .71
Port B I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
8-1
8-2
8-3
8-4
Multifunction Timer Block Diagram. . . . . . . . . . . . . . . . . . . . .76
Timer Status and Control Register (TSCR) . . . . . . . . . . . . . .77
Timer Counter Register (TCNTR). . . . . . . . . . . . . . . . . . . . . .79
COP Register (COPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
9-1
9-2
9-3
EPROM Programming Register (EPROG) . . . . . . . . . . . . . . .84
Programming Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Mask Option Register (MOR) . . . . . . . . . . . . . . . . . . . . . . . . .87
10-1
10-2
10-3
Personality EPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
PEPROM Bit Select Register (PEBSR) . . . . . . . . . . . . . . . . .93
PEPROM Status and Control Register (PESCR) . . . . . . . . . .95
12-1
12-2
12-3
12-4
12-5
12-6
12-7
12-8
12-9
12-10
12-11
12-12
12-13
12-14
Equivalent Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
Typical High-Side Driver Characteristics . . . . . . . . . . . . . . .123
Typical Low-Side Driver Characteristics. . . . . . . . . . . . . . . .123
Run IDD versus Internal Clock Frequency . . . . . . . . . . . . . .124
Wait IDD versus Internal Clock Frequency . . . . . . . . . . . . . .124
Stop IDD versus Temperature. . . . . . . . . . . . . . . . . . . . . . . .125
External Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . .128
Stop Mode Recovery Timing . . . . . . . . . . . . . . . . . . . . . . . .128
Power-On Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
2-Pin RC Oscillator R versus Frequency (VDD = 5.0 V) . . . .131
3-Pin RC Oscillator R versus Frequency (VDD = 5.0 V) . . . .131
2-Pin Oscillator R versus Frequency (VDD = 3.0 V) . . . . . . .132
3-Pin Oscillator R versus Frequency (VDD = 3.0 V) . . . . . . .132
Technical Data
MC68HC705K1 — Rev. 2.0
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List of Tables
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Table
Title
Page
4-1
Reset/Interrupt Vector Addresses . . . . . . . . . . . . . . . . . . . . .48
7-1
7-2
7-3
Port A Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
PB0 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
PB1/OSC3 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
8-1
8-2
Real-Time Interrupt Rate Selection . . . . . . . . . . . . . . . . . . . .78
COP Watchdog Recommendations . . . . . . . . . . . . . . . . . . . .81
10-1
PEPROM Bit Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
11-1
11-2
11-3
11-4
11-5
11-6
11-7
Register/Memory Instructions. . . . . . . . . . . . . . . . . . . . . . . .104
Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . .105
Jump and Branch Instructions . . . . . . . . . . . . . . . . . . . . . . .107
Bit Manipulation Instructions. . . . . . . . . . . . . . . . . . . . . . . . .108
Control Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .110
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
13-1
MC68HC705K1 Order Numbers. . . . . . . . . . . . . . . . . . . . . .137
MC68HC705K1 — Rev. 2.0
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List of Tables
Technical Data
MC68HC705K1 — Rev. 2.0
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Technical Data — MC68HC705K1
Section 1. General Description
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1.1 Contents
1.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
1.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
1.4
Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
1.5
MCU Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
1.6
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
1.6.1
VDD and VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
1.6.2
OSC1 and OSC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
1.6.2.1
Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
1.6.2.2
Ceramic Resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
1.6.2.3
2-Pin RC Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
1.6.2.4
3-Pin RC Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
1.6.2.5
External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
1.6.3
RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
1.6.4
IRQ/VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
1.6.5
PA7–PA0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
1.6.6
PB1/OSC3 and PB0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
1.2 Introduction
The MC68HC705K1 is a member of the low-cost, high-performance
M68HC05 Family of 8-bit microcontroller units (MCU). The M68HC05
Family is based on the customer-specified integrated circuit (CSIC)
design strategy. All MCUs in the family use the popular M68HC05
central processor unit (CPU) and are available with a variety of
subsystems, memory sizes and types, and package types.
MC68HC705K1 — Rev. 2.0
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On-chip memory of the MC68HC705K1 includes 504 bytes of erasable,
programmable read-only memory (EPROM). In packages without the
transparent window for EPROM erasure, the 504 EPROM bytes serve
as one-time programmable read-only memory (OTPROM).
1.3 Features
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Features of the MCU include:
•
Popular M68HC05 CPU
•
Memory-mapped input/output (I/O) registers
•
504 bytes of EPROM/OTPROM, including eight user vector
locations
•
32 bytes of user random-access memory (RAM)
•
64-bit personality EPROM
•
10 bidirectional I/O pins with these features:
– Software programmable pulldown devices
– Four I/O pins with 8-mA current sinking capability
– Four I/O pins with maskable external interrupt capability
•
Hardware mask and flag for external interrupts
•
Fully static operation with no minimum clock speed
•
On-chip oscillator with connections for:
– Crystal or ceramic resonator
– Mask-optional 2-pin or 3-pin resistor-capacitor (RC) oscillator
•
Computer operating properly (COP) watchdog
•
15-bit multifunction timer with real-time interrupt circuit
•
Power-saving stop, wait, halt, and data-retention modes
•
8 × 8 unsigned multiply instruction
•
Illegal address reset
•
Low-voltage reset
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General Description
Mask Options
•
16-pin plastic dual in-line package (PDIP)
•
16-pin small outline integrated circuit package (SOIC)
•
16-pin ceramic DIP (cerdip)
1.4 Mask Options
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These MC68HC705K1 options are programmable in the mask option
register (MOR):
•
Enabled or disabled COP watchdog
•
Edge-triggered or edge- and level-triggered external interrupt pins
•
Enabled or disabled port A external interrupt function
•
Enabled or disabled low-voltage reset function
•
Enabled or disabled STOP instruction
•
Oscillator driven by crystal or ceramic resonator or oscillator
driven by RC circuit
•
2-pin RC-driven oscillator or 3-pin RC-driven oscillator
•
Enabled or disabled port A and port B programmable pulldown
devices
The mask option register is an EPROM/OTPROM byte at location
$0017. Section 9. EPROM/OTPROM describes the mask option
register and the EPROM/OTPROM programming procedure.
1.5 MCU Structure
Figure 1-1 shows the structure of the MC68HC705K1 MCU.
MC68HC705K1 — Rev. 2.0
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USER EPROM/OTPROM
504 BYTES
MASK OPTION REGISTER
EPROM/OTPROM
PERSONALITY EPROM/OTPROM
64 BITS
IRQ/VPP
ARITHMETIC/LOGIC
UNIT
CPU CONTROL
PA6*
PA5*
PA4*
PA3**
PA2**
PA1**
PA0**
*8-mA sink capability
**External interrupt capability
M68HC05
MCU
RESET
INDEX REGISTER
STACK POINTER
0 0 0 0 0 0 0 0 1 1 1
PROGRAM COUNTER
0 0 0 0 0 0
CONDITION CODE REGISTER
1 1 1 H I N C Z
PB0
TIMER
CLOCK
LOW-VOLTAGE
DETECT
PB1/OSC3
MULTIFUNCTION
TIMER
COP WATCHDOG
AND
ILLEGAL ADDRESS
DETECT
VDD
PORT B
RESET
DATA DIRECTION REGISTER B
ACCUMULATOR
CPU
CLOCK
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USER RAM
32 BYTES
PORT A
DATA DIRECTION REGISTER A
PA7*
VSS
OSC1
OSC2
INTERNAL
OSCILLATOR
DIVIDE
BY TWO
Figure 1-1. MC68HC705K1 Block Diagram
Technical Data
MC68HC705K1 — Rev. 2.0
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General Description
Pin Assignments
1.6 Pin Assignments
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Figure 1-2 shows the MC68HC705K1 pin assignments.
RESET
1
16
OSC1
PB1/OSC3
2
15
OSC2
PB0
3
14
VSS
IRQ/VPP
4
13
VDD
PA0
5
12
PA7
PA1
6
11
PA6
PA2
7
10
PA5
PA3
8
9
PA4
Figure 1-2. Pin Assignments
1.6.1 VDD and VSS
VDD and VSS are the power supply and ground pins. The MCU operates
from a single 5-volt power supply.
Very fast signal transitions occur on the MCU pins, placing high
short-duration current demands on the power supply. To prevent noise
problems, take special care to provide good power supply bypassing at
the MCU. Place bypass capacitors as close to the MCU as possible, as
Figure 1-3 shows.
V+
OSC1
VDD
OSC2
+
MCU
C1
C2
VSS
C1 C2
VSS
VDD
Figure 1-3. Bypassing Layout Recommendation
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1.6.2 OSC1 and OSC2
•
Crystal
•
Ceramic resonator
•
Resistor-capacitor network
•
External clock signal
The frequency of the internal oscillator is fOSC. The MCU divides the
internal oscillator output by two to produce the internal clock with a
frequency of fOP.
1.6.2.1 Crystal
The circuit in Figure 1-4 shows a typical crystal oscillator circuit for an
AT-cut, parallel resonant crystal. Follow the crystal supplier’s
recommendations, as the crystal parameters determine the external
component values required to provide reliable start-up and maximum
stability. The load capacitance values used in the oscillator circuit design
should include all stray layout capacitances. To minimize output
distortion, mount the crystal and capacitors as close as possible to
the pins.
VSS
C3
MCU
2 MΩ
OSC1
XTAL
OSC2
OSC1
OSC2
C4
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The OSC1, OSC2, and PB1/OSC3 pins are the control connections for
the 2-pin or 3-pin on-chip oscillator. The oscillator can be driven by any
of these:
VSS
XTAL
C3
27 pF
C4
27 pF
C1 C2
VDD
Figure 1-4. Crystal Connections
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General Description
Pin Assignments
NOTE:
Use an AT-cut crystal and not a strip or tuning fork crystal. The MCU may
overdrive or have the wrong characteristic impedance for a strip or
tuning fork crystal.
1.6.2.2 Ceramic Resonator
To reduce cost, use a ceramic resonator in place of the crystal. Use the
circuit in Figure 1-5 for a 2-pin ceramic resonator or Figure 1-6 for a
3-pin ceramic resonator, and follow the resonator manufacturer’s
recommendations. The resonator parameters determine the external
component values required for maximum stability and reliable starting.
The load capacitance values used in the oscillator circuit design should
include all stray layout capacitances. To minimize output distortion,
mount the resonator and capacitors as close as possible to the pins.
VSS
C3
MCU
2 MΩ
OSC1
CER.
RES.
OSC2
OSC1
OSC2
C4
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To use the crystal-driven oscillator, the RC and PIN3 bits in the mask
option register must be clear. See 9.6 Mask Option Register. Clearing
the RC bit connects an internal 2-MΩ startup resistor between OSC1
and OSC2.
C3
27 pF
CERAMIC
RESONATOR
VSS
C4
27 pF
C1 C2
VDD
Figure 1-5. 2-Pin Ceramic Resonator Connections
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VSS
MCU
2 MΩ
OSC2
OSC1
OSC1
CER.
RES.
OSC2
VSS
C1 C2
VDD
Figure 1-6. 3-Pin Ceramic Resonator Connections
To use the resonator-driven oscillator, the RC bit in the mask option
register must be clear. See 9.6 Mask Option Register. Clearing the RC
bit connects an internal 2-MΩ startup resistor between OSC1 and
OSC2.
1.6.2.3 2-Pin RC Oscillator
For maximum cost reduction, use the 2-pin RC oscillator configuration
shown in Figure 1-7. The OSC2 signal is a square wave, and the signal
on OSC1 is a triangular wave. The optimum frequency for the 2-pin
oscillator configuration is 2 MHz.
VSS
MCU
R
OSC2
OSC1
OSC1
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CERAMIC
RESONATOR
C3
R C3
OSC2
VSS
C1 C2
VDD
Figure 1-7. 2-Pin RC Oscillator Connections
To use the 2-pin RC oscillator configuration, the RC bit in the mask
option register must be programmed to a logic 1. Setting the RC bit
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General Description
Pin Assignments
disconnects the internal startup resistor. The PIN3 bit in the mask option
register must remain erased (logic 0). The PIN3 bit selects the 3-pin RC
oscillator configuration. See 9.6 Mask Option Register.
Another low-cost option is the 3-pin RC oscillator configuration shown in
Figure 1-8. The 3-pin oscillator is more stable than the 2-pin oscillator.
The OSC2 and PB1/OSC3 signals are square waves, and the signal on
OSC1 is a triangular wave. The 3-pin RC oscillator configuration is
recommended for frequencies of 1 MHz and less.
VSS
C3
MCU
R
R
PB1/OSC3
OSC2
OSC1
OSC1
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1.6.2.4 3-Pin RC Oscillator
+
PB1/OSC3
C3
OSC2
VSS
C1 C2
VDD
Figure 1-8. 3-Pin RC Oscillator Connections
To use the 3-pin RC oscillator configuration, both the RC and PIN3 bits
in the mask option register must be programmed to logic 1s. See
9.6 Mask Option Register.
NOTE:
In 3-pin RC oscillator configurations, the personality EPROM
(PEPROM) cannot be programmed by user software. If the voltage on
IRQ/VPP is raised above VDD, the oscillator will revert to a 2-pin oscillator
configuration and device operation will be disrupted.
1.6.2.5 External Clock
An external clock from another CMOS-compatible device can drive the
OSC1 input, with the OSC2 pin unconnected, as Figure 1-9 shows.
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OSC2
OSC1
MCU
EXTERNAL
CMOS CLOCK
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Figure 1-9. External Clock Connections
1.6.3 RESET
A logic 0 on the RESET pin forces the MCU to a known startup state.
See 5.3.2 External Reset for more information.
1.6.4 IRQ/VPP
The IRQ/VPP pin has these functions:
•
Applying asynchronous external interrupt signals,
see 4.3.2 External Interrupts
•
Applying the EPROM/OTPROM programming voltage,
see 9.4 EPROM/OTPROM Programming
1.6.5 PA7–PA0
PA7–PA0 are the pins of port A, a general-purpose, bidirectional I/O
port. See 7.4 Port A.
1.6.6 PB1/OSC3 and PB0
PB1/OSC3 and PB0 are the pins of port B, a general-purpose,
bidirectional I/O port. See 7.5 Port B.
Technical Data
MC68HC705K1 — Rev. 2.0
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Section 2. Memory
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2.1 Contents
2.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
2.3
Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
2.4
Input/Output Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
2.5
Random-Access Memory (RAM) . . . . . . . . . . . . . . . . . . . . . . .26
2.6
EPROM/OTPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
2.7
Personality EPROM/OTPROM . . . . . . . . . . . . . . . . . . . . . . . . .30
2.2 Introduction
This section describes the organization of the on-chip memory.
2.3 Memory Map
The central processor unit (CPU) can address 1 Kbyte of memory space.
The program counter typically advances one address at a time through
the memory, reading the program instructions and data. The erasable,
programmable read-only memory (EPROM) portion of memory holds
the program instructions, fixed data, user-defined vectors, and interrupt
service routines. The random-access memory (RAM) portion of memory
holds variable data. Input/output (I/O) registers are memory-mapped so
that the CPU can access their locations in the same way that it accesses
all other memory locations.
Figure 2-1 is a memory map of the microcontroller unit (MCU). Refer to
Figure 2-2 for a more detailed memory map of the 32-byte I/O register
section.
MC68HC705K1 — Rev. 2.0
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Memory
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Memory
2.4 Input/Output Section
The first 32 addresses of the memory space, $0001–$001F, are the I/O
section. These are the addresses of the I/O control registers, status
registers, and data registers. See Figure 2-2.
2.5 Random-Access Memory (RAM)
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The 32 addresses from $00E0 to $00FF serve as both the user RAM and
the stack RAM. The CPU uses five RAM bytes to save all CPU register
contents before processing an interrupt. During a subroutine call, the
CPU uses two bytes to store the return address. The stack pointer
decrements during pushes and increments during pulls.
NOTE:
Be careful when using nested subroutines or multiple interrupt levels.
The CPU may overwrite data in the RAM during a subroutine or during
the interrupt stacking operation.
Technical Data
MC68HC705K1 — Rev. 2.0
Memory
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Memory
Random-Access Memory (RAM)
$0000
I/O REGISTERS
32 BYTES
$001F
$0020
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$00DF
$00E0
UNUSED
192 BYTES
USER
STACK
RAM
RAM
32 BYTES 32 BYTES
$00FF
$0100
$01FF
$0200
UNUSED
256 BYTES
USER EPROM
496 BYTES
$03EF
$03F0
$03F7
$03F8
$03FF
TEST ROM AND
COP REGISTER
(8 BYTES)
USER VECTORS (EPROM)
8 BYTES
PORT A DATA REGISTER
PORT B DATA REGISTER
UNUSED
UNUSED
PORT A DATA DIRECTION REGISTER
PORT B DATA DIRECTION REGISTER
UNUSED
UNUSED
TIMER STATUS AND CONTROL REGISTER
TIMER COUNTER REGISTER
IRQ STATUS AND CONTROL REGISTER
UNUSED
UNUSED
UNUSED
PEPROM BIT SELECT REGISTER
PEPROM STATUS AND CONTROL REGISTER
PULLDOWN REGISTER A
PULLDOWN REGISTER B
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
MASK OPTION REGISTER
EPROM PROGRAMMING REGISTER
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
TEST
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
$000C
$000D
$000E
$000F
$0010
$0011
$0012
$0013
$0014
$0015
$0016
$0017
$0018
$0019
$001A
$001B
$001C
$001D
$001E
$001F
COP REGISTER *
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
TIMER VECTOR (HIGH BYTE)
TIMER VECTOR (LOW BYTE)
EXTERNAL INTERRUPT VECTOR (HIGH BYTE)
EXTERNAL INTERRUPT VECTOR (LOW BYTE)
SOFTWARE INTERRUPT VECTOR (HIGH BYTE)
SOFTWARE INTERRUPT VECTOR (LOW BYTE)
RESET VECTOR (LOW BYTE)
RESET VECTOR (LOW BYTE)
$03F0
$03F1
$03F2
$03F3
$03F4
$03F5
$03F6
$03F7
$03F8
$03F9
$03FA
$03FB
$03FC
$03FD
$03FE
$03FF
* Writing to bit 0 of $03F0 clears the COP watchdog.
Reading $03F0 returns ROM data.
Figure 2-1. Memory Map
MC68HC705K1 — Rev. 2.0
Technical Data
Memory
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Memory
Addr.
Register Name
Read:
Port A Data Register
(PORTA) Write:
See page 64.
Reset:
$0000
Read:
Port B Data Register
(PORTB) Write:
See page 69.
Reset:
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$0001
$0002
Unimplemented
$0003
Unimplemented
$0004
$0005
Bit 7
6
5
4
3
2
1
Bit 0
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
0
PB1/
OSC3
PB0
Unaffected by reset
0
0
0
0
Unaffected by reset
Read:
Data Direction Register A
DDRA7
(DDRA) Write:
See page 65.
Reset:
0
Read:
Data Direction Register B
(DDRB) Write:
See page 70.
Reset:
0
0
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
0
0
0
0
0
0
0
0
0
0
0
0
DDRB1
DDRB0
0
0
RT1
RT0
0
0
RTIF
0
0
TOIE
RTIE
0
0
TOFR
RTIFR
$0006
Unimplemented
$0007
Unimplemented
TOF
$0008
Read:
Timer Status and Control
Register (TSCR) Write:
See page 77.
Reset:
0
0
0
0
U
U
1
1
Read:
Timer Counter Register
(TCNTR) Write:
See page 79.
Reset:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
IRQE
0
0
0
$0009
$000A
Read:
IRQ Status and Control
Register (ISCR) Write:
See page 45.
Reset:
IRQF
0
0
IRQR
1
0
0
= Unimplemented
0
0
R
= Reserved
0
U
0
U = Unaffected
Figure 2-2. I/O Register Summary (Sheet 1 of 3)
Technical Data
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Memory
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Memory
Random-Access Memory (RAM)
Addr.
Register Name
$000B
Unimplemented
Bit 7
6
5
4
3
2
1
Bit 0
PEB7
PEB6
PEB5
PEB4
PEB3
PEB2
PEB1
PEB0
0
0
0
0
0
0
0
0
0
PEPGM
0
0
0
0
0
0
0
0
0
0
1
PDIA6
PDIA5
PDIA4
PDIA3
PDIA2
PDIA1
PDIA0
0
0
0
0
0
0
0
0
0
0
0
0
0
PDIB1
PDIB0
0
0
0
0
0
0
0
0
PIN3
RC
SWAIT
LVRE
PIRQ
LEVEL
COPEN
↓
$000D
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$000E
$000F
$0010
$0011
$0012
Unimplemented
Read:
PEPROM Bit Select Register
(PEBSR) Write:
See page 93.
Reset:
Read: PEDATA
PEPROM Status and Control
Register (PESCR) Write:
See page 95.
Reset:
U
Read:
Pulldown Register A
(PDRA) Write: PDIA7
See page 66.
Reset:
0
Read:
Pulldown Register B
(PDRB) Write:
See page 71.
Reset:
PEPRZF
Unimplemented
↓
$0016
$0017
$0018
Unimplemented
Read:
Mask Option Register
SWPDI
(MOR) Write:
See page 87.
Reset:
Read:
EPROM Programming
Register (EPROG) Write:
See page 84.
Reset:
Unaffected by reset
R
R
R
R
R
ELAT
MPGM
EPGM
U
U
U
U
U
0
0
0
= Unimplemented
R
= Reserved
U = Unaffected
Figure 2-2. I/O Register Summary (Sheet 2 of 3)
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Memory
Addr.
Register Name
$0019
Unimplemented
Bit 7
6
5
4
3
2
1
Bit 0
↓
$001E
Unimplemented
Read:
LVRF
$001F
Test Register Write:
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Reset:
U
U
U
U
U
U
0
U
↓
$03F0
Read:
COP Register
(COPR) Write:
See page 54.
Reset:
COPC
U
U
U
U
U
= Unimplemented
R
= Reserved
U
U
0
U = Unaffected
Figure 2-2. I/O Register Summary (Sheet 3 of 3)
2.6 EPROM/OTPROM
An MCU with a quartz window has 504 bytes of erasable, programmable
ROM (EPROM). The quartz window allows EPROM erasure with
ultraviolet light. In an MCU without the quartz window, the EPROM
cannot be erased and serves as 504 bytes of one-time programmable
ROM (OTPROM). Addresses $0020–$03EF contain 496 bytes of user
EPROM/OTPROM. The eight addresses from $03F8 to $03FF are
EPROM/OTPROM locations reserved for interrupt vectors and reset
vectors.
2.7 Personality EPROM/OTPROM
An MCU with a quartz window has a 64-bit array of erasable,
programmable ROM (EPROM) to serve as a personality EPROM. The
quartz window allows EPROM erasure with ultraviolet light. In an MCU
without the quartz window, the personality EPROM cannot be erased
and serves as a 64-bit array of OTPROM.
Technical Data
MC68HC705K1 — Rev. 2.0
Memory
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Technical Data — MC68HC705K1
Section 3. Central Processor Unit (CPU)
3.1 Contents
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3.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
3.3
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
3.3.1
Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
3.3.2
Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
3.3.3
Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
3.3.4
Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
3.3.5
Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . .36
3.4
Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . .37
3.2 Introduction
This section describes the central processor unit (CPU) registers.
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Central Processor Unit (CPU)
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Central Processor Unit (CPU)
3.3 CPU Registers
Figure 3-1 shows the five CPU registers. CPU registers and are not part
of the memory map.
7
6
5
4
3
2
1
0
ACCUMULATOR (A)
7
6
5
4
3
2
1
0
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INDEX
REGISTER (X)
15
14
13
12
11
10
9
8
7
6
5
0
0
0
0
0
0
0
0
1
1
1
15
14
13
12
11
10
9
8
7
6
5
0
0
0
0
0
0
4
3
2
1
0
STACK
POINTER (SP)
4
3
2
1
0
PROGRAM
COUNTER (PC)
7
6
5
4
3
2
1
0
1
1
1
H
I
N
Z
C
CONDITION CODE
REGISTER (CCR)
HALF-CARRY FLAG
INTERRUPT MASK
NEGATIVE FLAG
ZERO FLAG
CARRY/BORROW FLAG
Figure 3-1. Programming Model
Technical Data
MC68HC705K1 — Rev. 2.0
Central Processor Unit (CPU)
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Central Processor Unit (CPU)
CPU Registers
3.3.1 Accumulator
The accumulator (A) shown in Figure 3-2 is a general-purpose 8-bit
register. The CPU uses the accumulator to hold operands and results of
arithmetic and non-arithmetic operations.
Bit 7
6
5
4
3
2
1
Bit 0
Read:
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Write:
Reset:
Unaffected by reset
Figure 3-2. Accumulator (A)
3.3.2 Index Register
In the indexed addressing modes, the CPU uses the byte in the index
register (X) shown in Figure 3-3 to determine the conditional address of
the operand. See 11.3.5 Indexed, No Offset, 11.3.6 Indexed, 8-Bit
Offset, and 11.3.7 Indexed, 16-Bit Offset for more information on
indexed addressing.
The 8-bit index register also can serve as a temporary data storage
location.
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Unaffected by reset
Figure 3-3. Index Register (X)
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Central Processor Unit (CPU)
3.3.3 Stack Pointer
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The stack pointer (SP) shown in Figure 3-4 is a 16-bit register that
contains the address of the next free location on the stack. During a
reset or after the reset stack pointer (RSP) instruction, the stack pointer
initializes to $00FF. The address in the stack pointer decrements as data
is pushed onto the stack and increments as data is pulled from the stack.
The 11 most significant bits of the stack pointer are fixed permanently at
00000000111, so the stack pointer produces addresses from $00E0 to
$00FF. If subroutines and interrupts use more than 32 stack locations,
the stack pointer wraps around to address $00FF and begins writing
over the previously stored data. A subroutine uses two stack locations.
An interrupt uses five locations.
Read:
Bit
15
14
13
12
11
10
9
8
7
6
5
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
1
1
1
4
3
2
1
Bit
0
1
1
1
1
1
Write:
Reset:
= Unimplemented
Figure 3-4. Stack Pointer (SP)
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Central Processor Unit (CPU)
CPU Registers
3.3.4 Program Counter
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The program counter (PC) shown in Figure 3-5 is a 16-bit register that
contains the address of the next instruction or operand to be fetched.
The six most significant bits of the program counter are ignored internally
and appear as 000000.
Normally, the address in the program counter automatically increments
to the next sequential memory location every time an instruction or
operand is fetched. Jump, branch, and interrupt operations load the
program counter with an address other than that of the next sequential
location.
Read:
Write:
Reset:
Bit
15
14
13
12
11
10
0
0
0
0
0
0
0
0
0
0
0
0
9
8
7
6
5
4
3
2
1
Bit
0
Loaded with vector from $03FE and $03FF
Figure 3-5. Program Counter (PC)
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Central Processor Unit (CPU)
3.3.5 Condition Code Register
The condition code register (CCR) shown in Figure 3-6 is an 8-bit
register whose three most significant bits are permanently fixed at 111.
The condition code register contains the interrupt mask and four flags
that indicate the results of prior instructions.
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Read:
Bit 7
6
5
1
1
1
4
3
2
1
Bit 0
H
I
N
Z
C
U
1
U
U
U
Write:
Reset:
1
1
1
= Unimplemented
U = Unaffected
Figure 3-6. Condition Code Register (CCR)
H — Half-Carry Flag
The CPU sets the half-carry flag when a carry occurs between bits 3
and 4 of the accumulator during an add without carry (ADD) or add
with carry (ADC) operation. The half-carry bit is required for
binary-coded decimal (BCD) arithmetic operations. Reset has no
affect on the half-carry flag.
I — Interrupt Mask Flag
Setting the interrupt mask (I) disables interrupts. If an interrupt
request occurs while the interrupt mask is a logic 0, the CPU saves
the CPU registers on the stack, sets the interrupt mask, and then
fetches the interrupt vector. If an interrupt request occurs while the
interrupt mask is set, the interrupt request is latched. The CPU
processes the latched interrupt as soon as the interrupt mask is
cleared again.
A return-from-interrupt (RTI) instruction pulls the CPU registers from
the stack, restoring the interrupt mask to its cleared state. After a
reset, the interrupt mask is set and can be cleared only by a clear
interrupt mask bit (CLI), STOP, or WAIT instruction.
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Central Processor Unit (CPU)
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Central Processor Unit (CPU)
Arithmetic/Logic Unit (ALU)
N — Negative Flag
The CPU sets the negative flag when an arithmetic operation, logical
operation, or data manipulation produces a negative result (bit 7 in the
results is a logic 1). Reset has no effect on the negative flag.
Z — Zero Flag
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The CPU sets the zero flag when an arithmetic operation, logical
operation, or data manipulation produces a result of $00. Reset has
no effect on the zero flag.
C — Carry/Borrow Flag
The CPU sets the carry/borrow flag when an addition operation
produces a carry out of bit 7 of the accumulator or when a subtraction
operation requires a borrow. Some logical operations and data
manipulation instructions also clear or set the carry/borrow bit. Reset
has no effect on the carry/borrow flag.
3.4 Arithmetic/Logic Unit (ALU)
The arithmetic/logic unit (ALU) performs the arithmetic and logical
operations defined by the instruction set. The binary arithmetic circuits
decode instructions and set up the ALU for the selected operation. Most
binary arithmetic is based on the addition algorithm, carrying out
subtraction as negative addition. Multiplication is not performed as a
discrete operation but as a chain of addition and shift operations within
the ALU. The multiply instruction requires 11 internal clock cycles to
complete this chain of operations.
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Central Processor Unit (CPU)
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Central Processor Unit (CPU)
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MC68HC705K1 — Rev. 2.0
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Technical Data — MC68HC705K1
Section 4. Interrupts
4.1 Contents
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4.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
4.3
Interrupt Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
4.3.1
Software Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
4.3.2
External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
4.3.2.1
IRQ/VPP Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
4.3.2.2
PA3–PA0 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
4.3.2.3
IRQ Status and Control Register . . . . . . . . . . . . . . . . . . .45
4.3.3
Timer Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
4.3.3.1
Timer Overflow Interrupt . . . . . . . . . . . . . . . . . . . . . . . . .46
4.3.3.2
Real-Time Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
4.4
Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
4.2 Introduction
This section describes how interrupts temporarily change the normal
processing sequence.
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Interrupts
4.3 Interrupt Types
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These conditions generate interrupts:
•
SWI instruction (software interrupt)
•
A logic 0 applied to the IRQ/VPP pin (external interrupt)
•
A logic 1 applied to one of the PA3–PA0 pins when port A external
interrupts are enabled (external interrupt)
•
A timer overflow (timer interrupt)
•
Expiration of the real-time interrupt period (timer interrupt)
An interrupt temporarily stops normal program execution to process a
particular event. An interrupt does not stop the execution of the
instruction in progress, but takes effect when the current instruction
completes its execution. Interrupt processing automatically saves the
central processor unit (CPU) registers on the stack and loads the
program counter with a user-defined vector address.
4.3.1 Software Interrupt
The software interrupt (SWI) instruction causes a non-maskable
interrupt.
4.3.2 External Interrupts
These sources can generate external interrupts:
•
IRQ/VPP pin
•
PA3–PA0 pins when port A external interrupts are enabled
Setting the I bit in the condition code register or clearing the IRQE bit in
the interrupt status and control register disables external interrupts.
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Interrupts
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Interrupts
Interrupt Types
4.3.2.1 IRQ/VPP Pin
An interrupt signal on the IRQ/VPP pin latches an external interrupt
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request. After completing the current instruction, the CPU tests these
bits:
•
IRQ latch
•
IRQE bit in the interrupt status and control register
•
I bit in the condition code register
If both the IRQ latch and the IRQE bit are set, and the I bit is clear, the
CPU then begins the interrupt sequence. The CPU clears the IRQ latch
while it fetches the interrupt vector, so that another external interrupt
request can be latched during the interrupt service routine. As soon as
the I bit is cleared during the return from interrupt, the CPU can
recognize the new interrupt request. Figure 4-1 shows the logic for
external interrupts.
The IRQ/VPP pin is negative edge-triggered only or negative edge- and
low-level-triggered, depending on the state of the LEVEL bit in the mask
option register (MOR). See 9.6 Mask Option Register.
Programming the LEVEL bit to a logic 1 selects the edge- and
level-sensitive trigger option. When LEVEL = 1:
•
A falling edge or a low level on the IRQ/VPP pin latches an external
interrupt request.
•
As long as the IRQ/VPP is low, an external interrupt request is
present, and the CPU continues to execute the interrupt service
routine. The edge- and level-sensitive trigger option allows
connection to the IRQ/VPP pin of multiple wired-OR interrupt
sources.
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Interrupts
Programming the LEVEL bit to a logic 0 selects the edge-sensitive-only
trigger option. When LEVEL = 0:
A falling edge on the IRQ/VPP pin latches an external interrupt
request.
•
A subsequent interrupt request can be latched only after the
voltage level on the IRQ/VPP pin returns to logic 1 and then falls
again to logic 0.
If the IRQ/VPP pin is not in use, connect it to the VDD pin.
TO BIH & BIL
INSTRUCTION
PROCESSING
IRQ/VPP
PA3
VDD
PA2
IRQ
LATCH
EXTERNAL
INTERRUPT
REQUEST
R
IRQF
PA1
PA0
IRQR
IRQE
LEVEL
RST
IRQ VECTOR FETCH
PIRQ
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NOTE:
•
MASK OPTION REGISTER
IRQ STATUS/CONTROL REGISTER
INTERNAL DATA BUS
Figure 4-1. External Interrupt Logic
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Interrupts
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Interrupts
Interrupt Types
4.3.2.2 PA3–PA0 Pins
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Programming the PIRQ bit in the mask option register to a logic 1
enables pins PA3–PA0 to serve as additional external interrupt sources.
See 9.6 Mask Option Register. An interrupt signal on a PA3–PA0 pin
latches an external interrupt request. After completing the current
instruction, the CPU tests these bits:
•
IRQ latch
•
IRQE bit in the IRQ status and control register
•
I bit in the condition code register.
If both the IRQ latch and the IRQE bit are set, and the I bit is clear, the
CPU then begins the interrupt sequence. The CPU clears the IRQ latch
while it fetches the interrupt vector, so that another external interrupt
request can be latched during the interrupt service routine. As soon as
the I bit is cleared during the return from interrupt, the CPU can
recognize the new interrupt request.
The PA3–PA0 pins are edge-triggered only or both edge- and
level-triggered, depending on the state of the LEVEL bit in the MOR.
Programming the LEVEL bit to a logic 1 selects the edge- and
level-sensitive trigger option. When LEVEL = 1:
•
A rising edge or a high level on a PA3–PA0 pin latches an external
interrupt request if and only if all other PA3–PA0 pins are low and
the IRQ/VPP pin is high.
•
A falling edge or a low level on the IRQ/VPP pin latches an external
interrupt request if and only if all of the PA3–PA0 pins are low.
•
As long as any PA3–PA0 pin is high or the IRQ/VPP pin is low, an
external interrupt request is present, and the CPU continues to
execute the interrupt service routine.
MC68HC705K1 — Rev. 2.0
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Interrupts
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Interrupts
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Programming the LEVEL bit to a logic 0 selects the edge-sensitive only
trigger option. When LEVEL = 0:
•
A rising edge on a PA3–PA0 pin latches an external interrupt
request if and only if all other PA3–PA0 pins are low and the
IRQ/VPP pin is high.
•
A falling edge on the IRQ/VPP pin latches an external interrupt
request if and only if all of the PA3–PA0 pins are low.
•
A subsequent PA3–PA0 pin interrupt request can be latched only
after the voltage level of the previous PA3–PA0 interrupt signal
returns to a logic 0 and then rises again to a logic 1.
•
A subsequent IRQ/VPP pin interrupt request can be latched only
after the voltage level of the previous IRQ/VPP interrupt signal
returns to a logic 1 and then falls again to a logic 0.
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MC68HC705K1 — Rev. 2.0
Interrupts
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Interrupts
Interrupt Types
4.3.2.3 IRQ Status and Control Register
The IRQ status and control register (ISCR) contains an external interrupt
mask, an external interrupt flag, and a flag reset bit. Unused bits read as
logic 0s.
Address:
$000A
Bit 7
6
5
4
IRQE
0
0
0
Read:
3
2
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Bit 0
IRQF
0
0
IRQR
Write:
Reset:
1
1
0
0
= Unimplemented
0
0
0
U
0
U = Unaffected
Figure 4-2. IRQ Status and Control Register (ISCR)
IRQE — External Interrupt Request Enable Bit
This read/write bit enables external interrupts. Reset sets the IRQE
bit.
1 = External interrupt processing enabled
0 = External interrupt processing disabled
IRQF — External Interrupt Request Flag
The IRQF bit is a clearable, read-only flag that is set when an external
interrupt request is pending. Reset clears the IRQF bit.
1 = Interrupt request pending
0 = No interrupt request pending
These conditions set the IRQF bit:
a. An external interrupt signal on the IRQ/VPP pin
b. An external interrupt signal on pin PA3, PA2, PA1, or PA0
when PA3–PA0 are enabled to serve as external interrupt
sources
The CPU clears the IRQF bit when fetching the interrupt vector.
Writing to the IRQF bit has no effect. Writing a logic 1 to the IRQR bit
clears the IRQF bit.
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Interrupts
IRQR — Interrupt Request Reset Bit
Writing a logic 1 to this write-only bit clears the IRQF bit. Writing a
logic 0 to IRQR has no effect. Reset has no effect on IRQR.
1 = IRQF bit cleared
0 = No effect
4.3.3 Timer Interrupts
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The multifunction timer can generate these interrupts:
•
Timer overflow interrupt
•
Real-time interrupt
Setting the I bit in the condition code register disables all timer interrupts.
4.3.3.1 Timer Overflow Interrupt
A timer overflow interrupt request occurs if the timer overflow flag, TOF,
becomes set while the timer overflow interrupt enable bit, TOIE, is also
set. See 8.3 Timer Status and Control Register.
4.3.3.2 Real-Time Interrupt
A real-time interrupt request occurs if the real-time interrupt flag, RTIF,
becomes set while the real-time interrupt enable bit, RTIE, is also set.
See 8.3 Timer Status and Control Register.
Technical Data
MC68HC705K1 — Rev. 2.0
Interrupts
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Interrupts
Interrupt Processing
4.4 Interrupt Processing
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The CPU does these things to begin servicing an interrupt:
•
Stores the CPU registers on the stack in the order shown in
Figure 4-3
•
Sets the I bit in the condition code register to prevent further
interrupts
•
Loads the program counter with the contents of the appropriate
interrupt vector locations:
– $03FC and $03FD (software interrupt vector)
– $03FA and $03FB (external interrupt vector)
– $03F8 and $03F9 (timer interrupt vector)
The return-from-interrupt (RTI) instruction causes the CPU to recover
the CPU registers from the stack as shown in Figure 4-3.
$00E0 (BOTTOM OF STACK)
$00E1
$00E2
UNSTACKING
ORDER
•
•
•
•
•
•
5
1
CONDITION CODE REGISTER
4
2
ACCUMULATOR
3
3
INDEX REGISTER
2
4
PROGRAM COUNTER (HIGH BYTE)
1
5
PROGRAM COUNTER (LOW BYTE)
STACKING
ORDER
•
•
•
•
•
•
$00FD
$00FE
$00FF (TOP OF STACK)
Figure 4-3. Interrupt Stacking Order
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Interrupts
Table 4-1 summarizes the reset and interrupt sources and vector
assignments.
Table 4-1. Reset/Interrupt Vector Addresses
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Function
Reset
Software
interrupt
(SWI)
External
interrupts
Timer
interrupts
Local
Mask
Source
Global
Mask
MOR
Control
Bit
Power-on logic
None
RESET pin
None
COP watchdog
None
None
LVIE(2)
Illegal address logic
None
None
None
None
IRQ/VPP pin
None
PA3 pin
PIRQ(3)
PA2 pin
IRQE bit
I bit
PIRQ3
PA0 pin
PIRQ3
TOFE bit
RTIF bit
RTIE bit
I bit
1
$03FE–$03FF
Same priority
as instruction
$03FC–$03FD
2
$03FA–$03FB
3
$03F8–$03F9
PIRQ3
PA1 pin
TOF bit
Vector
Address
COPEN(1)
Low voltage detect
User code
Priority
(1 = Highest)
None
1. COPEN enables the COP watchdog.
2. LVIE enables low-voltage resets.
3. PIRQ enables port A external interrupts.
NOTE:
If more than one interrupt request is pending, the CPU fetches the vector
of the higher priority interrupt first. A higher priority interrupt does not
interrupt a lower priority interrupt service routine unless the lower priority
interrupt service routine clears the I bit.
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MC68HC705K1 — Rev. 2.0
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Interrupts
Interrupt Processing
Figure 4-4 shows the sequence of events caused by an interrupt.
FROM
RESET
YES
I BIT SET?
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NO
EXTERNAL
INTERRUPT?
YES
CLEAR IRQ LATCH
NO
TIMER
INTERRUPT?
YES
STACK PCL, PCH, X, A, CCR
SET I BIT
LOAD PC WITH INTERRUPT VECTOR
NO
FETCH NEXT
INSTRUCTION
SWI
INSTRUCTION?
YES
NO
RTI
INSTRUCTION?
YES
UNSTACK CCR, A, X, PCH, PCL
NO
EXECUTE INSTRUCTION
Figure 4-4. Interrupt Flowchart
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Interrupts
Technical Data
MC68HC705K1 — Rev. 2.0
Interrupts
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Section 5. Resets
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5.1 Contents
5.3
Reset Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
5.3.1
Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
5.3.2
External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
5.3.3
Computer Operating Properly (COP) Reset . . . . . . . . . . . . .54
5.3.4
Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
5.3.5
Low-Voltage Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
5.4
Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
5.4.1
CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
5.4.2
I/O Port Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
5.4.3
Multifunction Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
5.4.4
COP Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
5.2 Introduction
This section describes the five reset sources and how they initialize the
microcontroller unit (MCU).
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Resets
5.3 Reset Types
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A reset immediately stops the operation of the instruction being
executed, initializes certain control bits, and loads the program counter
with a user-defined reset vector address. These conditions produce a
reset:
•
Initial power-up (power-on reset)
•
A logic 0 applied to the RESET pin (external reset)
•
Timeout of the computer operating properly (COP) watchdog
(COP reset)
•
An opcode fetch from an address not in the memory map (illegal
address reset)
•
VDD voltage below nominal 3.5 volts (low-voltage reset)
5.3.1 Power-On Reset
A positive transition on the VDD pin generates a power-on reset. The
power-on reset is strictly for power-up conditions and cannot be used to
detect drops in power supply voltage.
A 4064 tCYC (internal clock cycle) delay after the oscillator becomes
active allows the clock generator to stabilize. If the RESET pin is at
logic 0 at the end of 4064 tCYC, the MCU remains in the reset condition
until the signal on the RESET pin goes to logic 1.
5.3.2 External Reset
A logic 0 applied to the RESET pin for one and one-half tCYC generates
an external reset. A Schmitt trigger senses the logic level at the RESET
pin.
A COP reset or an illegal address reset pulls the RESET pin low for one
internal clock cycle. A low-voltage reset pulls the RESET pin low for as
long as the low-voltage condition exists.
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Resets
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Resets
Reset Types
COPEN
LVRE
MASK OPTION REGISTER
COP WATCHDOG
LOW-VOLTAGE RESET
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IRQ/VPP
POWER-ON RESET
ILLEGAL ADDRESS RESET
INTERNAL ADDRESS BUS
RESET
INTERNAL
CLOCK
S
D
RESET
LATCH
RST
TO CPU AND
SUBSYSTEMS
R
Figure 5-1. Reset Sources
NOTE:
To avoid overloading some power supply designs, do not connect the
RESET pin directly to VDD. Use a pullup resistor of 10 kΩ or more.
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Resets
5.3.3 Computer Operating Properly (COP) Reset
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A timeout of the COP watchdog generates a COP reset. The COP
watchdog is part of a software error detection system and must be
cleared periodically to start a new timeout period. (See 8.5 COP
Watchdog.) To clear the COP watchdog and prevent a COP reset, write
a logic 0 to bit 0 (COPC) of the COP register at location $03F0. The COP
register is a write-only register that returns the contents of a ROM
location when read.
Address:
$03F0
Bit 7
6
5
4
3
2
1
Bit 0
Read:
COPC
Write:
Reset:
U
U
U
= Unimplemented
U
U
U
U
0
U = Unaffected
Figure 5-2. COP Register (COPR)
COPC — COP Clear Bit
COPC is a write-only bit. Periodically writing a logic 0 to COPC
prevents the COP watchdog from resetting the MCU. Writing a logic 1
has no effect. Reset clears the COPC bit.
5.3.4 Illegal Address Reset
An opcode fetch from an address that is not in the erasable,
programmable read-only memory (EPROM) (locations $0200–$03FF)
or the random-access memory (RAM) (locations $00E0–$00FF)
generates an illegal address reset. An illegal address reset pulls the
RESET pin low for one cycle of the internal clock.
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Resets
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Resets
Reset States
5.3.5 Low-Voltage Reset
The low-voltage reset circuit generates a reset signal if the voltage on
the VDD pin falls below 3.5 V (nominal). VDD must be set at 5 V ±10%
while the low-voltage reset circuit is enabled.
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Programming the LVRE bit to a logic 1 enables the low-voltage reset
function. When erased, the LVRE bit in the mask option register disables
the low-voltage reset circuit. See 9.6 Mask Option Register.
A low-voltage reset pulls the RESET pin low for as long as the
low-voltage condition exists.
The state of the low-voltage reset circuit is readable in the test register
at location $001F. Bit 1 of the test register is the low-voltage reset flag
(LVRF). Regardless of the LVRE bit in the mask option register, the
low-voltage reset circuit is active in all modes except stop mode.
5.4 Reset States
This subsection describes how resets initialize the MCU.
5.4.1 CPU
A reset has these effects on the central processor unit (CPU):
•
Loads the stack pointer with $FF
•
Sets the I bit in the condition code register, inhibiting interrupts
•
Sets the IRQE bit in the interrupt status and control register
•
Loads the program counter with the user-defined reset vector from
locations $03FE and $03FF
•
Clears the stop latch, enabling the CPU clock
•
Clears the wait latch, waking the CPU from the wait mode
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5.4.2 I/O Port Registers
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A reset has these effects on input/output (I/O) port registers:
•
Clears bits DDRA7–DDRA0 in data direction register A so that
port A pins are inputs
•
Clears bits PDIA7–PDIA0 in pulldown register A so that port A
pulldown devices are enabled (if the SWPDI bit in the mask option
register is programmed to a logic 0)
•
Clears bits DDRB1 and DDRB0 in data direction register B so that
port B pins are inputs (if the SWPDI bit in the mask option register
is programmed to logic 0)
•
Clears bits PDIB1 and PDIB0 in pulldown register B so that port B
pulldown devices are enabled
•
Has no effect on port A or port B data registers
5.4.3 Multifunction Timer
A reset has these effects on the multifunction timer:
•
Clears the timer status and control register
•
Clears the timer counter register
5.4.4 COP Watchdog
A reset clears the COP watchdog timeout counter.
Technical Data
MC68HC705K1 — Rev. 2.0
Resets
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Section 6. Low-Power Modes
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6.1 Contents
6.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
6.3
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
6.4
Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
6.5
Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
6.6
Data-Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
6.2 Introduction
This section describes the four low-power modes:
•
Stop mode
•
Wait mode
•
Halt mode
•
Data-retention mode
6.3 Stop Mode
If the SWAIT bit in the mask option register (MOR) is programmed to a
logic 0, the STOP instruction puts the microcontroller unit (MCU) in its
lowest power-consumption mode and has these effects on the MCU:
•
Clears TOF and RTIF, the timer interrupt flags in the timer status
and control register, removing any pending timer interrupts
•
Clears TOIE and RTIE, the timer interrupt enable bits in the timer
status and control register, disabling further timer interrupts
•
Clears the multifunction timer counter register
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•
Sets the IRQE bit in the IRQ status and control register to enable
external interrupts
•
Clears the I bit in the condition code register, enabling interrupts
•
Stops the internal oscillator, turning off the central processor unit
(CPU) clock and the timer clock, including the computer operating
properly (COP) watchdog
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The STOP instruction does not affect any other registers or any
input/output (I/O) lines.
These conditions bring the MCU out of stop mode:
•
An external interrupt signal on the IRQ/VPP pin — A high-to-low
transition on the IRQ/VPP pin loads the program counter with the
contents of locations $03FA and $03FB.
•
An external interrupt signal on a port A external interrupt pin — If
the PIRQ bit in the mask option register is programmed to a
logic 1, a low-to-high transition on a PA3–PA0 pin loads the
program counter with the contents of locations $03FA and $03FB.
•
External reset — A logic 0 on the RESET pin resets the MCU and
loads the program counter with the contents of locations $03FE
and $03FF.
When the MCU exits stop mode, processing resumes after a
stabilization delay of 4064 oscillator cycles.
6.4 Wait Mode
The WAIT instruction puts the MCU in an intermediate
power-consumption mode and has these effects on the MCU:
•
Clears the I bit in the condition code register, enabling interrupts
•
Sets the IRQE bit in the IRQ status and control register, enabling
external interrupts
•
Stops the CPU clock, but allows the internal oscillator and timer
clock to continue to run
The WAIT instruction does not affect any other registers or any I/O lines.
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Low-Power Modes
Halt Mode
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These conditions restart the CPU clock and bring the MCU out of wait
mode:
•
An external interrupt signal on the IRQ/VPP pin — A high-to-low
transition on the IRQ/VPP pin loads the program counter with the
contents of locations $03FA and $03FB.
•
An external interrupt signal on a port A external interrupt pin — If
the PIRQ bit in the mask option register is programmed to a
logic 1, a low-to-high transition on a PA3–PA0 pin loads the
program counter with the contents of locations $03FA and $03FB.
•
A timer interrupt — A timer overflow or a real-time interrupt request
loads the program counter with the contents of locations $03F8
and $03F9.
•
A COP watchdog reset — A timeout of the COP watchdog resets
the MCU and loads the program counter with the contents of
locations $03FE and $03FF. Software can enable real-time
interrupts so that the MCU can periodically exit wait mode to reset
the COP watchdog.
•
External reset — A logic 0 on the RESET pin resets the MCU and
loads the program counter with the contents of locations $03FE
and $03FF.
6.5 Halt Mode
The STOP instruction puts the MCU in halt mode if the SWAIT bit in the
mask option register is programmed to a logic 1. Halt mode is identical
to wait mode, except that a recovery delay of 1–4064 internal clock
cycles occurs when the MCU exits halt mode. When the SWAIT bit is set,
the COP watchdog cannot be inadvertently turned off by a STOP
instruction.
Figure 6-1 shows the sequence of events in stop, wait, and halt modes.
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Low-Power Modes
STOP
YES
SWAIT
BIT SET?
HALT
WAIT
CLEAR I BIT IN CCR
SET IRQE BIT IN ISCR
TURN OFF CPU CLOCK
TIMER CLOCK ACTIVE
CLEAR I BIT IN CCR
SET IRQE BIT IN ISCR
TURN OFF CPU CLOCK
TIMER CLOCK ACTIVE
NO
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CLEAR I BIT IN CCR
SET IRQE BIT IN ISCR
CLEAR TOF, RTIF, TOIE, AND RTIE BITS IN TSCR
TURN OFF INTERNAL OSCILLATOR
YES
EXTERNAL
RESET?
YES
EXTERNAL
RESET?
YES
NO
EXTERNAL
RESET?
NO
NO
YES
EXTERNAL
INTERRUPT?
YES
EXTERNAL
INTERRUPT?
YES
NO
EXTERNAL
INTERRUPT?
NO
NO
YES
TIMER
INTERRUPT?
YES
TIMER
INTERRUPT?
TURN ON INTERNAL OSCILLATOR
RESET STABILIZATION TIMER
NO
YES
END OF
STABILIZATION
DELAY?
YES
COP
RESET?
NO
NO
YES
COP
RESET?
NO
NO
TURN ON CPU CLOCK
1. LOAD PC WITH RESET VECTOR
OR
2. SERVICE INTERRUPT
a. SAVE CPU REGISTERS ON STACK
b. SET I BIT IN CCR
c. LOAD PC WITH INTERRUPT VECTOR
Figure 6-1. Stop/Wait/Halt Flowchart
Technical Data
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Low-Power Modes
Data-Retention Mode
6.6 Data-Retention Mode
In data-retention mode, the MCU retains random-access memory (RAM)
contents and CPU register contents at VDD voltages as low as 2.0 Vdc.
Data-retention mode allows the MCU to remain in a low
power-consumption state during which it retains data, but the CPU
cannot execute instructions.
To put the MCU in data-retention mode:
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1. Drive the RESET pin to a logic 0.
2. Lower the VDD voltage. The RESET pin must remain low
continuously during data-retention mode.
To take the MCU out of data-retention mode:
1. Return VDD to normal operating voltage.
2. Return the RESET pin to a logic 1.
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Low-Power Modes
Technical Data
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Technical Data — MC68HC705K1
Section 7. Parallel Input/Output (I/O)
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7.1 Contents
7.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
7.3
I/O Port Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
7.4
Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
7.4.1
Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
7.4.2
Data Direction Register A. . . . . . . . . . . . . . . . . . . . . . . . . . . .2
7.4.3
Pulldown Register A (PDRA) . . . . . . . . . . . . . . . . . . . . . . . . .3
7.4.4
Port A External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
7.4.5
Port A Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
7.5
Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
7.5.1
Port B Data Register (PORTB). . . . . . . . . . . . . . . . . . . . . . . .6
7.5.2
Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . . .8
7.5.3
Pulldown Register B (PDRB) . . . . . . . . . . . . . . . . . . . . . . . . .8
7.5.4
Port B Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
7.2 Introduction
This section describes the two bidirectional input/output (I/O) ports:
•
Port A
•
Port B
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Parallel Input/Output (I/O)
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Parallel Input/Output (I/O)
7.3 I/O Port Function
The 10 bidirectional input/output (I/O) pins form two parallel I/O ports.
Each I/O pin is programmable as an input or an output. The contents of
the data direction registers determine the data direction of each I/O pin.
All 10 I/O pins have software-programmable pulldown devices.
Freescale Semiconductor, Inc...
7.4 Port A
Port A is an 8-bit, general-purpose, bidirectional I/O port with these
features:
•
Programmable pulldown devices
•
8-mA current sinking capability (pins PA7–PA4)
•
External interrupt capability (pins PA3–PA0)
7.4.1 Port A Data Register
The port A data register (PORTA) contains a bit for each of the port A
pins. When a port A pin is programmed to be an output, the state of its
data register bit determines the state of the output pin. When a port A pin
is programmed to be an input, reading the port A data register returns
the logic state of the pin.
Address:
$0000
Bit 7
6
5
4
3
2
1
Bit 0
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
Read:
Write:
Reset:
Unaffected by reset
Figure 7-1. Port A Data Register (PORTA)
PA7–PA0 — Port A Data Bits
These read/write bits are software-programmable. Data direction of
each bit is under the control of the corresponding bit in data direction
register A. Reset has no effect on port A data.
Technical Data
MC68HC705K1 — Rev. 2.0
Parallel Input/Output (I/O)
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Parallel Input/Output (I/O)
Port A
7.4.2 Data Direction Register A
The contents of data direction register A (DDRA) determine whether
each port A pin is an input or an output. Writing a logic 1 to a DDRA bit
enables the output buffer for the associated port A pin; a logic 0 disables
the output buffer. A reset initializes all DDRA bits to logic 0s, configuring
all port A pins as inputs. If the pulldown devices are enabled, setting a
DDRA bit to a logic 1 turns off the pulldown device for that pin.
Freescale Semiconductor, Inc...
Address:
$0004
Bit 7
6
5
4
3
2
1
Bit 0
DDRA7
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Figure 7-2. Data Direction Register A (DDRA)
DDRA7–DDRA0 — Port A Data Direction Bits
These read/write bits control port A data direction. Reset clears bits
DDRA7–DDRA0.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
NOTE:
Avoid glitches on port A pins by writing to the port A data register before
changing DDRA bits from logic 0 to logic 1.
MC68HC705K1 — Rev. 2.0
Technical Data
Parallel Input/Output (I/O)
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Parallel Input/Output (I/O)
7.4.3 Pulldown Register A
Programming the SWPDI bit in the mask option register to a logic 0
enables the port A and port B pulldown devices. The port A pulldown
devices sink approximately 100 µA and are under the control of the
PDIA7–PDIA0 bits in pulldown register A (PDRA).
Freescale Semiconductor, Inc...
Clearing the PDIA7–PDIA0 bits turns on the pulldown devices of the port
A pins that are configured as inputs. A pulldown device can be turned on
only when its pin is an input. When SWPDI is a logic 0, reset initializes
all port A pins as inputs with pulldown devices turned on.
Programming the SWPDI bit to a logic 1 disables the port A and port B
pulldown devices. Reset initializes all port A pins as inputs with pulldown
devices disabled when the SWPDI bit is programmed to a logic 1.
Address:
$0010
Bit 7
6
5
4
3
2
1
Bit 0
Write:
PDIA7
PDIA6
PDIA5
PDIA4
PDIA3
PDIA2
PDIA1
PDIA0
Reset:
0
0
0
0
0
0
0
0
Read:
= Unimplemented
Figure 7-3. Pulldown Register A (PDRA)
PDIA7–PDIA0 — Port A Pulldown Inhibit Bits 7–0
Writing logic 0s to these write-only bits turns on the port A pulldown
devices. Reading pulldown register A returns undefined data. Reset
clears bits PDIA7–PDIA0.
1 = Corresponding port A pin pulldown device turned off
0 = Corresponding port A pin pulldown device turned on
NOTE:
Avoid a floating port A input by clearing its pulldown register bit before
changing its DDRA bit from logic 1 to logic 0.
Do not use read-modify-write instructions on pulldown register A.
Technical Data
MC68HC705K1 — Rev. 2.0
Parallel Input/Output (I/O)
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Parallel Input/Output (I/O)
Port A
7.4.4 Port A External Interrupts
NOTE:
When testing for external interrupts, the branch if interrupt pin is high
(BIH) and branch if interrupt pin is low (BIL) instructions test the voltage
on the IRQ/VPP pin, not the state of the internal IRQ signal. Therefore,
BIH and BIL cannot test the port A external interrupt pins.
7.4.5 Port A Logic
Figure 7-4 shows the port A I/O logic.
READ $0004
WRITE $0004
WRITE $0000
INTERNAL DATA BUS
DATA DIRECTION
REGISTER A
BIT DDRAx
PORT A DATA
REGISTER
BIT PAx
EXTERNAL
INTERRUPT
REQUEST
(PINS PA3–PA0)
PAx
8-mA SINK
CAPABILITY
(PINS PA7–PA4)
READ $0000
WRITE $0010
PULLDOWN
REGISTER A
BIT PDIAx
RESET
100-µA
PULLDOWN
DEVICE
SWPDI
Freescale Semiconductor, Inc...
Programming the PIRQ bit in the mask option register to a logic 1
enables the PA3–PA0 pins to serve as external interrupt pins in addition
to the IRQ/VPP pin. The active interrupt state for the PA3–PA0 pins is a
logic 1 or a rising edge. The active interrupt state for the IRQ/VPP pin is
a logic 0 or a falling edge. The state of the LEVEL bit in the mask option
register determines whether external interrupt inputs are edge-sensitive
only or both edge- and level-sensitive.
MASK OPTION REGISTER ($0017)
Figure 7-4. Port A I/O Circuit
MC68HC705K1 — Rev. 2.0
Technical Data
Parallel Input/Output (I/O)
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Parallel Input/Output (I/O)
When a port A pin is programmed as an output, reading the port bit
actually reads the value of the data latch and not the voltage on the pin
itself. When a port A pin is programmed as an input, reading the port bit
reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction register bit. Table 7-1
summarizes the operations of the port A pins.
Freescale Semiconductor, Inc...
Table 7-1. Port A Pin Functions
Pulldown
Mask
Option
PDIAx
DDRAx
No
X(1)
0
No
X
Yes
Control Bits
Accesses
to PDRA
I/O Pin
Mode
Accesses
to DDRA
Accesses
to PORTA
Read
Write
Read/Write
Read
Write
Input, hi-z
U(2)
PDIA7–PDIA0
DDRA7–DDRA0
Pin
PA7–PA0
1
Output
U
PDIA7–PDIA0
DDRA7–DDRA0
PA7-PA0
PA7–PA0
0
0
Input,
pulldown on
U
PDIA7–PDIA0
DDRA7–DDRA0
Pin
PA7–PA0
Yes
0
1
Output
U
PDIA7–PDIA0
DDRA7–DDRA0
PA7-PA0
PA7–PA0
Yes
1
0
Input, hi-z
U
PDIA7–PDIA0
DDRA7–DDRA0
Pin
PA7–PA0
Yes
1
1
Output
U
PDIA7–PDIA0
DDRA7–DDRA0
PA7-PA0
PA7–PA0
1. X = Don’t care
2. U = Undefined
7.5 Port B
Port B is a 2-bit, general-purpose, bidirectional I/O port with these
features:
•
Programmable pulldown devices
•
Oscillator output for 3-pin resistance-capacitance (RC) oscillator
configuration
7.5.1 Port B Data Register
The port B data register (PORTB) contains a bit for each of the port B
pins. When a port B pin is programmed to be an output, the state of its
data register bit determines the state of the output pin. When a port B pin
Technical Data
MC68HC705K1 — Rev. 2.0
Parallel Input/Output (I/O)
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Parallel Input/Output (I/O)
Port B
is programmed to be an input, reading the port B data register returns
the logic state of the pin. Reset has no effect on port B data.
Address:
Read:
$0001
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
PB1/
OSC3
PB0
Write:
Reset:
Unaffected by reset
Freescale Semiconductor, Inc...
= Unimplemented
Figure 7-5. Port B Data Register (PORTB)
PB1/OSC3 — Port B Data Bit 1/Oscillator Output Bit
This read/write data bit is software programmable. Data direction
of PB1 bit is under the control of the DDRB1 bit in data direction
register B.
When both the RC and PIN3 bits in the mask option register are set,
PB1/OSC3 can be used as an oscillator output in the 3-pin RC
oscillator configuration. Using PB1/OSC3 as an oscillator output
affects port B in these ways:
a. Bit PB1 can be used as a read/write storage location without
affecting the oscillator. Reset has no effect on bit PB1.
b. Bit DDRB1 in data direction register B can be used as a
read/write storage location without affecting the oscillator.
Reset clears DDRB1.
c. The PB1/OSC3 pulldown device is disabled, regardless of
the state of the SWPDI bit in the mask option register.
PB0 — Port B Data Bit 0
This read/write data bit is software programmable. Data direction of
PB0 is under the control of the DDRB0 bit in data direction register B.
Bits 7–2 — Not Used
Bits 7–2 always read as logic 0s. Writes to these bits have no effect.
MC68HC705K1 — Rev. 2.0
Technical Data
Parallel Input/Output (I/O)
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Parallel Input/Output (I/O)
7.5.2 Data Direction Register B
The contents of data direction register B (DDRB) determine whether
each port B pin is an input or an output. Writing a logic 1 to a DDRB bit
enables the output buffer for the associated port B pin; a logic 0 disables
the output buffer. A reset initializes all DDRB bits to logic 0, configuring
all port B pins as inputs. Setting a DDRB bit to a logic 1 turns off the
pulldown device for that pin.
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Address:
Read:
$0005
Bit 7
6
5
4
3
2
0
0
0
0
0
0
0
0
0
0
0
0
Write:
Reset:
1
Bit 0
DDRB1
DDRB0
0
0
= Unimplemented
Figure 7-6. Data Direction Register B (DDRB)
DDRB1 and DDRB0 — Data Direction Bits 1 and 0
These read/write bits control port B data direction.
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
Bit 7–2 — Not Used
Bits 7–2 always read as logic 0s. Writes to these bits have no effect.
NOTE:
Avoid glitches on port B pins by writing to the port B data register before
changing DDRB bits from logic 0 to logic 1.
7.5.3 Pulldown Register B
Programming the SWPDI bit in the mask option register to a logic 0
enables the port A and port B pulldown devices. The port B pulldown
devices sink approximately 100 µA and are under the control of the
PDIB1 and PDIB0 bits in pulldown register B (PDRB). Clearing PDIB1
and PDIB0 turns on the port B pulldown devices if they are configured
as inputs. A pulldown device can be turned on only when its pin is an
input. When SWPDI is a logic 0, reset initializes both port B pins as
inputs with pulldown devices turned on.
Technical Data
MC68HC705K1 — Rev. 2.0
Parallel Input/Output (I/O)
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Parallel Input/Output (I/O)
Port B
Programming the SWPDI bit to a logic 1 disables both of the port B
pulldown devices. Reset initializes both port B pins as inputs with
pulldown devices disabled when the SWPDI bit is programmed to a
logic 1.
Address:
$0011
Bit 7
6
5
4
3
2
1
Bit 0
Write:
0
0
0
0
0
0
PDIB1
PDIB0
Reset:
0
0
0
0
0
0
0
0
Freescale Semiconductor, Inc...
Read:
= Unimplemented
Figure 7-7. Pulldown Register B (PDRB)
PDIB1 and PDIB0 — Port B Pulldown Inhibit Bits 1 and 0
Writing logic 0s to these write-only bits turns on the port B pulldown
devices. Reading pulldown register B returns undefined data. Reset
clears PDIB1 and PDIB0.
1 = Corresponding port B pin pulldown device turned off
0 = Corresponding port B pin pulldown device turned on
Bits 7–2 — Not Used
Bits 7–2 always read as logic 0s.
Programming the SWPDI bit in the mask option register to logic 1 turns
off all port A and port B pulldown devices and disables software control
of the pulldown devices. Reset has no effect on the pulldown devices
when the SWPDI bit is set to a logic 1.
NOTE:
Avoid a floating port B input by clearing its pulldown register bit before
changing its DDRB bit from logic 1 to logic 0.
Do not use read-modify-write instructions on pulldown register B.
7.5.4 Port B Logic
Figure 7-8 shows the port B I/O logic.
MC68HC705K1 — Rev. 2.0
Technical Data
Parallel Input/Output (I/O)
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Parallel Input/Output (I/O)
READ $0005
TO 3-PIN OSCILLATOR
WRITE $0005
DATA DIRECTION
REGISTER B
BIT DDRB1
PORT B DATA
REGISTER
BIT PB1
PB1/
OSC3
PULLDOWN
REGISTER B
BIT PDIB1
100-µA
PULLDOWN
DEVICE
SWPDI
RC
WRITE $0011
PIN3
READ $0001
INTERNAL DATA BUS
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WRITE $0001
MASK OPTION REGISTER ($0017)
READ $0005
WRITE $0005
WRITE $0001
DATA DIRECTION
REGISTER B
BIT DDRB0
PORT B DATA
REGISTER
BIT PB0
PB0
READ $0001
WRITE $0011
PULLDOWN
REGISTER B
BIT PDIB0
100-µA
PULLDOWN
DEVICE
RESET
Figure 7-8. Port B I/O Circuit
Technical Data
MC68HC705K1 — Rev. 2.0
Parallel Input/Output (I/O)
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Parallel Input/Output (I/O)
Port B
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When a port B pin is programmed as an output, reading the port bit reads
the value of the data latch and not the voltage on the pin itself. When a
port B pin is programmed as an input, reading the port bit reads the
voltage level on the pin. The data latch can always be written, regardless
of the state of its DDR bit. Table 7-2 summarizes the operation of the
PB0 pin.
Programming the RC and PIN3 bits to logic 1 disables the PB1/OSC3
output buffer and pulldown device. The PB1/OSC3 bit becomes an
output from the 3-pin RC oscillator. The DDRB1 and PB1 bits are
available as read/write storage locations; reset clears DDRB1 but does
not affect PB1. Table 7-3 summarizes the operation of the PB1/OSC3
pin.
Table 7-2. PB0 Pin Functions
Control Bits
PB0
Pin Mode
SWPDI
PDIB0
DDRB0
1
X(1)
0
1
X
0
Accesses
to PDRB
Accesses
to DDRB
Accesses
to PORTB
Read
Write
Read/Write
Read
Write
Input, hi-z
U(2)
PDIB0
DDRB0
Pin
PB0
1
Output
U
PDIB0
DDRB0
PB0
PB0
0
0
Input,
pulldown on
U
PDIB0
DDRB0
Pin
PB0
0
0
1
Output
U
PDIB0
DDRB0
PB0
PB0
0
1
0
Input, hi-z
U
PDIB0
DDRB0
Pin
PB0
0
1
1
Output
U
PDIB0
DDRB0
PB0
PB0
1. X = Don’t care
2. U = Undefined
MC68HC705K1 — Rev. 2.0
Technical Data
Parallel Input/Output (I/O)
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Parallel Input/Output (I/O)
Table 7-3. PB1/OSC3 Pin Functions
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Control Bits
PB1/OSC3
Pin Mode
RC
PIN3
SWPDI
PDIB1
DDRB1
0
X(1)
1
X
0
0
X
1
X
0
X
0
0
X
0
Accesses
to PDRB
Accesses
to DDRB
Accesses
to PORTB
Read
Write
Read/Write
Read
Write
Input, hi-z
U(2)
PDIB1
DDRB1
Pin
PB1
1
Output
U
PDIB1
DDRB1
PB1
PB1
0
0
Input,
pulldown on
U
PDIB1
DDRB1
Pin
PB1
0
0
1
Output
U
PDIB1
DDRB1
PB1
PB1
X
0
1
0
Input, hi-z
U
PDIB1
DDRB1
Pin
PB1
0
X
0
1
1
Output
U
PDIB1
DDRB1
PB1
PB1
1
0
1
X
0
Input, hi-z
U
PDIB1
DDRB1
Pin
PB1
1
0
1
X
1
Output
U
PDIB1
DDRB1
PB1
PB1
1
0
0
0
0
Input,
pulldown on
U
PDIB1
DDRB1
Pin
PB1
1
0
0
0
1
Output
U
PDIB1
DDRB1
PB1
PB1
1
0
0
1
0
Input, hi-z
U
PDIB1
DDRB1
Pin
PB1
1
0
0
1
1
Output
U
PDIB1
DDRB1
PB1
PB1
1
1
X
X
X
3-pin
RC oscillator
output
U
PDIB1
DDRB1
PB1
PB1
1. X = Don’t care
2. U = Undefined
Technical Data
MC68HC705K1 — Rev. 2.0
Parallel Input/Output (I/O)
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Technical Data — MC68HC705K1
Section 8. Multifunction Timer
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8.1 Contents
8.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
8.3
Timer Status and Control Register . . . . . . . . . . . . . . . . . . . . . .77
8.4
Timer Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
8.5
COP Watchdog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
8.2 Introduction
This section describes the operation of the multifunction timer and the
computer operating properly (COP) watchdog. Figure 8-1 shows the
organization of the timer subsystem.
MC68HC705K1 — Rev. 2.0
Technical Data
Multifunction Timer
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Multifunction Timer
RESET
OVERFLOW
INTERNAL CLOCK
÷4
TIMER COUNTER REGISTER
(XTAL ÷ 2)
BITS 0–7 OF 15-STAGE
RIPPLE COUNTER
RTIFR
TOFR
RTIE
TOIE
RTIF
INTERRUPT
REQUEST
TOF
Freescale Semiconductor, Inc...
INTERNAL DATA BUS
RESET
RT0
RT1
TIMER STATUS/CONTROL REGISTER
RESET
CLEAR COP TIMER
RTI RATE SELECT
POWER-ON
RESET (POR)
÷2
÷2
÷2
÷2
÷2
÷2
BITS 8–14 OF 15-STAGE RIPPLE COUNTER
÷2
RESET
÷2
÷2
÷2
S
Q
COP RESET
R
Figure 8-1. Multifunction Timer Block Diagram
Technical Data
MC68HC705K1 — Rev. 2.0
Multifunction Timer
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Multifunction Timer
Timer Status and Control Register
8.3 Timer Status and Control Register
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The read/write timer status and control register (TSCR) contains these
bits:
•
Timer interrupt enable bits
•
Timer interrupt flags
•
Timer interrupt flag reset bits
•
Timer interrupt rate select bits
Address:
Read:
$0008
Bit 7
6
TOF
RTIF
5
4
TOIE
RTIE
Write:
Reset:
0
0
0
= Unimplemented
0
3
2
TOFR
RTIFR
U
U
1
Bit 0
RT1
RT0
1
1
U = Unaffected
Figure 8-2. Timer Status and Control Register (TSCR)
TOF — Timer Overflow Flag
This read-only flag becomes set when the first eight stages of the
counter roll over from $FF to $00. TOF generates a timer overflow
interrupt request if TOIE is also set. Clear TOF by writing a logic 1 to
the TOFR bit. Writing to TOF has no effect. Reset clears TOF.
RTIF — Real-Time Interrupt Flag
This read-only flag becomes set when the selected real-time interrupt
(RTI) output becomes active. RTIF generates a real-time interrupt
request if RTIE is also set. Clear RTIF by writing a logic 1 to the
RTIFR bit. Writing to RTIF has no effect. Reset clears RTIF.
TOIE — Timer Overflow Interrupt Enable Bit
This read/write bit enables timer overflow interrupts. Reset clears
TOIE.
1 = Timer overflow interrupts enabled
0 = Timer overflow interrupts disabled
MC68HC705K1 — Rev. 2.0
Technical Data
Multifunction Timer
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Multifunction Timer
RTIE — Real-Time Interrupt Enable Bit
This read/write bit enables real-time interrupts. Reset clears RTIE.
1 = Real-time interrupts enabled
0 = Real-time interrupts disabled
TOFR — Timer Overflow Flag Reset
Writing a logic 1 to this write-only bit clears the TOF bit. TOFR always
reads as a logic 0. Reset does not affect TOFR.
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RTIFR — Real-Time Interrupt Flag Reset
Writing a logic 1 to this write-only bit clears the RTIF bit. RTIFR
always reads as a logic 0. Reset does not affect RTIFR.
RT1 and RT0 — Real-Time Interrupt Select Bits 1 and 0
These read/write bits select one of four real-time interrupt rates, as
shown in Table 8-1. Because the selected RTI output drives the COP
watchdog, changing the real-time interrupt rate also changes the
counting rate of the COP watchdog. Reset sets RT1 and RT0,
selecting the longest COP timeout period and RTI period.
NOTE:
Changing RT1 and RT0 when a COP timeout is imminent or uncertain
may cause an RTI request to be missed or an additional RTI request to
be generated. Clear the COP timer just before changing RT1 and RT0.
Table 8-1. Real-Time Interrupt Rate Selection
RT1:RT0
Number
of Cycles
to RTI
RTI
Period(1)
Number
of Cycles
to COP Reset
COP Timeout
Period(1)
00
214 = 16,384
8.2 ms
217 = 131,072
65.5 ms
01
215 = 32,768
16.4 ms
218 = 262,144
131.1 ms
10
216 = 65,536
32.8 ms
219 = 524,288
262.1 ms
11
217 = 131,072
65.5 ms
220 = 1,048,576
524.3 ms
1. At 2-MHz bus, 4-MHz XTAL, 0.5 µs per cycle
Technical Data
MC68HC705K1 — Rev. 2.0
Multifunction Timer
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Multifunction Timer
Timer Counter Register
8.4 Timer Counter Register
A 15-stage ripple counter is the core of the timer. The value of the first
eight stages is readable at any time from the read-only timer counter
register (TCNTR).
Address:
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Read:
$0009
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
Write:
Reset:
= Unimplemented
Figure 8-3. Timer Counter Register (TCNTR)
Power-on clears the entire counter chain and begins clocking the
counter. After 4064 cycles, the power-on reset circuit is released,
clearing the counter again and allowing the MCU to come out of reset.
A timer overflow function at the eighth counter stage allows a timer
interrupt every 1024 internal clock cycles.
Each count of the timer counter register takes eight oscillator cycles or
four cycles of the internal clock.
MC68HC705K1 — Rev. 2.0
Technical Data
Multifunction Timer
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Multifunction Timer
8.5 COP Watchdog
Four counter stages at the end of the timer make up the mask-optional
computer operating properly (COP) watchdog. The COP watchdog is a
software error detection system that automatically times out and resets
the MCU if not cleared periodically by a program sequence. Writing a
logic 0 to bit 0 of the COP register clears the COP watchdog and
prevents a COP reset.
Freescale Semiconductor, Inc...
Address:
$03F0
Bit 7
6
5
4
3
2
1
Bit 0
Read:
COPC
Write:
Reset:
U
U
U
= Unimplemented
U
U
U
U
0
U = Unaffected
Figure 8-4. COP Register (COPR)
COPC — COP Clear Bit
This write-only bit resets the COP watchdog. Reading address $03F0
returns the read-only memory (ROM) data at that address.
The COP watchdog is active in the run, wait, and halt modes of
operation if the COPEN bit in the mask option register is set.
The STOP instruction disables the COP watchdog by clearing the
counter and turning off its clock source. In applications that depend
on the COP watchdog, the STOP instruction can be disabled by
programming the SWAIT bit to a logic 1 in the mask option register. In
applications that have wait cycles longer than the COP timeout
period, the COP watchdog can be disabled by not programming the
COPEN bit to a logic 1 in the mask option register.
NOTE:
If the voltage on the IRQ/VPP pin exceeds 2 × VDD, the COP watchdog
turns off and remains off until the IRQ/VPP voltage falls below 2 × VDD.
Technical Data
MC68HC705K1 — Rev. 2.0
Multifunction Timer
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Multifunction Timer
COP Watchdog
Table 8-2 summarizes recommended conditions for enabling and
disabling the COP watchdog.
Freescale Semiconductor, Inc...
Table 8-2. COP Watchdog Recommendations
Voltage on
IRQ/VPP Pin
SWAIT
Bit(1)
Wait/Halt Time
Recommended
COP Watchdog
Condition
Less than 2 × VDD
1
Less than COP timeout period
Enabled(2)
Less than 2 × VDD
1
Greater than COP timeout period
Disabled
Less than 2 × VDD
0
More than 2 × VDD
X
(3)
X
X
Disabled
Automatically
disabled
1. The SWAIT bit in the mask option register converts STOP instructions to HALT instructions.
2. Reset the COP watchdog immediately before executing the WAIT/HALT instruction.
3. X = Don’t care
MC68HC705K1 — Rev. 2.0
Technical Data
Multifunction Timer
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Freescale Semiconductor, Inc...
Multifunction Timer
Technical Data
MC68HC705K1 — Rev. 2.0
Multifunction Timer
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Freescale Semiconductor, Inc.
Technical Data — MC68HC705K1
Section 9. EPROM/OTPROM
Freescale Semiconductor, Inc...
9.1 Contents
9.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
9.3
EPROM Programming Register . . . . . . . . . . . . . . . . . . . . . . . .84
9.4
EPROM/OTPROM Programming . . . . . . . . . . . . . . . . . . . . . . .85
9.5
EPROM Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
9.6
Mask Option Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
9.2 Introduction
This section describes how to program the 504-byte erasable,
programmable read-only memory (EPROM)/one-time programmable
read-only memory (OTPROM).
NOTE:
In packages with no quartz window, the 504 bytes of EPROM function
as an OTPROM.
MC68HC705K1 — Rev. 2.0
Technical Data
EPROM/OTPROM
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Freescale Semiconductor, Inc.
EPROM/OTPROM
9.3 EPROM Programming Register
The EPROM programming register (EPROG) contains the control bits
for programming the EPROM/OTPROM. In normal operation, the
EPROM programming register is a read-only register that contains all
logic 0s.
Address:
$0018
Bit 7
6
5
4
3
2
1
Bit 0
R
R
R
R
R
ELAT
MPGM
EPGM
U
U
U
U
U
0
0
0
R
= Reserved
Freescale Semiconductor, Inc...
Read:
Write:
Reset:
U = Unaffected
Figure 9-1. EPROM Programming Register (EPROG)
ELAT — EPROM Bus Latch Bit
This read/write bit configures address and data buses for
programming the EPROM/OTPROM array. EPROM/OTPROM data
cannot be read when ELAT is set. Clearing the ELAT bit also clears
the EPGM bit. Reset clears ELAT.
1 = Address and data buses configured for EPROM/OTPROM
programming
0 = Address and data buses configured for normal operation
MPGM — Mask Option Register (MOR) Programming Bit
This read/write bit applies programming power from the IRQ/VPP pin
to the MOR. Reset clears MPGM.
1 = MOR programming power switched on
0 = MOR programming power switched off
EPGM — EPROM Programming Bit
This read/write bit applies the voltage from the IRQ/VPP pin to the
EPROM/OTPROM. To write the EPGM bit, the ELAT bit must already
be set. Reset clears EPGM.
1 = EPROM/OTPROM programming power switched on
0 = EPROM/OTPROM programming power switched off
Technical Data
MC68HC705K1 — Rev. 2.0
EPROM/OTPROM
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EPROM/OTPROM
EPROM/OTPROM Programming
NOTE:
Writing logic 1s to both the ELAT and EPGM bits with a single instruction
sets ELAT and clears EPGM. ELAT must be set first by a separate
instruction.
Bits 7–3 — Reserved
Bits 7–3 are factory test bits that always read as logic 0s.
9.4 EPROM/OTPROM Programming
Freescale Semiconductor, Inc...
The MC68HC705K1 does not contain built-in bootloader ROM code. To
program this device, use an external programming system such as the
M68HC705KICS evaluation module (EVM) or an M68HC705K1GANG
programmer.
Factory-provided software for programming the EPROM/OTPROM is
available through the Motorola web site at:
htt://mcu.motsps.com
The programming software copies to the 496-byte space located at
EPROM/OTPROM addresses $0200–$03EF, to the 8-byte space at
addresses $03F8–$03FF, and to the mask option register at address
$0017.
Figure 9-2 shows the circuit used to download to the on-chip
EPROM/OTPROM using the factory-provided programming software.
This sequence shows the steps in programming a byte of
EPROM/OTPROM:
1. Switch S1 powers up the MC68HC705K1.
2. Software synchronizes the external oscillator to the internal clock.
3. Switch S2 applies VPP to the IRQ/VPP pin.
4. Software sets the ELAT bit.
5. Software writes to an EPROM/OTPROM address.
6. Software sets the EPGM bit for a time tEPGM to apply the
programming voltage.
7. Software clears the ELAT bit.
NOTE:
To program the EPROM/OTPROM, VDD must be greater than 4.5 Vdc.
MC68HC705K1 — Rev. 2.0
Technical Data
EPROM/OTPROM
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EPROM/OTPROM
VCC
2.2 kΩ
VCC
Freescale Semiconductor, Inc...
2.2 kΩ
1
14
2
15
3
16
4
17
5
18
6
19
7
20
8
21
9
22
10
23
11
24
12
25
13
STROBE
220 Ω
MC68HC705K1
1
2
3
4
5
6
7
8
D0
D1
INIT
D2
D3
RESET
PB1
PB0
IRQ/VPP
PA0
PA1
PA2
PA3
OSC1
OSC2
VSS
VDD
PA7
PA6
PA5
PA4
16
15
14
13
12
11
10
9
0.1µF
VCC
DIP SOCKET
D4
D5
D6
D7
MC68HC705K1
1
2
3
4
5
6
7
8
ACK
PE
0.1 µF
RESET
PB1
PB0
IRQ/VPP
PA0
PA1
PA2
PA3
OSC1
OSC2
VSS
VDD
PA7
PA6
PA5
PA4
16
15
14
13
12
11
10
9
SOIC SOCKET
170 µH
5V
VCC
330 Ω
4.7 Ω
S1
10 µF
+
10 µF
+
IN5817
8
1
DR COL
SW COL
7
2
SENSE
SW EMIT
6
3
VCC
CAP
5
4
COMPARE
GND
0.1 µF
5 kΩ
100 pF
MC34063
100 Ω
15 kΩ
VPP
1.5 kΩ
OPTIONAL VPP GENERATOR
S2
10 µH
0.1 µF
100 Ω
10 µF
+
0.1 µF
10 µF
+
Figure 9-2. Programming Circuit
Technical Data
MC68HC705K1 — Rev. 2.0
EPROM/OTPROM
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Freescale Semiconductor, Inc.
EPROM/OTPROM
EPROM Erasing
9.5 EPROM Erasing
MCUs with windowed packages permit EPROM erasure with ultraviolet
light. Erase the EPROM by exposing it to 15 Ws/cm2 of ultraviolet light
with a wave length of 2537 angstroms. Position the ultraviolet light
source 1 inch from the window. Do not use a shortwave filter. The erased
state of an EPROM bit is a logic 0.
Freescale Semiconductor, Inc...
9.6 Mask Option Register
The mask option register (MOR) is an EPROM/OTPROM byte that
controls these options:
•
Port A and port B programmable pulldown devices (enable or
disable)
•
Oscillator connections (2-pin or 3-pin RC oscillator)
•
Oscillator connections (RC oscillator or crystal/ceramic resonator)
•
STOP instruction (enable or disable)
•
Low-voltage reset (enable or disable)
•
Port A external interrupt function (enable or disable)
•
IRQ trigger sensitivity (edge-triggered only or both edge- and
level-triggered)
•
COP watchdog (enable or disable)
The mask option register is unaffected by reset. The erased state of the
mask option register is $0000.
Address:
$0017
Bit 7
6
5
4
3
2
1
Bit 0
SWPDI
PIN3
RC
SWAIT
LVRE
PIRQ
LEVEL
COPEN
0
0
0
Read:
Write:
Reset:
Erased:
Unaffected by reset
0
0
0
0
0
Figure 9-3. Mask Option Register (MOR)
MC68HC705K1 — Rev. 2.0
Technical Data
EPROM/OTPROM
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EPROM/OTPROM
SWPDI —Software Pulldown Inhibit Bit
This EPROM bit inhibits software control of the port A and port B
pulldown devices.
1 = Software pulldown inhibited
0 = Software pulldown enabled
PIN3 — 3-Pin RC Oscillator Bit
Freescale Semiconductor, Inc...
This EPROM bit configures the on-chip oscillator as either a 3-pin
oscillator or as a 2-pin oscillator. The PIN3 bit should be cleared when
the RC bit is clear.
1 = 3-pin oscillator configured
0 = 2-pin oscillator configured
RC — RC Oscillator Bit
This EPROM bit configures the on-chip oscillator for an external RC
network.
1 = Oscillator configured for external RC network
0 = Oscillator configured for external crystal, ceramic resonator, or
clock source
SWAIT — STOP Conversion to WAIT Bit
This EPROM bit disables the STOP instruction and prevents
inadvertently turning off the COP watchdog with a STOP instruction.
When the SWAIT bit is set, a STOP instruction puts the MCU in halt
mode. Halt mode is a low-power state similar to wait mode. The
internal oscillator and timer clock continue to run, but the CPU clock
stops. When the SWAIT bit is clear, a STOP instruction stops the
internal oscillator, the internal clock, the CPU clock, and the timer
clock.
1 = STOP instruction converted to WAIT instruction
0 = STOP instruction not converted to WAIT instruction
LVRE — Low-Voltage Reset Enable Bit
This EPROM bit enables the low-voltage reset (LVR) circuit.
1 = LVR circuit enabled
0 = LVR circuit disabled
Technical Data
MC68HC705K1 — Rev. 2.0
EPROM/OTPROM
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EPROM/OTPROM
Mask Option Register
PIRQ — Port A IRQ Enable Bit
This EPROM bit enables the PA3–PA0 pins to function as external
interrupt sources.
1 = PA3–PA0 enabled as external interrupt sources
0 = PA3–PA0 not enabled as external interrupt sources
Freescale Semiconductor, Inc...
LEVEL — External Interrupt Sensitivity Bit
This EPROM bit makes the external interrupt inputs level-triggered as
well as edge-triggered.
1 = IRQ/VPP pin negative-edge triggered and low-level triggered;
PA3–PA0 pins positive-edge triggered and high-level triggered
0 = IRQ/VPP pin negative-edge triggered only; PA3–PA0 pins
positive-edge triggered only
COPEN — COP Watchdog Enable Bit
This EPROM bit enables the COP watchdog.
1 = COP watchdog enabled
0 = COP watchdog disabled
NOTE:
In 3-pin RC oscillator configurations, the personality EPROM
(PEPROM) cannot be programmed by user software. If the voltage on
IRQ/VPP is raised above VDD, the oscillator will revert to a 2-pin oscillator
configuration and device operation will be disrupted.
MC68HC705K1 — Rev. 2.0
Technical Data
EPROM/OTPROM
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Freescale Semiconductor, Inc...
EPROM/OTPROM
Technical Data
MC68HC705K1 — Rev. 2.0
EPROM/OTPROM
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Technical Data — MC68HC705K1
Section 10. Personality EPROM (PEPROM)
10.1 Contents
Freescale Semiconductor, Inc...
10.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
10.3 PEPROM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
10.3.1 PEPROM Bit Select Register . . . . . . . . . . . . . . . . . . . . . . . .93
10.3.2 PEPROM Status and Control Register. . . . . . . . . . . . . . . . .95
10.4
PEPROM Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
10.5
PEPROM Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
10.6
PEPROM Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
10.2 Introduction
This section describes how to program the 64-bit personality erasable,
programmable read-only memory (PEPROM). Figure 10-1 shows the
structure of the PEPROM subsystem.
MC68HC705K1 — Rev. 2.0
Technical Data
Personality EPROM (PEPROM)
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Personality EPROM (PEPROM)
INTERNAL DATA BUS
0
0
0
0
PEPRZF
PEDATA
RESET
VPP
ROW 0
ROW 1
ROW 2
ROW 3
ROW 4
ROW 5
ROW 6
COL 7
COL 6
COL 5
COL 4
COL 3
COL 2
COL 1
COL 0
ROW 7
8-TO-1 COLUMN DECODER
AND MULTIPLEXER
VPP SWITCH
8-TO-1 ROW DECODER
AND MULTIPLEXER
VPP SWITCH
PEB0
PEB1
PEB2
PEB3
PEB4
PEB5
0
ROW ZERO
DECODER
0
Freescale Semiconductor, Inc...
SINGLE
SENSE
AMPLIFIER
PEPGM
0
PEPROM STATUS/CONTROL REGISTER
PEPROM STATUS/CONTROL REGISTER
RESET
INTERNAL DATA BUS
Figure 10-1. Personality EPROM
Technical Data
MC68HC705K1 — Rev. 2.0
Personality EPROM (PEPROM)
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Personality EPROM (PEPROM)
PEPROM Registers
10.3 PEPROM Registers
Two input/output (I/O) registers control programming and reading of the
PEPROM:
•
PEPROM bit select register (PEBSR)
•
PEPROM status and control register (PESCR)
Freescale Semiconductor, Inc...
10.3.1 PEPROM Bit Select Register
The PEPROM bit select register (PEBSR) selects one of 64 bits in the
PEPROM array. Reset clears all the bits in the PEPROM bit select
register.
Address:
$000E
Bit 7
6
5
4
3
2
1
Bit 0
PEB7
PEB6
PEB5
PEB4
PEB3
PEB2
PEB1
PEB0
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Figure 10-2. PEPROM Bit Select Register (PEBSR)
PEB7 and PEB6 — Not Connected to the PEPROM Array
These read/write bits are available as storage locations. Reset clears
PEB7 and PEB6.
PEB5–PEB0 — PEPROM Bit Select Bits
These read/write bits select one of 64 bits in the PEPROM as shown
in Table 10-1. Bits PEB2–PEB0 select the PEPROM row, and bits
PEB5–PEB3 select the PEPROM column. Reset clears PEB5–PEB0,
selecting the PEPROM bit in row zero, column zero.
MC68HC705K1 — Rev. 2.0
Technical Data
Personality EPROM (PEPROM)
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Personality EPROM (PEPROM)
Table 10-1. PEPROM Bit Selection
Freescale Semiconductor, Inc...
PEBSR
PEPROM Bit Selected
$00
Row 0
Column 0
$01
Row 1
Column 0
$02
Row 2
Column 0
$07
Row 7
Column 0
$08
Row 0
Column 1
$09
Row 1
Column 1
$0A
Row 2
Column 1
$0F
Row 7
Column 1
$10
Row 0
Column 2
$11
Row 1
Column 2
$12
Row 2
Column 2
$37
Row 7
Column 6
$38
Row 0
Column 7
$39
Row 1
Column 7
$3A
Row 2
Column 7
$3B
Row 3
Column 7
$3C
Row 4
Column 7
$3D
Row 5
Column 7
$3E
Row 6
Column 7
$3F
Row 7
Column 7
Technical Data
MC68HC705K1 — Rev. 2.0
Personality EPROM (PEPROM)
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Personality EPROM (PEPROM)
PEPROM Registers
10.3.2 PEPROM Status and Control Register
The PEPROM status and control register (PESCR) controls the
PEPROM programming voltage. This register also transfers the
PEPROM bits to the internal data bus and contains a row zero flag.
Address:
$000F
Bit 7
6
5
4
3
2
1
0
PEPGM
0
0
0
0
0
0
0
0
0
0
Read: PEDATA
Bit 0
PEPRZF
Freescale Semiconductor, Inc...
Write:
Reset:
U
= Unimplemented
1
U = Unaffected
Figure 10-3. PEPROM Status and Control Register (PESCR)
PEDATA — PEPROM Data Bit
This read-only bit is the state of the PEPROM sense amplifier and
shows the state of the currently selected bit. Reset does not affect the
PEDATA bit.
1 = PEPROM data logic 1
0 = PEPROM data logic 0
PEPGM — PEPROM Program Control Bit
This read/write bit controls the switches that apply the programming
voltage, VPP, to the selected PEPROM cell. Reset clears PEPGM.
1 = Programming voltage applied
0 = Programming voltage not applied
PEPRZF — PEPROM Row Zero Flag
This read-only bit is set when the PEPROM bit select register selects
the first row (row zero) of the PEPROM array. Selecting any other row
clears PEPRZF. Monitoring PEPRZF can reduce the code needed to
access one byte of PEPROM. Reset sets PEPRZF.
1 = Row zero selected
0 = Row zero not selected
MC68HC705K1 — Rev. 2.0
Technical Data
Personality EPROM (PEPROM)
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Personality EPROM (PEPROM)
10.4 PEPROM Programming
Factory-provided software for programming the PEPROM is available
through the Motorola web site at:
htt://mcu.motsps.com
The circuit shown in Figure 9-2. Programming Circuit can be used to
program the PEPROM with the factory-provided programming software.
Freescale Semiconductor, Inc...
NOTE:
To program the PEPROM, VDD must be greater than 4.5 Vdc.
The PEPROM can also be programmed by user software with VPP
applied to the IRQ/VPP pin. This sequence shows how to program each
PEPROM bit:
1. Select a PEPROM bit by writing to PEBSR.
2. Set the PEPGM bit in PESCR.
3. Wait 3 ms.
4. Clear the PEPGM bit.
NOTE:
While the PEPGM bit is set and VPP is applied to the IRQ/VPP pin, do not
access bits that are to be left unprogrammed (erased).
In 3-pin RC oscillator configurations, the PEPROM cannot be
programmed by user software. If the voltage on IRQ/VPP is raised above
VDD, the oscillator will revert to a 2-pin oscillator configuration and
device operation will be disrupted.
10.5 PEPROM Reading
This sequence shows how to read the PEPROM:
1. Select a bit by writing to PEBSR.
2. Read the PEDATA bit in PESCR.
3. Store the PEDATA bit in RAM or in a register.
4. Select another bit by changing PEBSR.
5. Continue reading and storing the PEDATA bits until the required
personality EPROM data is stored.
Technical Data
MC68HC705K1 — Rev. 2.0
Personality EPROM (PEPROM)
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Personality EPROM (PEPROM)
PEPROM Erasing
Reading the PEPROM is easiest when each PEPROM column contains
one byte. Selecting a row 0 bit selects the first bit, and incrementing the
PEPROM bit select register (PEBSR) selects the next row 1 bit from the
same column. Incrementing PEBSR seven more times selects the
remaining bits of the column and selects the row 0 bit of the next column,
setting the row 0 flag, PEPRZF.
Freescale Semiconductor, Inc...
A PEPROM byte that has been read can be transferred to the
personality EPROM bit select register (PEBSR) so that subsequent
reads of the PEBSR quickly yield that PEPROM byte.
10.6 PEPROM Erasing
MCUs with windowed packages permit PEPROM erasure with
ultraviolet light. Erase the PEPROM by exposing it to 15 Ws/cm2 of
ultraviolet light with a wave length of 2537 angstroms. Position the
ultraviolet light source 1 inch from the window. Do not use a shortwave
filter. The erased state of a PEPROM bit is a logic 0.
MC68HC705K1 — Rev. 2.0
Technical Data
Personality EPROM (PEPROM)
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Freescale Semiconductor, Inc...
Personality EPROM (PEPROM)
Technical Data
MC68HC705K1 — Rev. 2.0
Personality EPROM (PEPROM)
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Technical Data — MC68HC705K1
Section 11. Instruction Set
11.1 Contents
Freescale Semiconductor, Inc...
11.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
11.3 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
11.3.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
11.3.2 Immediate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
11.3.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
11.3.4 Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
11.3.5 Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
11.3.6 Indexed, 8-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
11.3.7 Indexed, 16-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
11.3.8 Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
11.4 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
11.4.1 Register/Memory Instructions. . . . . . . . . . . . . . . . . . . . . . .104
11.4.2 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . .105
11.4.3 Jump/Branch Instructions. . . . . . . . . . . . . . . . . . . . . . . . . .106
11.4.4 Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . .108
11.4.5 Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
11.5
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
11.6
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
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Instruction Set
11.2 Introduction
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The microcontroller unit (MCU) instruction set has 62 instructions and
uses eight addressing modes. The instructions include all those of the
M146805 CMOS Family plus one more: the unsigned multiply (MUL)
instruction. The MUL instruction allows unsigned multiplication of the
contents of the accumulator (A) and the index register (X). The
high-order product is stored in the index register, and the low-order
product is stored in the accumulator.
11.3 Addressing Modes
The central processor unit (CPU) uses eight addressing modes for
flexibility in accessing data. The addressing modes provide eight
different ways for the CPU to find the data required to execute an
instruction.
The eight addressing modes are:
•
Inherent
•
Immediate
•
Direct
•
Extended
•
Indexed, no offset
•
Indexed, 8-bit offset
•
Indexed, 16-bit offset
•
Relative
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Addressing Modes
11.3.1 Inherent
Inherent instructions are those that have no operand, such as return
from interrupt (RTI) and stop (STOP). Some of the inherent instructions
act on data in the CPU registers, such as set carry flag (SEC) and
increment accumulator (INCA). Inherent instructions require no operand
address and are one byte long.
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11.3.2 Immediate
Immediate instructions are those that contain a value to be used in an
operation with the value in the accumulator or index register. Immediate
instructions require no operand address and are two bytes long. The
opcode is the first byte, and the immediate data value is the second byte.
11.3.3 Direct
Direct instructions can access any of the first 256 memory locations with
two bytes. The first byte is the opcode, and the second is the low byte of
the operand address. In direct addressing, the CPU automatically uses
$00 as the high byte of the operand address.
11.3.4 Extended
Extended instructions use three bytes and can access any address in
memory. The first byte is the opcode; the second and third bytes are the
high and low bytes of the operand address.
When using the Motorola assembler, the programmer does not need to
specify whether an instruction is direct or extended. The assembler
automatically selects the shortest form of the instruction.
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11.3.5 Indexed, No Offset
Indexed instructions with no offset are 1-byte instructions that can
access data with variable addresses within the first 256 memory
locations. The index register contains the low byte of the effective
address of the operand. The CPU automatically uses $00 as the high
byte, so these instructions can address locations $0000–$00FF.
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Indexed, no offset instructions are often used to move a pointer through
a table or to hold the address of a frequently used RAM or I/O location.
11.3.6 Indexed, 8-Bit Offset
Indexed, 8-bit offset instructions are 2-byte instructions that can access
data with variable addresses within the first 511 memory locations. The
CPU adds the unsigned byte in the index register to the unsigned byte
following the opcode. The sum is the effective address of the operand.
These instructions can access locations $0000–$01FE.
Indexed 8-bit offset instructions are useful for selecting the kth element
in an n-element table. The table can begin anywhere within the first 256
memory locations and could extend as far as location 510 ($01FE). The
k value is typically in the index register, and the address of the beginning
of the table is in the byte following the opcode.
11.3.7 Indexed, 16-Bit Offset
Indexed, 16-bit offset instructions are 3-byte instructions that can access
data with variable addresses at any location in memory. The CPU adds
the unsigned byte in the index register to the two unsigned bytes
following the opcode. The sum is the effective address of the operand.
The first byte after the opcode is the high byte of the 16-bit offset; the
second byte is the low byte of the offset.
Indexed, 16-bit offset instructions are useful for selecting the kth element
in an n-element table anywhere in memory.
As with direct and extended addressing, the Motorola assembler
determines the shortest form of indexed addressing.
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Instruction Types
11.3.8 Relative
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Relative addressing is only for branch instructions. If the branch
condition is true, the CPU finds the effective branch destination by
adding the signed byte following the opcode to the contents of the
program counter. If the branch condition is not true, the CPU goes to the
next instruction. The offset is a signed, two’s complement byte that gives
a branching range of –128 to +127 bytes from the address of the next
location after the branch instruction.
When using the Motorola assembler, the programmer does not need to
calculate the offset, because the assembler determines the proper offset
and verifies that it is within the span of the branch.
11.4 Instruction Types
The MCU instructions fall into five categories:
•
Register/memory instructions
•
Read-modify-write instructions
•
Jump/branch instructions
•
Bit manipulation instructions
•
Control instructions
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Instruction Set
11.4.1 Register/Memory Instructions
These instructions operate on CPU registers and memory locations.
Most of them use two operands. One operand is in either the
accumulator or the index register. The CPU finds the other operand in
memory.
Table 11-1. Register/Memory Instructions
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Instruction
Mnemonic
Add memory byte and carry bit to accumulator
ADC
Add memory byte to accumulator
ADD
AND memory byte with accumulator
AND
Bit test accumulator
BIT
Compare accumulator
CMP
Compare index register with memory byte
CPX
Exclusive OR accumulator with memory byte
EOR
Load accumulator with memory byte
LDA
Load Index register with memory byte
LDX
Multiply
MUL
OR accumulator with memory byte
ORA
Subtract memory byte and carry bit from
accumulator
SBC
Store accumulator in memory
STA
Store index register in memory
STX
Subtract memory byte from accumulator
SUB
Technical Data
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Instruction Types
11.4.2 Read-Modify-Write Instructions
These instructions read a memory location or a register, modify its
contents, and write the modified value back to the memory location or to
the register.
NOTE:
Do not use read-modify-write operations on write-only registers.
Table 11-2. Read-Modify-Write Instructions
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Instruction
Mnemonic
Arithmetic shift left (same as LSL)
ASL
Arithmetic shift right
ASR
Bit clear
BCLR(1)
Bit set
BSET(1)
Clear register
CLR
Complement (one’s complement)
COM
Decrement
DEC
Increment
INC
Logical shift left (same as ASL)
LSL
Logical shift right
LSR
Negate (two’s complement)
NEG
Rotate left through carry bit
ROL
Rotate right through carry bit
ROR
Test for negative or zero
TST(2)
1. Unlike other read-modify-write instructions, BCLR and BSET use
only direct addressing.
2. TST is an exception to the read-modify-write sequence because it
does not write a replacement value.
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11.4.3 Jump/Branch Instructions
Jump instructions allow the CPU to interrupt the normal sequence of the
program counter. The unconditional jump instruction (JMP) and the
jump-to-subroutine instruction (JSR) have no register operand. Branch
instructions allow the CPU to interrupt the normal sequence of the
program counter when a test condition is met. If the test condition is not
met, the branch is not performed.
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The BRCLR and BRSET instructions cause a branch based on the state
of any readable bit in the first 256 memory locations. These 3-byte
instructions use a combination of direct addressing and relative
addressing. The direct address of the byte to be tested is in the byte
following the opcode. The third byte is the signed offset byte. The CPU
finds the effective branch destination by adding the third byte to the
program counter if the specified bit tests true. The bit to be tested and its
condition (set or clear) is part of the opcode. The span of branching is
from –128 to +127 from the address of the next location after the branch
instruction. The CPU also transfers the tested bit to the carry/borrow bit
of the condition code register.
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Instruction Set
Instruction Types
Table 11-3. Jump and Branch Instructions
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Instruction
Mnemonic
Branch if carry bit clear
BCC
Branch if carry bit set
BCS
Branch if equal
BEQ
Branch if half-carry bit clear
BHCC
Branch if half-carry bit set
BHCS
Branch if higher
BHI
Branch if higher or same
BHS
Branch if IRQ pin high
BIH
Branch if IRQ pin low
BIL
Branch if lower
BLO
Branch if lower or same
BLS
Branch if interrupt mask clear
BMC
Branch if minus
BMI
Branch if interrupt mask set
BMS
Branch if not equal
BNE
Branch if plus
BPL
Branch always
BRA
Branch if bit clear
Branch never
Branch if bit set
BRCLR
BRN
BRSET
Branch to subroutine
BSR
Unconditional jump
JMP
Jump to subroutine
JSR
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11.4.4 Bit Manipulation Instructions
The CPU can set or clear any writable bit in the first 256 bytes of
memory, which includes I/O registers and on-chip RAM locations. The
CPU can also test and branch based on the state of any bit in any of the
first 256 memory locations.
Table 11-4. Bit Manipulation Instructions
Instruction
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Bit clear
Mnemonic
BCLR
Branch if bit clear
BRCLR
Branch if bit set
BRSET
Bit set
Technical Data
BSET
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Instruction Types
11.4.5 Control Instructions
These instructions act on CPU registers and control CPU operation
during program execution.
Table 11-5. Control Instructions
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Instruction
Mnemonic
Clear carry bit
CLC
Clear interrupt mask
CLI
No operation
NOP
Reset stack pointer
RSP
Return from interrupt
RTI
Return from subroutine
RTS
Set carry bit
SEC
Set interrupt mask
SEI
Stop oscillator and enable IRQ pin
STOP
Software interrupt
SWI
Transfer accumulator to index register
TAX
Transfer index register to accumulator
TXA
Stop CPU clock and enable interrupts
WAIT
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11.5 Instruction Set Summary
ADD #opr
ADD opr
ADD opr
ADD opr,X
ADD opr,X
ADD ,X
AND #opr
AND opr
AND opr
AND opr,X
AND opr,X
AND ,X
ASL opr
ASLA
ASLX
ASL opr,X
ASL ,X
↕
IMM
DIR
EXT
IX2
IX1
IX
A9 ii
2
B9 dd 3
C9 hh ll 4
D9 ee ff 5
E9 ff
4
F9
3
↕
IMM
DIR
EXT
IX2
IX1
IX
AB ii
2
BB dd 3
CB hh ll 4
DB ee ff 5
EB ff
4
FB
3
↕ —
IMM
DIR
EXT
IX2
IX1
IX
A4 ii
2
B4 dd 3
C4 hh ll 4
D4 ee ff 5
E4 ff
4
F4
3
38
48
58
68
78
dd
↕
DIR
INH
INH
IX1
IX
DIR
INH
INH
IX1
IX
37
47
57
67
77
dd
REL
24
rr
3
11
13
15
17
19
1B
1D
1F
dd
dd
dd
dd
dd
dd
dd
dd
5
5
5
5
5
5
5
5
H I N Z C
A ← (A) + (M) + (C)
Add with Carry
A ← (A) + (M)
Add without Carry
Arithmetic Shift Left (Same as LSL)
C
BCC rel
Branch if Carry Bit Clear
— — ↕
0
b7
Arithmetic Shift Right
↕ — ↕
A ← (A) ∧ (M)
Logical AND
ASR opr
ASRA
ASRX
ASR opr,X
ASR ,X
↕ — ↕
— — ↕
↕
↕
↕
b0
C
b7
— — ↕
↕
↕
b0
PC ← (PC) + 2 + rel ? C = 0
Mn ← 0
— — — — —
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — —
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
ff
ff
Cycles
Description
Opcode
ADC #opr
ADC opr
ADC opr
ADC opr,X
ADC opr,X
ADC ,X
Operation
Effect
on CCR
Address
Mode
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Source
Form
Operand
Table 11-6. Instruction Set Summary (Sheet 1 of 6)
5
3
3
6
5
5
3
3
6
5
BCLR n opr
Clear Bit n
BCS rel
Branch if Carry Bit Set (Same as BLO)
PC ← (PC) + 2 + rel ? C = 1
— — — — —
REL
25
rr
3
BEQ rel
Branch if Equal
PC ← (PC) + 2 + rel ? Z = 1
— — — — —
REL
27
rr
3
BHCC rel
Branch if Half-Carry Bit Clear
PC ← (PC) + 2 + rel ? H = 0
— — — — —
REL
28
rr
3
BHCS rel
Branch if Half-Carry Bit Set
PC ← (PC) + 2 + rel ? H = 1
— — — — —
REL
29
rr
3
PC ← (PC) + 2 + rel ? C ∨ Z = 0 — — — — —
BHI rel
Branch if Higher
BHS rel
Branch if Higher or Same
PC ← (PC) + 2 + rel ? C = 0
Technical Data
— — — — —
REL
22
rr
3
REL
24
rr
3
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Instruction Set Summary
Address
Mode
Opcode
Operand
Cycles
Table 11-6. Instruction Set Summary (Sheet 2 of 6)
BIH rel
Branch if IRQ Pin High
PC ← (PC) + 2 + rel ? IRQ = 1
— — — — —
REL
2F
rr
3
BIL rel
Branch if IRQ Pin Low
PC ← (PC) + 2 + rel ? IRQ = 0
— — — — —
REL
2E
rr
3
— — ↕
IMM
DIR
EXT
IX2
IX1
IX
A5 ii
2
B5 dd 3
C5 hh ll 4
D5 ee ff 5
E5 ff
4
F5
3
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Source
Form
Operation
Description
BIT #opr
BIT opr
BIT opr
BIT opr,X
BIT opr,X
BIT ,X
Bit Test Accumulator with Memory Byte
BLO rel
Branch if Lower (Same as BCS)
BLS rel
Branch if Lower or Same
BMC rel
Branch if Interrupt Mask Clear
PC ← (PC) + 2 + rel ? I = 0
BMI rel
Branch if Minus
PC ← (PC) + 2 + rel ? N = 1
(A) ∧ (M)
PC ← (PC) + 2 + rel ? C = 1
Effect
on CCR
H I N Z C
↕ —
— — — — —
REL
25
rr
3
PC ← (PC) + 2 + rel ? C ∨ Z = 1 — — — — —
REL
23
rr
3
— — — — —
REL
2C
rr
3
— — — — —
REL
2B
rr
3
BMS rel
Branch if Interrupt Mask Set
PC ← (PC) + 2 + rel ? I = 1
— — — — —
REL
2D
rr
3
BNE rel
Branch if Not Equal
PC ← (PC) + 2 + rel ? Z = 0
— — — — —
REL
26
rr
3
BPL rel
Branch if Plus
PC ← (PC) + 2 + rel ? N = 0
— — — — —
REL
2A
rr
3
BRA rel
Branch Always
PC ← (PC) + 2 + rel ? 1 = 1
— — — — —
REL
20
rr
3
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — ↕
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
01
03
05
07
09
0B
0D
0F
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
— — — — —
BRCLR n opr rel Branch if Bit n Clear
BRN rel
Branch Never
BRSET n opr rel Branch if Bit n Set
BSET n opr
Set Bit n
PC ← (PC) + 2 + rel ? Mn = 0
PC ← (PC) + 2 + rel ? 1 = 0
21
rr
3
PC ← (PC) + 2 + rel ? Mn = 1
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — ↕
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
REL
00
02
04
06
08
0A
0C
0E
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
Mn ← 1
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — —
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
10
12
14
16
18
1A
1C
1E
dd
dd
dd
dd
dd
dd
dd
dd
5
5
5
5
5
5
5
5
PC ← (PC) + 2; push (PCL)
SP ← (SP) – 1; push (PCH)
SP ← (SP) – 1
PC ← (PC) + rel
— — — — —
REL
AD
rr
6
BSR rel
Branch to Subroutine
CLC
Clear Carry Bit
C←0
— — — — 0
INH
98
2
CLI
Clear Interrupt Mask
I←0
— 0 — — —
INH
9A
2
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CMP #opr
CMP opr
CMP opr
CMP opr,X
CMP opr,X
CMP ,X
COM opr
COMA
COMX
COM opr,X
COM ,X
CPX #opr
CPX opr
CPX opr
CPX opr,X
CPX opr,X
CPX ,X
DEC opr
DECA
DECX
DEC opr,X
DEC ,X
EOR #opr
EOR opr
EOR opr
EOR opr,X
EOR opr,X
EOR ,X
INC opr
INCA
INCX
INC opr,X
INC ,X
JMP opr
JMP opr
JMP opr,X
JMP opr,X
JMP ,X
DIR
INH
INH
IX1
IX
3F
4F
5F
6F
7F
dd
↕
IMM
DIR
EXT
IX2
IX1
IX
A1 ii
2
B1 dd 3
C1 hh ll 4
D1 ee ff 5
E1 ff
4
F1
3
↕ 1
DIR
INH
INH
IX1
IX
33
43
53
63
73
↕
IMM
DIR
EXT
IX2
IX1
IX
A3 ii
2
B3 dd 3
C3 hh ll 4
D3 ee ff 5
E3 ff
4
F3
3
↕ —
DIR
INH
INH
IX1
IX
3A
4A
5A
6A
7A
↕ —
IMM
DIR
EXT
IX2
IX1
IX
A8 ii
2
B8 dd 3
C8 hh ll 4
D8 ee ff 5
E8 ff
4
F8
3
↕ —
DIR
INH
INH
IX1
IX
3C
4C
5C
6C
7C
DIR
EXT
IX2
IX1
IX
BC dd 2
CC hh ll 3
DC ee ff 4
EC ff
3
FC
2
Effect
on CCR
H I N Z C
M ← $00
A ← $00
X ← $00
M ← $00
M ← $00
Clear Byte
Compare Accumulator with Memory Byte
Complement Byte (One’s Complement)
Compare Index Register with Memory Byte
EXCLUSIVE OR Accumulator with Memory
Byte
Unconditional Jump
M ← (M) = $FF – (M)
A ← (A) = $FF – (A)
X ← (X) = $FF – (X)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
(X) – (M)
M ← (M) – 1
A ← (A) – 1
X ← (X) – 1
M ← (M) – 1
M ← (M) – 1
Decrement Byte
Increment Byte
(A) – (M)
A ← (A) ⊕ (M)
M ← (M) + 1
A ← (A) + 1
X ← (X) + 1
M ← (M) + 1
M ← (M) + 1
PC ← Jump Address
Technical Data
— — 0 1 —
— — ↕
— — ↕
— — ↕
— — ↕
— — ↕
— — ↕
↕
↕
— — — — —
ff
dd
ff
dd
ff
dd
ff
Cycles
Description
Operand
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CLR opr
CLRA
CLRX
CLR opr,X
CLR ,X
Operation
Opcode
Source
Form
Address
Mode
Table 11-6. Instruction Set Summary (Sheet 3 of 6)
5
3
3
6
5
5
3
3
6
5
5
3
3
6
5
5
3
3
6
5
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Instruction Set Summary
LDA #opr
LDA opr
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
LSL opr
LSLA
LSLX
LSL opr,X
LSL ,X
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
PC ← Effective Address
Jump to Subroutine
A ← (M)
Load Accumulator with Memory Byte
X ← (M)
Load Index Register with Memory Byte
Logical Shift Left (Same as ASL)
— — ↕
↕ —
IMM
DIR
EXT
IX2
IX1
IX
A6 ii
2
B6 dd 3
C6 hh ll 4
D6 ee ff 5
E6 ff
4
F6
3
↕ —
IMM
DIR
EXT
IX2
IX1
IX
AE ii
2
BE dd 3
CE hh ll 4
DE ee ff 5
EE ff
4
FE
3
38
48
58
68
78
dd
↕
DIR
INH
INH
IX1
IX
0
DIR
INH
INH
IX1
IX
34
44
54
64
74
dd
MUL
Unsigned Multiply
0
C
b7
0 — — — 0
INH
42
— — ↕
DIR
INH
INH
IX1
IX
30
40
50
60
70
Negate Byte (Two’s Complement)
NOP
No Operation
— — — — —
INH
9D
— — ↕
↕ —
IMM
DIR
EXT
IX2
IX1
IX
AA ii
2
BA dd 3
CA hh ll 4
DA ee ff 5
EA ff
4
FA
3
M ← –(M) = $00 – (M)
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
A ← (A) ∨ (M)
Logical OR Accumulator with Memory
↕
DIR
INH
INH
IX1
IX
39
49
59
69
79
Rotate Byte Left through Carry Bit
C
— — 0 ↕
— — ↕
b7
↕
↕
b0
X : A ← (X) × (A)
NEG opr
NEGA
NEGX
NEG opr,X
NEG ,X
— — ↕
b0
b0
MC68HC705K1 — Rev. 2.0
↕
↕
↕
ff
ff
Cycles
BD dd 5
CD hh ll 6
DD ee ff 7
ED ff
6
FD
5
— — ↕
C
b7
Logical Shift Right
ROL opr
ROLA
ROLX
ROL opr,X
ROL ,X
— — — — —
DIR
EXT
IX2
IX1
IX
H I N Z C
LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
ORA #opr
ORA opr
ORA opr
ORA opr,X
ORA opr,X
ORA ,X
Description
Opcode
Freescale Semiconductor, Inc...
JSR opr
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
Operation
Effect
on CCR
Address
Mode
Source
Form
Operand
Table 11-6. Instruction Set Summary (Sheet 4 of 6)
5
3
3
6
5
5
3
3
6
5
1
1
dd
ff
5
3
3
6
5
2
dd
ff
5
3
3
6
5
Technical Data
Instruction Set
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Instruction Set
Opcode
Operand
DIR
INH
INH
IX1
IX
36
46
56
66
76
dd
— — — — —
INH
9C
2
Return from Interrupt
SP ← (SP) + 1; Pull (CCR)
SP ← (SP) + 1; Pull (A)
SP ← (SP) + 1; Pull (X)
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
↕
↕
INH
80
9
Return from Subroutine
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
— — — — —
INH
81
6
— — ↕
↕
IMM
DIR
EXT
IX2
IX1
IX
A2 ii
2
B2 dd 3
C2 hh ll 4
D2 ee ff 5
E2 ff
4
F2
3
Freescale Semiconductor, Inc...
Source
Form
Operation
Effect
on CCR
Description
H I N Z C
ROR opr
RORA
RORX
ROR opr,X
ROR ,X
Rotate Byte Right through Carry Bit
RSP
Reset Stack Pointer
SP ← $00FF
RTI
RTS
C
b7
— — ↕
↕
↕
b0
↕
↕
↕
ff
Cycles
Address
Mode
Table 11-6. Instruction Set Summary (Sheet 5 of 6)
5
3
3
6
5
SBC #opr
SBC opr
SBC opr
SBC opr,X
SBC opr,X
SBC ,X
Subtract Memory Byte and Carry Bit from
Accumulator
SEC
Set Carry Bit
C←1
— — — — 1
INH
99
2
SEI
Set Interrupt Mask
I←1
— 1 — — —
INH
9B
2
— — ↕
↕ —
DIR
EXT
IX2
IX1
IX
B7 dd 4
C7 hh ll 5
D7 ee ff 6
E7 ff
5
F7
4
— 0 — — —
INH
8E
— — ↕
↕ —
DIR
EXT
IX2
IX1
IX
BF dd 4
CF hh ll 5
DF ee ff 6
EF ff
5
FF
4
↕
↕
IMM
DIR
EXT
IX2
IX1
IX
A0 ii
2
B0 dd 3
C0 hh ll 4
D0 ee ff 5
E0 ff
4
F0
3
PC ← (PC) + 1; Push (PCL)
SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
— 1 — — —
SP ← (SP) – 1; Push (CCR)
SP ← (SP) – 1; I ← 1
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
INH
83
1
0
INH
97
2
STA opr
STA opr
STA opr,X
STA opr,X
STA ,X
Store Accumulator in Memory
STOP
Stop Oscillator and Enable IRQ Pin
STX opr
STX opr
STX opr,X
STX opr,X
STX ,X
SUB #opr
SUB opr
SUB opr
SUB opr,X
SUB opr,X
SUB ,X
Store Index Register In Memory
Subtract Memory Byte from Accumulator
SWI
Software Interrupt
TAX
Transfer Accumulator to Index Register
A ← (A) – (M) – (C)
M ← (A)
M ← (X)
A ← (A) – (M)
X ← (A)
Technical Data
— — ↕
↕
— — — — —
2
MC68HC705K1 — Rev. 2.0
Instruction Set
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Instruction Set
Opcode Map
Freescale Semiconductor, Inc...
Description
3D
4D
5D
6D
7D
dd
Test Memory Byte for Negative or Zero
TXA
Transfer Index Register to Accumulator
— — — — —
INH
9F
2
WAIT
Stop CPU Clock and Enable Interrupts
— 0 — — —
INH
8F
2
Accumulator
Carry/borrow flag
Condition code register
Direct address of operand
Direct address of operand and relative offset of branch instruction
Direct addressing mode
High and low bytes of offset in indexed, 16-bit offset addressing
Extended addressing mode
Offset byte in indexed, 8-bit offset addressing
Half-carry flag
High and low bytes of operand address in extended addressing
Interrupt mask
Immediate operand byte
Immediate addressing mode
Inherent addressing mode
Indexed, no offset addressing mode
Indexed, 8-bit offset addressing mode
Indexed, 16-bit offset addressing mode
Memory location
Negative flag
Any bit
— — ↕
(M) – $00
A ← (X)
opr
PC
PCH
PCL
REL
rel
rr
SP
X
Z
#
∧
∨
⊕
()
–( )
←
?
:
↕
—
↕ —
ff
Cycles
DIR
INH
INH
IX1
IX
Effect
on CCR
H I N Z C
TST opr
TSTA
TSTX
TST opr,X
TST ,X
A
C
CCR
dd
dd rr
DIR
ee ff
EXT
ff
H
hh ll
I
ii
IMM
INH
IX
IX1
IX2
M
N
n
Operand
Operation
Opcode
Source
Form
Address
Mode
Table 11-6. Instruction Set Summary (Sheet 6 of 6)
4
3
3
5
4
Operand (one or two bytes)
Program counter
Program counter high byte
Program counter low byte
Relative addressing mode
Relative program counter offset byte
Relative program counter offset byte
Stack pointer
Index register
Zero flag
Immediate value
Logical AND
Logical OR
Logical EXCLUSIVE OR
Contents of
Negation (two’s complement)
Loaded with
If
Concatenated with
Set or cleared
Not affected
11.6 Opcode Map
See Table 11-7.
MC68HC705K1 — Rev. 2.0
Technical Data
Instruction Set
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Technical Data
Instruction Set
For More Information On This Product,
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F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
MSB
LSB
1
DIR
2
REL
Branch
3
DIR
4
5
INH
6
IX1
Read-Modify-Write
INH
7
IX
INH = Inherent
IMM = Immediate
DIR = Direct
EXT = Extended
REL = Relative
IX = Indexed, No Offset
IX1 = Indexed, 8-Bit Offset
IX2 = Indexed, 16-Bit Offset
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
EOR
IMM 2
2
ADC
IMM 2
2
ORA
IMM 2
2
ADD
IMM 2
2
2
SUB
IMM 2
2
CMP
IMM 2
2
SBC
IMM 2
2
CPX
IMM 2
2
AND
IMM 2
2
BIT
IMM 2
2
LDA
IMM 2
A
IMM
MSB
0
LSB
0
5
SUB
IX2 2
5
CMP
IX2 2
5
SBC
IX2 2
5
CPX
IX2 2
5
AND
IX2 2
5
BIT
IX2 2
5
LDA
IX2 2
6
STA
IX2 2
5
EOR
IX2 2
5
ADC
IX2 2
5
ORA
IX2 2
5
ADD
IX2 2
4
JMP
IX2 2
7
JSR
IX2 2
5
LDX
IX2 2
6
STX
IX2 2
D
IX2
4
SUB
IX1 1
4
CMP
IX1 1
4
SBC
IX1 1
4
CPX
IX1 1
4
AND
IX1 1
4
BIT
IX1 1
4
LDA
IX1 1
5
STA
IX1 1
4
EOR
IX1 1
4
ADC
IX1 1
4
ORA
IX1 1
4
ADD
IX1 1
3
JMP
IX1 1
6
JSR
IX1 1
4
LDX
IX1 1
5
STX
IX1 1
E
IX1
MSB of Opcode in Hexadecimal
4
SUB
EXT 3
4
CMP
EXT 3
4
SBC
EXT 3
4
CPX
EXT 3
4
AND
EXT 3
4
BIT
EXT 3
4
LDA
EXT 3
5
STA
EXT 3
4
EOR
EXT 3
4
ADC
EXT 3
4
ORA
EXT 3
4
ADD
EXT 3
3
JMP
EXT 3
6
JSR
EXT 3
4
LDX
EXT 3
5
STX
EXT 3
C
EXT
Register/Memory
3
SUB
DIR 3
3
CMP
DIR 3
3
SBC
DIR 3
3
CPX
DIR 3
3
AND
DIR 3
3
BIT
DIR 3
3
LDA
DIR 3
4
STA
DIR 3
3
EOR
DIR 3
3
ADC
DIR 3
3
ORA
DIR 3
3
ADD
DIR 3
2
JMP
DIR 3
5
JSR
DIR 3
3
LDX
DIR 3
4
STX
DIR 3
B
DIR
5 Number of Cycles
BRSET0 Opcode Mnemonic
3
DIR Number of Bytes/Addressing Mode
2
6
BSR
REL 2
2
LDX
2
IMM 2
2
TAX
INH
2
CLC
INH 2
2
SEC
INH 2
2
CLI
INH 2
2
SEI
INH 2
2
RSP
INH
2
NOP
INH 2
9
2
STOP
INH
2
2
TXA
WAIT
INH 1
INH
10
SWI
INH
9
RTI
INH
6
RTS
INH
8
INH
Control
INH
LSB of Opcode in Hexadecimal
5
5
3
5
3
3
6
5
BRSET0
BRA
BSET0
NEG
NEGA
NEGX
NEG
NEG
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX 1
5
5
3
BRCLR0
BRN
BCLR0
3
1
DIR 2
DIR 2
REL
5
11
5
3
BRSET1
MUL
BHI
BSET1
3
1
DIR 2
INH
DIR 2
REL
5
5
3
5
3
3
6
5
BRCLR1
BLS
BCLR1
COM
COMA
COMX
COM
COM
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX 1
5
5
3
5
3
3
6
5
BRSET2
BCC
BSET2
LSR
LSRA
LSRX
LSR
LSR
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
BRCLR2
BCLR2 BCS/BLO
3
DIR 2
DIR 2
REL
5
5
3
5
3
3
6
5
BRSET3
BNE
BSET3
ROR
RORA
RORX
ROR
ROR
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
5
3
3
6
5
BRCLR3
BEQ
BCLR3
ASR
ASRA
ASRX
ASR
ASR
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
5
3
3
6
5
BRSET4
BHCC
BSET4
ASL/LSL ASLA/LSLA ASLX/LSLX ASL/LSL ASL/LSL
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
5
3
3
6
5
BRCLR4
BHCS
BCLR4
ROL
ROLA
ROLX
ROL
ROL
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
5
3
3
6
5
BRSET5
BPL
BSET5
DEC
DECA
DECX
DEC
DEC
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
BRCLR5
BMI
BCLR5
3
DIR 2
DIR 2
REL
5
5
3
5
3
3
6
5
BRSET6
BMC
BSET6
INC
INCA
INCX
INC
INC
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
4
3
3
5
4
BRCLR6
BMS
BCLR6
TST
TSTA
TSTX
TST
TST
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
BRSET7
BIL
BSET7
3
1
DIR 2
DIR 2
REL
5
5
3
5
3
3
6
5
BRCLR7
BIH
BCLR7
CLR
CLRA
CLRX
CLR
CLR
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX 1
0
DIR
Bit Manipulation
Table 11-7. Opcode Map
Freescale Semiconductor, Inc...
STX
LDX
JSR
JMP
ADD
ORA
ADC
EOR
STA
LDA
BIT
AND
CPX
SBC
CMP
SUB
F
IX
3
IX
IX
4
IX
3
IX
5
IX
2
IX
3
IX
3
IX
3
IX
3
IX
4
IX
3
IX
3
IX
3
IX
3
IX
3
IX
3
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
MSB
LSB
Freescale Semiconductor, Inc.
Instruction Set
MC68HC705K1 — Rev. 2.0
Freescale Semiconductor, Inc.
Technical Data — MC68HC705K1
Section 12. Electrical Specifications
Freescale Semiconductor, Inc...
12.1 Contents
12.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
12.3
Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
12.4
Operating Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .118
12.5
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
12.6
Power Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
12.7
Equivalent Pin Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
12.8
5.0-Volt DC Electrical Characteristics. . . . . . . . . . . . . . . . . . .121
12.9
3.3-Volt DC Electrical Characteristics. . . . . . . . . . . . . . . . . . .122
12.10 5.0-Volt Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
12.11 3.3-Volt Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
12.12 Typical Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . .130
12.2 Introduction
This section contains electrical and timing specifications.
MC68HC705K1 — Rev. 2.0
Technical Data
Electrical Specifications
For More Information On This Product,
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Freescale Semiconductor, Inc.
Electrical Specifications
12.3 Maximum Ratings
Maximum ratings are the extreme limits to which the MCU can be
exposed without permanently damaging it.
Freescale Semiconductor, Inc...
The MCU contains circuitry to protect the inputs against damage from
high static voltages; however, do not apply voltages higher than those
shown in the table here. Keep VIn and VOut within the range
VSS ≤ (VIn or VOut) ≤ VDD. Connect unused inputs to the appropriate
voltage level, either VSS or VDD.
Rating(1)
Symbol
Value
Unit
Supply voltage
VDD
–0.3 to +7.0
V
Input voltage
VIn
VSS –0.3
to VDD +0.3
V
EPROM programming voltage
VPP
VDD –0.3 to
16.0
Current drain per pin excluding
VDD and VSS
I
25
mA
TSTG
–65 to +150
°C
Storage temperature range
1. Voltages referenced to VSS
NOTE:
This device is not guaranteed to operate properly at the maximum
ratings. Refer to 12.8 5.0-Volt DC Electrical Characteristics and
12.9 3.3-Volt DC Electrical Characteristics for guaranteed operating
conditions.
12.4 Operating Temperature Range
Rating(1)
Operating temperature range(2)
MC68HC705K1P, DW, S
Symbol
Value
Unit
TA
TL to TH
–40 to +85
°C
MC68HC705K1CP, CDW, CS
1. Voltages referenced to VSS
2. P = Plastic dual in-line package (PDIP)
DW = Small outline integrated circuit (SOIC)
S = Ceramic dual in-line package (cerdip)
C = Extended temperature range (–40°C to +85°C)
Technical Data
MC68HC705K1 — Rev. 2.0
Electrical Specifications
For More Information On This Product,
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Freescale Semiconductor, Inc.
Electrical Specifications
Thermal Characteristics
12.5 Thermal Characteristics
Characteristic
Symbol
Value
Unit
Maximum junction temperature
TJ
150
°C
Thermal resistance
MC68HC705K1P(1)
MC68HC705K1DW(2)
θJA
100
140
°C/W
Freescale Semiconductor, Inc...
1. P = Plastic dual in-line package (PDIP)
2. DW = Small outline integrated circuit (SOIC)
12.6 Power Considerations
The average chip junction temperature, TJ, in °C can be obtained from:
TJ = TA + (PD x θJA)
(1)
Where:
TA = ambient temperature in °C
θJA = package thermal resistance, junction to ambient in °C/W
PD = PINT + PI/O
PINT = ICC × VCC = chip internal power dissipation
PI/O = power dissipation on input and output pins (user-determined)
For most applications, PI/O < PINT and can be neglected.
Ignoring PI/O, the relationship between PD and TJ is approximately:
K
PD =
(2)
TJ + 273°C
Solving equations (1) and (2) for K gives:
= PD x (TA + 273°C) + θJA x (PD)2
(3)
where K is a constant pertaining to the particular part. K can be
determined from equation (3) by measuring PD (at equilibrium) for a
known TA. Using this value of K, the values of PD and TJ can be obtained
by solving equations (1) and (2) iteratively for any value of TA.
MC68HC705K1 — Rev. 2.0
Technical Data
Electrical Specifications
For More Information On This Product,
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Freescale Semiconductor, Inc.
Electrical Specifications
12.7 Equivalent Pin Loading
Figure 12-1 shows the equivalent input/output (I/O) pin loading for test
purposes.
VDD
R2
Freescale Semiconductor, Inc...
TEST POINT
C
R1
PINS
VDD
PA3–PA0, PB1–PB0
4.5 V
PA7–PA4
PA3–PA0, PB1–PB0
3.0 V
R1
R2
C
3.26 kΩ
2.38 kΩ
50 pF
470 Ω
2.38 kΩ
50 pF
10.91 kΩ
6.32 kΩ
50 pF
Figure 12-1. Equivalent Test Load
Technical Data
MC68HC705K1 — Rev. 2.0
Electrical Specifications
For More Information On This Product,
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Freescale Semiconductor, Inc.
Electrical Specifications
5.0-Volt DC Electrical Characteristics
12.8 5.0-Volt DC Electrical Characteristics
Characteristic(1)
Symbol
Min
Typ(2)
Max
Unit
VOL
VOH
—
VDD – 0.1
—
—
0.1
—
V
VOH
VDD – 0.8
—
—
V
VOL
—
—
—
—
0.4
0.4
V
Input high voltage
PA7–PA0, PB1/OSC3, PB0, IRQ/VPP, RESET, OSC1
VIH
0.7 x VDD
—
VDD
V
Input low voltage
PA7–PA0, PB1/OSC3, PB0, IRQ/VPP, RESET, OSC1
VIL
VSS
—
0.2 x VDD
V
—
—
2.6
0.9
—
—
mA
mA
—
—
—
200
700
1000
—
—
—
nA
nA
nA
IOZ
—
—
±10
µA
IIL
50
75
200
µA
—
—
1.0
—
—
4.0
±1
±1
8.0
µA
µA
mA
COut
CIn
—
—
—
—
12
8
pF
VLVR
2.8
3.5
4.5
V
ROSC
1.0
2.0
3.0
MΩ
VPP
17.0
17.5
18.0
V
IPP
—
5
10
mA
Output voltage
ILoad = 10.0 µA
ILoad = –10.0 µA
Freescale Semiconductor, Inc...
Output high voltage, ILoad = –0.8 mA
PA7–PA0, PB1/OSC3, PB0
Output low voltage
ILoad = 1.6 mA, PA3–PA0, PB1/OSC3, PB0
ILoad = 8.0 mA, PC7–PC4
Supply current
Run(3)
Wait(4)
Stop(5)
25°C
0°C to +70°C (standard)
–40°C to +85°C (extended)
I/O ports hi-z leakage current
PA7–PA0, PB1/OSC3, PB0 (pulldown devices off)
Input pulldown current
PA7–PA0, PB1/OSC3, PB0 (pulldown devices on)
Input current
IRQ/VPP, OSC1
RESET (pulldown devices off)
RESET (pulldown devices on)
Capacitance
Ports (input or output)
RESET, IRQ/VPP
Low-voltage reset threshold(6)
Oscillator internal resistor (OSC1 to OSC2)
voltage(7)
Programming
Programming current
IDD
IIn
1. VDD = 5.0 V ±10%; VSS = 0 Vdc, TA = TL to TH, unless otherwise noted
2. Typical values reflect average measurements at midpoint of voltage range at 25°C.
3. Run (operating) IDD measured using external square wave clock source (fOSC = 4.2 MHz). All inputs 0.2 V from rail. No dc
loads. Less than 50 pF on all outputs. CL = 20 pF on OSC2.
4. Wait IDD measured using external square wave clock source (fOSC = 4.2 MHz). All inputs 0.2 V from rail. No dc loads. Less
than 50 pF on all outputs. CL = 20 pF on OSC2. VIL = 0.2 V, VIH = VDD – 0.2 V. OSC2 capacitance linearly affects wait IDD.
5. Stop IDD measured with OSC1 = VDD. All ports configured as inputs. VIL = 0.2 V, VIH = VDD – 0.2 V. With low-voltage reset
enabled, stop IDD can be as high as 25 µA.
6. All MCUs guaranteed to operate at VDD = 5 V ±10%. Each MCU guaranteed to operate at its VLVR.
7. Programming voltage measured at IRQ/VPP pin.
MC68HC705K1 — Rev. 2.0
Technical Data
Electrical Specifications
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Electrical Specifications
12.9 3.3-Volt DC Electrical Characteristics
Characteristic(1)
Symbol
Min
Typ(2)
Max
Unit
VOL
VOH
—
VDD – 0.1
—
—
0.1
—
V
Output high voltage, ILoad = –0.4 mA
PA7–PA0, PB1/OSC3, PB0
VOH
VDD – 0.3
—
—
V
Output low voltage
ILoad = 0.4 mA, PA3–PA0, PB1/OSC3, PB0
ILoad = 3.0 mA, PC7–PC4
VOL
—
—
—
—
0.3
0.3
V
Input high voltage
PA7–PA0, PB1/OSC3, PB0, IRQ/VPP, RESET, OSC1
VIH
0.7 x VDD
—
VDD
V
Input low voltage
PA7–PA0, PB1/OSC3, PB0, IRQ/VPP, RESET, OSC1
VIL
VSS
—
0.2 x VDD
V
—
—
0.7
300
—
—
mA
µA
—
—
—
50
500
1000
—
—
—
nA
nA
nA
Freescale Semiconductor, Inc...
Output voltage
ILoad = 10.0 µA
ILoad = –10.0 µA
Supply current
Run(3)
Wait(4)
Stop(5)
25°C
0°C to +70°C (standard)
–40°C to +85°C (extended)
IDD
I/O ports hi-z leakage current
PA7–PA0, PB1/OSC3, PB0 (pulldown devices off)
IOZ
—
—
±10
µA
Input pulldown current
PA7–PA0, PB1/OSC3, PB0 (pulldown devices on)
IIL
10
20
100
µA
Input current
IRQ/VPP, OSC1
RESET (pulldown devices off)
RESET (pulldown devices on)
IIn
—
—
0.2
—
—
2.0
±1
±1
4.0
µA
µA
mA
Capacitance
Ports (input or output)
RESET, IRQ/VPP
COut
CIn
—
—
—
—
12
8
pF
Oscillator internal resistor (OSC1 to OSC2)
ROSC
1.0
2.0
3.0
MΩ
1. VDD = 3.3 V ±10%; VSS = 0 Vdc, TA = TL to TH, unless otherwise noted
2. Typical values reflect average measurements at midpoint of voltage range at 25°C.
3. Run (operating) IDD measured using external square wave clock source (fOSC = 2.0 MHz). All inputs 0.2 V from rail. No dc
loads. Less than 50 pF on all outputs. CL = 20 pF on OSC2.
4. Wait IDD measured using external square wave clock source (fOSC = 2.0 MHz). All inputs 0.2 V from rail. No dc loads. Less
than 50 pF on all outputs. CL = 20 pF on OSC2. VIL = 0.2 V, VIH = VDD – 0.2 V. OSC2 capacitance linearly affects wait IDD.
5. Stop IDD measured with OSC1 = VDD. All ports configured as inputs. VIL = 0.2 V, VIH = VDD – 0.2 V. With low-voltage reset
enabled, stop IDD can be as high as 25 µA.
Technical Data
MC68HC705K1 — Rev. 2.0
Electrical Specifications
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Freescale Semiconductor, Inc.
Electrical Specifications
3.3-Volt DC Electrical Characteristics
VDD = 5.0 V
VDD = 3.3 V
0.8
0.8
0.6
0.6
0.5
0.5
VDD – VOH (V)
0.7
0.4
0.3
0.4
(NOTE 3)
0.3
0.2
0.2
0.1
0.1
0
0
0
–1.0
–2.0
–3.0
–4.0
–5.0
0
–1.0
–2.0
IOH (mA)
–3.0
–4.0
–5.0
IOH (mA)
Notes:
1. Shaded area indicates variation in driver characteristics due to changes in temperature and for normal processing tolerances.
Within the limited range of values shown, V versus I curves are approximately straight lines.
2. At VDD = 5.0 V, devices are specified and tested for VOL ≤ 800 mV @ IOL = –0.8 mA.
3. At VDD = 3.3 V, devices are specified and tested for VOL ≤ 300 mV @ IOL = –0.2 mA.
Figure 12-2. Typical High-Side Driver Characteristics
VDD = 5.0 V
VDD = 3.3 V
0.40
0.40
(NOTE 2)
0.35
0.35
0.30
0.30
0.25
0.25
VOL (V)
VOL (V)
Freescale Semiconductor, Inc...
VDD – VOH (V)
(NOTE 2)
0.7
0.20
0.15
0.20
0.15
0.10
0.10
0.05
0.05
0
(NOTE 3)
0
0
2.0
4.0
6.0
8.0
10.0
0
2.0
4.0
IOL (mA)
6.0
8.0
10.0
IOL (mA)
Notes:
1. Shaded area indicates variation in driver characteristics due to changes in temperature and for normal processing tolerances.
Within the limited range of values shown, V versus I curves are approximately straight lines.
2. At VDD = 5.0 V, devices are specified and tested for VOL ≤ 400 mV @ IOL = 1.6 mA.
3. At VDD = 3.3 V, devices are specified and tested for VOL ≤ 300 mV @ IOL = 0.4 mA.
Figure 12-3. Typical Low-Side Driver Characteristics
MC68HC705K1 — Rev. 2.0
Technical Data
Electrical Specifications
For More Information On This Product,
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Freescale Semiconductor, Inc.
Electrical Specifications
T = 25°C
3.0
2.5
5.5 V
4.5 V
Freescale Semiconductor, Inc...
SUPPLY CURRENT (mA)
2.0
3.6 V
3.0 V
1.5
1.0
0.5
0
0
0.5
1.0
1.5
2.0
INTERNAL CLOCK FREQUENCY (MHz)
Figure 12-4. Run IDD versus Internal Clock Frequency
T = 25°C
900
800
700
5.5 V
4.5 V
SUPPLY CURRENT (µA)
600
3.6 V
500
3.0 V
400
300
200
100
0
0
0.5
1.0
1.5
2.0
INTERNAL CLOCK FREQUENCY (MHz)
Figure 12-5. Wait IDD versus Internal Clock Frequency
Technical Data
MC68HC705K1 — Rev. 2.0
Electrical Specifications
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Freescale Semiconductor, Inc.
Electrical Specifications
3.3-Volt DC Electrical Characteristics
2500
2000
SUPPLY CURRENT (nA)
5.5 V
4.5 V
1500
3.6 V
3.0 V
1000
Freescale Semiconductor, Inc...
500
0
0
20
40
60
80
100
TEMPERATURE (°C)
Figure 12-6. Stop IDD versus Temperature
MC68HC705K1 — Rev. 2.0
Technical Data
Electrical Specifications
For More Information On This Product,
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Freescale Semiconductor, Inc.
Electrical Specifications
12.10 5.0-Volt Control Timing
Freescale Semiconductor, Inc...
Characteristic(1)
Symbol
Oscillator frequency
3-pin RC oscillator
2-pin RC oscillator
Crystal/ceramic resonator(2)
External clock
fOSC
Internal operating frequency (fOSC ÷ 2)
3-pin RC oscillator
2-pin RC oscillator
Crystal/ceramic resonator
External clock
fOP
Min
Max
(3)
1.2
2.4
4.0
4.0
(3)
0.500
dc
0.250
dc
0.6
1.2
2.0
2.0
(3)
(3)
Unit
MHz
MHz
2-pin RC oscillator frequency combined stability(4)
fOSC = 2.0 MHz; VDD = 5.0 Vdc ±10%; TA = –40°C to +85°C
fOSC = 2.0 MHz; VDD = 5.0 Vdc ±10%; TA = 0°C to +40°C
∆fOSC
—
—
±25
±20
%
3-pin RC oscillator frequency combined stability(4)
fOSC = 1.0 MHz; VDD = 5.0 Vdc ±10%; TA = –40°C to +85°C
fOSC = 1.0 MHz; VDD = 5.0 Vdc ±10%; TA = 0°C to +40°C
∆fOSC
—
—
±15
±10
%
tCYC
500
—
ns
RC oscillator stabilization time
tRCON
—
1
ms
Crystal oscillator startup time
tOXON
—
100
ms
Stop recovery startup time
tILCH
—
100
ms
tRL
1.5
—
tCYC
tRESL
4.0
—
tCYC
IRQ interrupt pulse width low (edge-triggered)
tILIH
250
—
ns
IRQ interrupt pulse period
tILIL
(6)
—
tCYC
PA3–PA0 interrupt pulse width high (edge-triggered)
tIHIL
250
—
ns
PA3–PA0 interrupt pulse period
tIHIH
(6)
—
tCYC
tOH, tOL
200
—
ns
tEPGM
10
15
ms
Cycle time (1 ÷ fOP)
RESET pulse width low
Timer resolution(5)
OSC1 pulse width
Programming time per byte(7)
1. VDD = 5.0 Vdc ±10%; VSS –0 Vdc; TA = TL to TH
2. Use only AT-cut crystals.
3. Minimum oscillator frequency with RC oscillator option is limited only by size of external R and C and leakage of external C.
4. Including processing tolerances and variations in temperature and supply voltage. Excluding tolerances of external R
and C.
5. The 2-bit timer prescaler is the limiting factor in determining timer resolution.
6. The minimum period, tILIL or tIHIH, should not be less than the number of cycles it takes to execute the interrupt service
routine plus 19 tCYC.
7. tEPGM is programming time per byte and may be accumulated during multiple programming passes.
Technical Data
MC68HC705K1 — Rev. 2.0
Electrical Specifications
For More Information On This Product,
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Freescale Semiconductor, Inc.
Electrical Specifications
3.3-Volt Control Timing
12.11 3.3-Volt Control Timing
Freescale Semiconductor, Inc...
Characteristic(1)
Symbol
Oscillator frequency
3-pin RC oscillator
2-pin RC oscillator
Crystal/ceramic resonator(2)
External clock
fOSC
Internal operating frequency (fOSC ÷ 2)
3-pin RC oscillator
2-pin RC oscillator
Crystal/ceramic resonator
External clock
fOP
Min
Max
(3)
1.2
2.0
2.0
2.0
(3)
0.500
dc
0.250
dc
0.6
1.0
1.0
1.0
(3)
(3)
Unit
MHz
MHz
2-pin RC oscillator frequency combined stability(4)
fOSC = 2.0 MHz; VDD = 3.3 Vdc ±10%; TA = –40°C to +85°C
fOSC = 2.0 MHz; VDD = 3.3 Vdc ±10%; TA = 0°C to +40°C
∆fOSC
—
—
±40
±30
%
3-pin RC oscillator frequency combined stability(4)
fOSC = 1.0 MHz; VDD = 3.3 Vdc ±10%; TA = –40°C to +85°C
fOSC = 1.0 MHz; VDD = 3.3 Vdc ±10%; TA = 0°C to +40°C
∆fOSC
—
—
±20
±15
%
tCYC
1000
—
ns
RC oscillator stabilization time
tRCON
—
1
ms
Crystal oscillator startup time
tOXON
—
100
ms
Stop recovery startup time
tILCH
—
100
ms
tRL
1.5
—
tCYC
tRESL
4.0
—
tCYC
IRQ interrupt pulse width low (edge-triggered)
tILIH
250
—
ns
IRQ interrupt pulse period
tILIL
(6)
—
tCYC
PA3–PA0 interrupt pulse width high (edge-triggered)
tIHIL
250
—
ns
PA3–PA0 interrupt pulse period
tIHIH
(6)
—
tCYC
tOH, tOL
200
—
ns
Cycle time (1 ÷ fOP)
RESET pulse width low
Timer resolution(5)
OSC1 pulse width
1. VDD = 3.3 Vdc ±10%; VSS –0 Vdc; TA = TL to TH
2. Use only AT-cut crystals.
3. Minimum oscillator frequency with RC oscillator option is limited only by size of external R and C and leakage of external C.
4. Including processing tolerances and variations in temperature and supply voltage. Excluding tolerances of external R
and C.
5. The 2-bit timer prescaler is the limiting factor in determining timer resolution.
6. The minimum period, tILIL or tIHIH, should not be less than the number of cycles it takes to execute the interrupt service
routine plus 19 tCYC.
MC68HC705K1 — Rev. 2.0
Technical Data
Electrical Specifications
For More Information On This Product,
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Freescale Semiconductor, Inc.
Electrical Specifications
tILIL
tILIH
IRQ/VPP PIN
tILIH
IRQ1
.
.
.
IRQn
Freescale Semiconductor, Inc...
IRQ (INTERNAL)
Figure 12-7. External Interrupt Timing
OSC (NOTE 1)
tRL
RESET
tILIH
IRQ/VPP (NOTE 2)
4064 tCYC
IRQ/VPP (NOTE 3)
INTERNAL
CLOCK
INTERNAL
ADDRESS BUS
03FE
(NOTE 4)
03FE
03FE
03FE
Notes:
1. Internal clocking from OSC1 pin.
2. Edge-triggered external interrupt mask option.
3. Edge- and level-triggered external interrupt mask option.
4. Reset vector shown as example.
03FE
03FF
RESET OR INTERRUPT
VECTOR FETCH
Figure 12-8. Stop Mode Recovery Timing
Technical Data
MC68HC705K1 — Rev. 2.0
Electrical Specifications
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Freescale Semiconductor, Inc.
Electrical Specifications
3.3-Volt Control Timing
VDD
(NOTE 1)
4064 tCYC
OSC1 PIN
INTERNAL
CLOCK
Freescale Semiconductor, Inc...
INTERNAL
ADDRESS BUS
03FE
03FE
03FE
03FE
03FE
03FE
INTERNAL
DATA BUS
03FF
NEW
PCH
NEW
PCL
Notes:
1. Power-on reset threshold is typically between 1 V and 2 V.
2. Internal clock, internal address bus, and internal data bus are not available externally.
Figure 12-9. Power-On Reset Timing
INTERNAL
CLOCK
INTERNAL
ADDRESS BUS
03FE
03FE
03FE
03FE
NEW
PCH
INTERNAL
DATA BUS
03FF
NEW
PCL
NEW PC
DUMMY
NEW PC
OP
CODE
tRL
Notes:
1. Internal clock, internal address bus, and internal data bus are not available externally.
2. The next rising edge of the internal clock after the rising edge of RESET initiates the reset sequence.
Figure 12-10. External Reset Timing
MC68HC705K1 — Rev. 2.0
Technical Data
Electrical Specifications
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Freescale Semiconductor, Inc.
Electrical Specifications
12.12 Typical Oscillator Characteristics
Parameter
Oscillator Type
Nominal Frequency
VDD = 3.0 V
VDD = 5.0 V
Units
Freescale Semiconductor, Inc...
Frequency Variation
(Part-to-Part)
2-pin RC oscillator
2 MHz
±12
±7
3-pin RC oscillator
1 MHz
±5
±4
%
Frequency Variation
with Temperature
2-pin RC oscillator
2 MHz
–2100
–1600
3-pin RC oscillator
1 MHz
–1100
–1100
ppm/°C
Frequency Variation
with Supply Voltage
2-pin RC oscillator
2 MHz
±1.0
±0.2
3-pin RC oscillator
1 MHz
±0.3
±0.1
∆f/∆V
Cumulative Frequency
Variations(1)
2-pin RC oscillator
2 MHz
±36
±20
3-pin RC oscillator
1 MHz
±16
±13
%
1. VDD ±10%; TA = –40°C to +85°C.
Technical Data
MC68HC705K1 — Rev. 2.0
Electrical Specifications
For More Information On This Product,
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Freescale Semiconductor, Inc.
Electrical Specifications
Typical Oscillator Characteristics
T = 25°C
10 pF
Freescale Semiconductor, Inc...
OSCILLATOR FREQUENCY (MHz)
4
20 pF
3
2
1
0
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
R (kΩ)
Figure 12-11. 2-Pin RC Oscillator R versus Frequency (VDD = 5.0 V)
T = 25°C
10 pF
OSCILLATOR FREQUENCY (kHz)
1000
20 pF
800
600
400
200
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
R (kΩ)
Figure 12-12. 3-Pin RC Oscillator R versus Frequency (VDD = 5.0 V)
MC68HC705K1 — Rev. 2.0
Technical Data
Electrical Specifications
For More Information On This Product,
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Freescale Semiconductor, Inc.
Electrical Specifications
T = 25°C
10 pF
Freescale Semiconductor, Inc...
OSCILLATOR FREQUENCY (MHz)
4
20 pF
3
2
1
0
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
R (kΩ)
Figure 12-13. 2-Pin Oscillator R versus Frequency (VDD = 3.0 V)
T = 25°C
10 pF
OSCILLATOR FREQUENCY (kHz)
1000
20 pF
800
600
400
200
0
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
R (kΩ)
Figure 12-14. 3-Pin Oscillator R versus Frequency (VDD = 3.0 V)
Technical Data
MC68HC705K1 — Rev. 2.0
Electrical Specifications
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Freescale Semiconductor, Inc.
Technical Data — MC68HC705K1
Section 13. Mechanical Specifications
Freescale Semiconductor, Inc...
13.1 Contents
13.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
13.3
Plastic Dual In-Line Package (Case 648) . . . . . . . . . . . . . . . .134
13.4
Small Outline Integrated Circuit (Case 751) . . . . . . . . . . . . . .134
13.5
Ceramic Dual In-Line Package (Case 620) . . . . . . . . . . . . . .135
13.2 Introduction
Package dimensions available at the time of this publication for the
MC68HC705K1 are provided in this section. The packages are:
•
16-pin plastic dual in-line package (PDIP)
•
16-pin small outline integrated circuit package (SOIC)
•
16-pin ceramic DIP (cerdip)
To make sure that you have the latest case outline specifications,
contact one of the following:
•
Local Motorola Sales Office
•
Motorola Mfax
– Phone 602-244-6609
– EMAIL [email protected]
•
Worldwide Web (wwweb) at http://www.mcu.motsps.com
Follow Mfax or wwweb on-line instructions to retrieve the current
mechanical specifications.
MC68HC705K1 — Rev. 2.0
Technical Data
Mechanical Specifications
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Mechanical Specifications
13.3 Plastic Dual In-Line Package (Case 648)
-A16
9
1
8
B
INCHES
DIM
F
C
A
B
C
D
F
G
H
J
K
L
M
S
L
Freescale Semiconductor, Inc...
S
-T-
SEATING
PLANE
K
H
M
J
G
D
16 PL
0.25 (0.010) M T A M
MIN
MAX
0.740
0.770
0.250
0.270
0.145
0.175
0.015
0.021
0.040
0.70
0.100 BSC
0.050 BSC
0.008
0.015
0.110
0.130
0.295
0.305
0°
10°
0.020
0.040
MILLIMETERS
MIN
MAX
18.80 19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.02
1.77
2.54 BSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
7.74
0°
10°
0.51
1.01
13.4 Small Outline Integrated Circuit (Case 751)
-A16
9
-B-
8X
P
0.010 (0.25) M
1
DIM
A
B
C
D
F
G
J
K
M
P
R
B
M
8
J
D 16X
0.010 (0.25) M T A
S
B S
F
R
MILLIMETERS
INCHES
MIN
MAX
10.15
10.45
7.40
7.60
2.35
2.65
0.35
0.49
0.50
0.90
1.27 BSC
0.25
0.32
0.10
0.25
0°
7°
10.05
10.55
0.25
0.75
MIN
MAX
0.400
0.411
0.292
0.299
0.093
0.104
0.014
0.019
0.020
0.035
0.050 BSC
0.010
0.012
0.004
0.009
0°
7°
0.395
0.415
0.010
0.029
X 45
C
-TG 14X
K
SEATING
PLANE
M
Technical Data
MC68HC705K1 — Rev. 2.0
Mechanical Specifications
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Mechanical Specifications
Ceramic Dual In-Line Package (Case 620)
13.5 Ceramic Dual In-Line Package (Case 620)
B
A
A
M
16
9
1
8
Freescale Semiconductor, Inc...
B
L
16X
0.25 (0.010)
E
M
J
T B
F
C
K
T
N
SEATING
PLANE
G
16X
0.25 (0.010)
M
D
T A
MC68HC705K1 — Rev. 2.0
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
DIM
A
B
C
D
E
F
G
H
K
L
M
N
INCHES
MIN
MAX
0.750
0.785
0.240
0.295
–––
0.200
0.015
0.020
0.050 BSC
0.055
0.065
0.100 BSC
0.008
0.015
0.125
0.170
0.300 BSC
0_
15 _
0.020
0.040
STYLE 1:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
MILLIMETERS
MIN
MAX
19.05
19.93
6.10
7.49
–––
5.08
0.39
0.50
1.27 BSC
1.40
1.65
2.54 BSC
0.21
0.38
3.18
4.31
7.62 BSC
0_
15 _
0.51
1.01
CATHODE
CATHODE
CATHODE
CATHODE
CATHODE
CATHODE
CATHODE
CATHODE
ANODE
ANODE
ANODE
ANODE
ANODE
ANODE
ANODE
ANODE
Technical Data
Mechanical Specifications
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Freescale Semiconductor, Inc...
Mechanical Specifications
Technical Data
MC68HC705K1 — Rev. 2.0
Mechanical Specifications
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Technical Data — MC68HC705K1
Section 13. Ordering Information
Freescale Semiconductor, Inc...
13.1 Contents
13.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
13.3
MCU Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
13.2 Introduction
This section contains ordering information for the available package
types.
13.3 MCU Order Numbers
Table 13-1 lists the MC order numbers.
Table 13-1. MC68HC705K1 Order Numbers
Package Type
Temperature Range
Order Number
16-pin plastic dual in-line package (PDIP)
0°C to +70°C
MC68HC705K1P(1)
16-pin small outline integrated circuit (SOIC)
0°C to +70°C
MC68HC705K1DW(2)
16-pin ceramic dual in-line package (cerdip)
0°C to +70°C
MC68HC705K1S(3)
16-pin plastic dual in-line package (PDIP)
–40°C to +85°C
MC68HC705K1CP(4)
16-pin small outline integrated circuit (SOIC)
–40°C to +85°C
MC68HC705K1CDW
16-pin ceramic dual in-line package (cerdip)
–40°C to +85°C
MC68HC705K1CS
1. P = Plastic dual in-line package (PDIP)
2. DW = Small outline integrated circuit (SOIC)
3. S = Ceramic dual in-line package (cerdip)
4. C = Extended temperature range (–40°C to +85°C)
MC68HC705K1 — Rev. 2.0
Technical Data
Ordering Information
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Freescale Semiconductor, Inc...
Ordering Information
Technical Data
MC68HC705K1 — Rev. 2.0
Ordering Information
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Go to: www.freescale.com
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
For More Information On This Product,
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Freescale Semiconductor, Inc...
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