FREESCALE MC9S08AC96

Freescale Semiconductor
Data Sheet: Advanced Information
Document Number: MC9S08AC128
Rev. 1, 9/2008
MC9S08AC128 8-Bit
Microcontroller Data Sheet
MC9S08AC128
840B-01
This document contains information on a new
product. Specifications and information herein
are subject to change without notice.
8-Bit HCS08 Central Processor Unit (CPU)
•
40-MHz HCS08 CPU (central processor unit)
•
20-MHz internal bus frequency
•
HC08 instruction set with added BGND, CALL and
RTC instructions
•
Memory Management Unit to support paged
memory.
•
Linear Address Pointer to allow direct page data
accesses of the entire memory map
Development Support
•
Background debugging system
•
Breakpoint capability to allow single breakpoint
setting during in-circuit debugging (plus two more
breakpoints in on-chip debug module)
•
On-chip in-circuit emulator (ICE) Debug module
containing three comparators and nine trigger
modes. Eight deep FIFO for storing change-of-flow
addresses and event-only data. Supports both tag
and force breakpoints.
Memory Options
•
Up to 128K FLASH — read/program/erase over full
operating voltage and temperature
•
Up to 8K Random-access memory (RAM)
•
Security circuitry to prevent unauthorized access to
RAM and FLASH contents
Clock Source Options
•
Clock source options include crystal, resonator,
external clock, or internally generated clock with
precision NVM trimming using ICG module
System Protection
•
Optional computer operating properly (COP) reset
with option to run from independent internal clock
source or bus clock
•
CRC module to support fast cyclic redundancy
checks on system memory
•
Low-voltage detection with reset or interrupt
•
Illegal opcode detection with reset
•
Master reset pin and power-on reset (POR)
824D-02
917A-03
Power-Saving Modes
•
Wait plus two stops
Peripherals
•
ADC — 16-channel, 10-bit resolution, 2.5 μs
conversion time, automatic compare function,
temperature sensor, internal bandgap reference
channel
•
SCIx — Two serial communications interface
modules supporting LIN 2.0 Protocol and SAE J2602
protocols; Full duplex non-return to zero (NRZ);
Master extended break generation; Slave extended
break detection; Wakeup on active edge
•
SPIx — One full and one master-only serial
peripheral interface modules; Full-duplex or
single-wire bidirectional; Double-buffered transmit
and receive; Master or Slave mode; MSB-first or
LSB-first shifting
•
IIC — Inter-integrated circuit bus module; Up to 100
kbps with maximum bus loading; Multi-master
operation; Programmable slave address; Interrupt
driven byte-by-byte data transfer; supports broadcast
mode and 10 bit addressing
•
TPMx — One 2-channel and two 6-channel 16-bit
timer/pulse-width modulator (TPM) modules:
Selectable input capture, output compare, and
edge-aligned PWM capability on each channel. Each
timer module may be configured for buffered,
centered PWM (CPWM) on all channels
•
KBI — 8-pin keyboard interrupt module
Input/Output
•
Up to 70 general-purpose input/output pins
•
Software selectable pullups on input port pins
•
Software selectable drive strength and slew rate
control on ports when used as outputs
Package Options
•
80-pin low-profile quad flat package (LQFP)
•
64-pin quad flat package (QFP)
•
44-pin low-profile quad flat package (LQFP)
This document contains information on a new product. Specifications and information herein
are subject to change without notice.
© Freescale Semiconductor, Inc., 2007-2008. All rights reserved.
Preliminary — Subject to Change
Table of Contents
Chapter 1
Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.1 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Chapter 2
Pins and Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
2.1 Device Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . .5
Chapter 3
Electrical Characteristics and Timing Specifications . . . . . . .11
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.2 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . .11
3.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . .11
3.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .13
3.5 ESD Protection and Latch-Up Immunity . . . . . . . . . . . .14
3.6 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3.7 Supply Current Characteristics . . . . . . . . . . . . . . . . . . .18
3.8 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .21
3.9 Internal Clock Generation Module Characteristics . . . .24
3.9.1 ICG Frequency Specifications . . . . . . . . . . . . .
3.10 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.10.1 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . .
3.10.2 Timer/PWM (TPM) Module Timing. . . . . . . . . .
3.11 SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.12 FLASH Specifications . . . . . . . . . . . . . . . . . . . . . . . . .
3.13 EMC Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.13.1 Radiated Emissions . . . . . . . . . . . . . . . . . . . . .
3.13.2 Conducted Transient Susceptibility . . . . . . . . .
Chapter 4
Ordering Information and Mechanical Drawings . . . . . . . . . .
4.1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2 Orderable Part Numbering System . . . . . . . . . . . . . . .
4.3 Mechanical Drawings. . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 5
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25
27
27
28
30
33
34
34
34
37
37
37
37
39
Related Documentation
MC9S08AC128 Series Reference Manual (MC9S08AC128RM)
contains extensive product information including modes of operartion, memory, resets and interrupts, register definitions, port pins, CPU, and all peripheral module information.
For the latest version of the documentation, check our website at:
http://www.freescale.com
MC9S08AC128 MCU Series Data Sheet, Rev. 1
2
Freescale Semiconductor
Preliminary — Subject to Change
Chapter 1
Device Overview
The MC9S08AC128 is a member of the low-cost, high-performance HCS08 Family of 8-bit
microcontroller units (MCUs). The MC9S08AC128 uses the enhanced HCS08 core.
1.1
MCU Block Diagram
The block diagram in Figure 1-1 shows the structure of the MC9S08AC128 Series MCU.
MC9S08AC128 MCU Series Data Sheet, Rev. 1
Freescale Semiconductor
3
Preliminary — Subject to Change
Chapter 1 Device Overview
HCS08 CORE
IRQ
LVD
VDDAD
EXTAL
XTAL
LOW-POWER OSC
8-BIT KEYBOARD
INTERRUPT MODULE (KBI1)
10-BIT
ANALOG-TO-DIGITAL
CONVERTER (ADC)
VSSAD
VREFL
VREFH
USERMEMORY
FLASH, RAM
(BYTES)
(AW128 = 128K, 8K)
(AW96 = 96K, 6K)
VDD
AD1P15–AD1P0
IIC MODULE (IIC1)
SCL
SDA
SERIAL COMMUNICATIONS
INTERFACE MODULE (SCI1)
RXD1
TXD1
SERIAL COMMUNICATIONS
INTERFACE MODULE (SCI2)
RXD2
TXD2
PTG6/EXTAL
PTG5/XTAL
PTG4/KBI1P4
PTG3/KBI1P3
PTG2/KBI1P2
PTG1/KBI1P1
PTG0/KBIP0
PORT J
PTC0/SCL1
SPSCK1
MOSI1
SERIAL PERIPHERAL
INTERFACE MODULE (SPI1)
SERIAL PERIPHERAL
INTERFACE MODULE (SPI2)
PORT H
PTH6/MISO2
PTH5/MOSI2
PTH4/SPSCK2
PTH3/TPM2CH5
PTH2/TPM2CH4
PTH1/TPM2CH3
PTH0/TPM2CH2
PORT G
PTJ7
PTJ6
PTJ5
PTJ4
PTJ3
PTJ2
PTJ1
PTJ0
PTC6
PTC5/RxD2
PTC4
PTC3/TxD2
PTC2/MCLK
PTC1/SDA1
KBI1P7–KBI1P0
VOLTAGE REGULATOR
VSS
PORT A
COP
PORT B
RTI
PTB7/AD1P7
PTB6/AD1P6
PTB5/AD1P5
PTB4/AD1P4
PTB3/AD1P3
PTB2/AD1P2
PTB1/TPM3CH1/AD1P1
PTB0/TPM3CH0/AD1P0
INTERNAL CLOCK
GENERATOR (ICG)
6-CHANNEL TIMER/PWM
MODULE (TPM1)
6-CHANNEL TIMER/PWM
MODULE (TPM2)
2-CHANNEL TIMER/PWM
MODULE (TPM3)
- Pin not connected in 64-pin and 48-pin packages
PTD7/KBI1P7/AD1P15
PTD6/TPM1CLK/AD1P14
PTD5/AD1P13
PTD4/TPM2CLK/AD1P12
PTD3/KBI1P6/AD1P11
PTD2/KBI1P5/AD1P10
PTD1/AD1P9
PTD0/AD1P8
MISO1
PTE7/SPSCK1
SS1
PTE6/MOSI1
PTE5/MISO1
SPSCK2
MOSI2
MISO2
PTE4/SS1
PORT E
RQ/TPMCLK
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
PORT C
HCS08 SYSTEM CONTROL
RESET
CYCLIC REDUNDANCY
CHECK MODULE (CRC)
PORT D
CPU
PTA7
PTA6
PTA5
PTA4
PTA3
PTA2
PTA1
PTA0
TPM1CLK or TPMCLK
TPM1CH0–TPM1CH5
TPM2CLK or TPMCLK
TPM2CH0–TPM2CH5
TPMCLK
TPM3CH1
TPM3CH0
PORT F
BDC
BKGD/MS
DEBUG
MODULE (DBG)
PTE3/TPM1CH1
PTE2/TPM1CH0
PTE1/RxD1
PTE0/TxD1
PTF7
PTF6
PTF5/TPM2CH1
PTF4/TPM2CH0
PTF3/TPM1CH5
PTF2/TPM1CH4
PTF1/TPM1CH3
PTF0/TPM1CH2
- Pin not connected in 48-pin package
Figure 1-1. MC9S08AC128 Series Block Diagram
MC9S08AC128 MCU Series Data Sheet, Rev. 1
4
Freescale Semiconductor
Preliminary — Subject to Change
Chapter 2
Pins and Connections
This section describes signals that connect to package pins. It includes pinout diagrams, recommended
system connections, and detailed discussions of signals.
2.1
Device Pin Assignment
80-Pin
LQFP
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
PTG3/KBI1P3
PTD3/KBI1P6/AD1P11
PTD2/KBI1P5/AD1P10
VSSAD
VDDAD
PTD1/AD1P9
PTD0/AD1P8
PTB7/AD1P7
PTB6/AD1P6
PTB5/AD1P5
PTB4/AD1P4
PTB3/AD1P3
PTB2/AD1P2
PTB1/TPM3CH1/AD1P1
PTB0/TPM3CH0/AD1P0
PTH3/TPM2CH5
PTH2/TPM2CH4
PTH1/TPM2CH3
PTH0/TPM2CH2
PTA7
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
PTE4/SS1
PTE5/MISO1
PTE6/MOSI1
PTE7/SPSCK1
VSS
VDD
PTJ4
PTJ5
PTJ6
PTJ7
PTG0/KBI1P0
PTG1/KBI1P1
PTG2/KBI1P2
PTA0
PTA1
PTA2
PTA3
PTA4
PTA5
PTA6
PTC4
IRQ/TPMCLK
RESET
PTF0/TPM1CH2
PTF1/TPM1CH3
PTF2/TPM1CH4
PTF3/TPM1CH5
PTF4/TPM2CH0
PTC6
PTF7
PTF5/TPM2CH1
PTF6
PTJ0
PTJ1
PTJ2
PTJ3
PTE0/TxD1
PTE1/RxD1
PTE2/TPM1CH0
PTE3/TPM1CH1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
PTC5/RxD2
PTC3/TxD2
PTC2/MCLK
PTH6/MISO2
PTH5/MIOSI2
PTH4/SPCK2
PTC1/SDA1
PTC0/SCL1
VDD (NC)
VSS
PTG6/EXTAL
PTG5/XTAL
BKGD/MS
VREFL
VREFH
PTD7/KBI1P7/AD1P15
PTD6/TPM1CLK/AD1P14
PTD5/AD1P13
PTD4/TPM2CLK/AD1P12
PTG4/KBI1P4
Figure 2-1 shows the 80-pin LQFP package pin assignments for the MC9S08AC128 Series device.
Note: Pin names in bold
are lost in lower pin count
packages.
Figure 2-1. MC9S08AC128 Series in 80-Pin LQFP Package
MC9S08AC128 MCU Series Data Sheet, Rev. 1
Freescale Semiconductor
5
Preliminary — Subject to Change
Chapter 2 Pins and Connections
PTC2/MCLK
PTC1/SDA1
PTC0/SCL1
VSS
PTG6/EXTAL
PTG5/XTAL
BKGD/MS
VREFL
VREFH
PTD7/AD1P15/KBI1P7
PTD6//TPM1CLK
PTD5/AD1P13
PTD4/AD1P12/TPM2CLK
63
62
61
60
59
58
57
56
55
54
53
52
51
50
64
PTC4 1
PTG4/KBI1P4
PTC3/TxD2
PTC5/RxD2
Figure 2-2 shows the 64-pin package assignments for the MC9S08AC128 Series devices.
49
48
PTG3/KBI1P3
IRQ/TPMCLK
2
47
PTD3/KBI1P6/AD1P11
RESET
3
46
PTD2KBI1P5/AD1P10
PTF0/TPM1CH2
4
45
VSSAD
PTF1/TPM1CH3
5
44
VDDAD
PTF2/TPM1CH4
6
43
PTD1/AD1P9
PTF3/TPM1CH5
7
42
PTD0/AD1P8
PTF4/TPM2CH0
8
41
PTB7/AD1P7
PTC6
9
40
PTB6/AD1P6
PTF7
10
39
PTB5/AD1P5
PTF5/TPM2CH1
11
38
PTB4/AD1P4
PTF6
12
37
PTB3/AD1P3
PTE0/TxD1
13
36
PTB2/AD1P2
PTE1/RxD1
14
35
PTB1/TPM3CH1/AD1P1
PTE2/TPM1CH0
15
34
PTB0/TPM3CH0/AD1P0
64-Pin QFP
PTE3/TPM1CH1 16
33 PTA7
18
19
20
21
22
23
24
25
26
27
28
29
30
31
PTA5
PTA4
PTA3
PTA2
PTA1
PTA0
PTG2/KBI1P2
PTG1/KBI1P1
PTG0/KBI1P0
VDD
VSS
PTE7/SPSCK1
PTE6/MOSI1
PTE5/MISO1
PTE4/SS1
PTA6
32
17
Note: Pin names in bold
are lost in lower pin count
packages.
Figure 2-2. MC9S08AC128 Series in 64-Pin QFP Package
MC9S08AC128 MCU Series Data Sheet, Rev. 1
6
Freescale Semiconductor
Preliminary — Subject to Change
Chapter 2 Pins and Connections
34
44
43
PTC4 1
VREFH
VREFL
BKGD/MS
PTG5/XTAL
PTG6/EXTAL
VSS
PTC0/SCL1
PTC1/SDA1
PTC2/MCLK
PTC3/TxD2
PTC5/RxD2
Figure 2-3 shows the 44-pin LQFP pin assignments for the MC9S08AC128 Series device.
42
41
40
39
38
37
36
35
33 PTG3/KBI1P3
IRQ/TPMCLK
2
32
PTD3/KBI1P6/AD1P11
RESET
3
31
PTD2/KBI1P5/AD1P10
PTF0/TPM1CH2
4
30
VSSAD
PTF1/TPM1CH3
5
29
VDDAD
28
PTD1/AD1P9
44-Pin LQFP
PTF4/TPM2CH0
6
PTF5/TPM2CH1
7
27
PTD0/AD1P8
PTE0/TxD1
8
26
PTB3/AD1P3
PTE1/RxD1
9
25
PTB2/AD1P2
PTE2/TPM1CH0
10
24
PTB1/TPM3CH1/AD1P1
PTE3/TPM1CH1 11
23 PTB0/TPM3CH0/AD1P0
14
13
15
16
17
18
19
20
21
PTA0
PTG2/KBI1P2
PTG1/KBI1P1
PTG0/KBI1P0
VDD
VSS
PTE7/SPSCK1
PTE6/MOSI1
PTE5/MISO1
PTE4/SS1
PTA1
22
12
Figure 2-3. MC9S08AC128 Series in 44-Pin LQFP Package
Table 2-4. Pin Availability by Package Pin-Count
Pin Number
Lowest <--
Priority
--> Highest
Port Pin
Alt 1
Alt 2
80
64
44
1
1
1
PTC4
2
2
2
IRQ
3
3
3
RESET
4
4
4
PTF0
TPM1CH2
5
5
5
PTF1
TPM1CH3
6
6
—
PTF2
TPM1CH4
7
7
—
PTF3
TPM1CH5
8
8
6
PTF4
TPM2CH0
TPMCLK1
MC9S08AC128 MCU Series Data Sheet, Rev. 1
Freescale Semiconductor
7
Preliminary — Subject to Change
Chapter 2 Pins and Connections
Table 2-4. Pin Availability by Package Pin-Count (continued)
Pin Number
Lowest <--
Priority
--> Highest
Port Pin
Alt 1
Alt 2
80
64
44
9
9
—
PTC6
10
10
—
PTF7
11
11
7
PTF5
12
12
—
PTF6
13
—
—
PTJ0
14
—
—
PTJ1
15
—
—
PTJ2
16
—
—
PTJ3
17
13
8
PTE0
18
14
9
PTE1
RxD1
19
15
10
PTE2
TPM1CH0
20
16
11
PTE3
TPM1CH1
21
17
12
PTE4
SS1
22
18
13
PTE5
MISO1
23
19
14
PTE6
MOSI1
24
20
15
PTE7
SPSCK1
25
21
16
VSS
26
22
17
VDD
27
—
—
PTJ4
28
—
—
PTJ5
29
—
—
PTJ6
TPM2CH1
TxD1
30
—
—
PTJ7
31
23
18
PTG0
KBI1P0
32
24
19
PTG1
KBI1P1
33
25
20
PTG2
KBI1P2
34
26
21
PTA0
35
27
22
PTA1
36
28
—
PTA2
37
29
—
PTA3
38
30
—
PTA4
39
31
—
PTA5
40
32
—
PTA6
41
33
—
PTA7
42
—
—
PTH0
TPM2CH2
43
—
—
PTH1
TPM2CH3
44
—
—
PTH2
TPM2CH4
45
—
—
PTH3
TPM2CH5
46
34
23
PTB0
TPM3CH0 AD1P0
47
35
24
PTB1
TPM3CH1 AD1P1
48
36
25
PTB2
AD1P2
49
37
26
PTB3
AD1P3
MC9S08AC128 MCU Series Data Sheet, Rev. 1
8
Freescale Semiconductor
Preliminary — Subject to Change
Chapter 2 Pins and Connections
Table 2-4. Pin Availability by Package Pin-Count (continued)
Pin Number
1
Lowest <--
Priority
--> Highest
Port Pin
Alt 1
Alt 2
80
64
44
50
38
—
PTB4
AD1P4
51
39
—
PTB5
AD1P5
52
40
—
PTB6
AD1P6
53
41
—
PTB7
AD1P7
54
42
27
PTD0
AD1P8
55
43
28
PTD1
AD1P9
56
44
29
VDDAD
57
45
30
VSSAD
58
46
31
PTD2
KBI1P5
AD1P10
59
47
32
PTD3
KBI1P6
AD1P11
60
48
33
PTG3
KBI1P3
61
49
—
PTG4
KBI1P4
62
50
—
PTD4
TPM2CLK AD1P12
63
51
—
PTD5
AD1P13
64
52
—
PTD6
TPM1CLK AD1P14
65
53
—
PTD7
KBI1P7
66
54
34
VREFH
67
55
35
VREFL
68
56
36
BKGD
MS
69
57
37
PTG5
XTAL
70
58
38
PTG6
EXTAL
71
59
39
VSS
72
—
—
VDD(NC)
73
60
40
PTC0
SCL1
74
61
41
PTC1
SDA1
75
—
—
PTH4
SPSCK2
76
—
—
PTH5
MOSI2
77
—
—
PTH6
MISO2
78
62
42
PTC2
MCLK
79
63
43
PTC3
TxD2
80
64
44
PTC5
RxD2
AD1P15
TPMCLK, TPM1CLK, and TPM2CLK options are
configured via software; out of reset, TPM1CLK,
TPM2CLK, and TPMCLK are available to TPM1,
TPM2, and TPM3 respectively.
MC9S08AC128 MCU Series Data Sheet, Rev. 1
Freescale Semiconductor
9
Preliminary — Subject to Change
Chapter 2 Pins and Connections
MC9S08AC128 MCU Series Data Sheet, Rev. 1
10
Freescale Semiconductor
Preliminary — Subject to Change
Chapter 3
Electrical Characteristics and Timing Specifications
3.1
Introduction
This section contains electrical and timing specifications.
3.2
Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better
understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate:
Table 3-1. Parameter Classifications
P
Those parameters are guaranteed during production testing on each individual device.
C
Those parameters are achieved by the design characterization by measuring a
statistically relevant sample size across process variations.
T
Those parameters are achieved by design characterization on a small sample size from
typical devices under typical conditions unless otherwise noted. All values shown in
the typical column are within this category.
D
Those parameters are derived mainly from simulations.
NOTE
The classification is shown in the column labeled “C” in the parameter tables where
appropriate.
3.3
Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the
limits specified in Table 3-2 may affect device reliability or cause permanent damage to the device. For functional operating
conditions, refer to the remaining tables in this section.
This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that
normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance
circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either
VSS or VDD).
MC9S08AC128 Series Data Sheet, Rev. 1
Freescale Semiconductor
11
Preliminary — Subject to Change
Chapter 3 Electrical Characteristics and Timing Specifications
Table 3-2. Absolute Maximum Ratings
Rating
Symbol
Value
Unit
Supply voltage
VDD
–0.3 to + 5.8
V
Input voltage
VIn
– 0.3 to VDD + 0.3
V
Instantaneous maximum current
Single pin limit (applies to all port pins)1, 2, 3
ID
± 25
mA
Maximum current into VDD
IDD
120
mA
Tstg
–55 to +150
°C
Storage temperature
1
Input must be current limited to the value specified. To determine the value of the required
current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp
voltages, then use the larger of the two resistance values.
2
All functional non-supply pins are internally clamped to VSS and VDD.
3
Power supply must maintain regulation within operating VDD range during instantaneous and
operating maximum current conditions. If positive injection current (VIn > VDD) is greater than
IDD, the injection current may flow out of VDD and could result in external power supply going
out of regulation. Ensure external VDD load will shunt current greater than maximum injection
current. This will be the greatest risk when the MCU is not consuming power. Examples are: if
no system clock is present, or if the clock rate is very low which would reduce overall power
consumption.
MC9S08AC128 Series Data Sheet, Rev. 1
12
Freescale Semiconductor
Preliminary — Subject to Change
Chapter 3 Electrical Characteristics and Timing Specifications
3.4
Thermal Characteristics
This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power
dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and it is user-determined rather than
being controlled by the MCU design. In order to take PI/O into account in power calculations, determine the difference between
actual pin voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except in cases of unusually high pin current
(heavy loads), the difference between pin voltage and VSS or VDD will be very small.
Table 3-3. Thermal Characteristics
Rating
Symbol
Value
Unit
TA
TL to TH
–40 to 125
°C
TJ
150
°C
Operating temperature range (packaged)
Maximum junction temperature
Thermal resistance 1,2,3,4
80-pin LQFP
1s
2s2p
64-pin QFP
1s
2s2p
61
47
θJA
57
43
°C/W
44-pin LQFP
1s
2s2p
73
56
1
Junction temperature is a function of die size, on-chip power dissipation, package thermal
resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation
of other components on the board, and board thermal resistance.
2 Junction to Ambient Natural Convection
3 1s - Single Layer Board, one signal layer
4 2s2p - Four Layer Board, 2 signal and 2 power layers
The average chip-junction temperature (TJ) in °C can be obtained from:
TJ = TA + (PD × θJA)
Eqn. 3-1
where:
TA = Ambient temperature, °C
θJA = Package thermal resistance, junction-to-ambient, °C/W
PD = Pint + PI/O
Pint = IDD × VDD, Watts — chip internal power
PI/O = Power dissipation on input and output pins — user determined
For most applications, PI/O << Pint and can be neglected. An approximate relationship between PD and TJ (if PI/O is neglected)
is:
PD = K ÷ (TJ + 273°C)
Eqn. 3-2
Solving equations 1 and 2 for K gives:
MC9S08AC128 MCU Series Data Sheet, Rev. 1
Freescale Semiconductor
13
Preliminary — Subject to Change
Chapter 3 Electrical Characteristics and Timing Specifications
K = PD × (TA + 273°C) + θJA × (PD)2
Eqn. 3-3
where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring PD (at equilibrium)
for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving equations 1 and 2 iteratively for any
value of TA.
3.5
ESD Protection and Latch-Up Immunity
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits,
normal handling precautions should be used to avoid exposure to static discharge. Qualification tests are performed to ensure
that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage.
All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits and
JEDEC Standard for Non-Automotive Grade Integrated Circuits. During the device qualification ESD stresses were performed
for the Human Body Model (HBM), the Machine Model (MM) and the Charge Device Model (CDM).
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete
DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot
temperature, unless specified otherwise in the device specification.
Table 3-4. ESD and Latch-up Test Conditions
Model
Human Body
Machine
Description
Symbol
Value
Unit
Series Resistance
R1
1500
Ω
Storage Capacitance
C
100
pF
Number of Pulse per pin
–
3
Series Resistance
R1
0
Ω
Storage Capacitance
C
200
pF
Number of Pulse per pin
–
3
Minimum input voltage limit
– 2.5
V
Maximum input voltage limit
7.5
V
Latch-up
Table 3-5. ESD and Latch-Up Protection Characteristics
Num C
3.6
Rating
Symbol
Min
Max
Unit
1
C Human Body Model (HBM)
VHBM
± 2000
–
V
2
C Machine Model (MM)
VMM
± 200
–
V
3
C Charge Device Model (CDM)
VCDM
± 500
–
V
4
C Latch-up Current at TA = 125°C
ILAT
± 100
–
mA
DC Characteristics
This section includes information about power supply requirements, I/O pin characteristics, and power supply current in various
operating modes.
MC9S08AC128 Series Data Sheet, Rev. 1
14
Freescale Semiconductor
Preliminary — Subject to Change
Chapter 3 Electrical Characteristics and Timing Specifications
Table 3-6. DC Characteristics
Num C
Parameter
1
— Operating Voltage
2
P Output high voltage — Low Drive (PTxDSn = 0)
5 V, ILoad = –2 mA
3 V, ILoad = –0.6 mA
5 V, ILoad = –0.4 mA
3 V, ILoad = –0.24 mA
P Output high voltage — High Drive (PTxDSn = 1)
5 V, ILoad = –10 mA
3 V, ILoad = –3 mA
5 V, ILoad = –2 mA
3 V, ILoad = –0.4 mA
3
5
6
Min
Typ1
Max
Unit
VDD
2.7
—
5.5
V
VDD – 1.5
VDD – 1.5
VDD – 0.8
VDD – 0.8
—
—
—
—
—
—
—
—
V
VOH
VDD – 1.5
VDD – 1.5
VDD – 0.8
VDD – 0.8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1.5
1.5
0.8
0.8
—
—
—
—
—
—
—
—
1.5
1.5
0.8
0.8
IOHT
—
—
—
—
100
60
mA
5V
3V
IOLT
—
—
—
—
100
60
mA
2.7v ≤ VDD 4.5v
VIH
0.70xVDD
—
—
4.5v ≤ VDD ≤ 5.5v
VIH
0.65xVDD
—
—
VIL
—
—
0.35 x VDD
Vhys
0.06 x VDD
P Output low voltage — Low Drive (PTxDSn = 0)
5 V, ILoad = 2 mA
3 V, ILoad = 0.6 mA
5 V, ILoad = 0.4 mA
3 V, ILoad = 0.24 mA
P Output low voltage — High Drive (PTxDSn = 1)
5 V, ILoad = 10 mA
3 V, ILoad = 3 mA
5 V, ILoad = 2 mA
3 V, ILoad = 0.4 mA
4
Symbol
P Output high current — Max total IOH for all ports
5V
3V
V
VOL
P Output low current — Max total IOL for all ports
P Input high
voltage; all
digital inputs
7
P Input low voltage; all digital inputs
8
P Input hysteresis; all digital inputs
2
V
mV
9
P Input leakage current; input only pins
|IIn|
—
0.1
1
μA
10
P High Impedance (off-state) leakage current2
|IOZ|
—
0.1
1
μA
11
P Internal pullup resistors3
RPU
20
45
65
kΩ
RPD
20
45
65
kΩ
12
4
P Internal pulldown resistors
13
C Input Capacitance; all non-supply pins
CIn
—
—
8
pF
14
D RAM retention voltage
VRAM
—
0.6
1.0
V
15
P POR rearm voltage
VPOR
0.9
1.4
2.0
V
16
D POR rearm time
tPOR
10
—
—
μs
17
P Low-voltage detection threshold — high range
VDD falling
VDD rising
VLVDH
4.2
4.3
4.3
4.4
4.4
4.5
V
Low-voltage detection threshold — low range
VDD falling
VDD rising
VLVDL
2.48
2.54
2.56
2.62
2.64
2.7
V
18
P
MC9S08AC128 MCU Series Data Sheet, Rev. 1
Freescale Semiconductor
15
Preliminary — Subject to Change
Chapter 3 Electrical Characteristics and Timing Specifications
Table 3-6. DC Characteristics (continued)
Num C
19
P
20
P
21
Parameter
Symbol
Low-voltage warning threshold — high range
VDD falling VLVWH
VDD rising
Low-voltage warning threshold — low range
VLVWL
VDD falling
VDD rising
Min
Typ1
Max
Unit
4.2
4.3
4.3
4.4
4.4
4.5
V
2.48
2.54
2.56
2.62
2.64
2.7
V
—
—
100
60
—
—
mV
Low-voltage inhibit reset/recover hysteresis
P
5V
3V
Vhys
1
Typical values are based on characterization data at 25°C unless otherwise stated.
Measured with VIn = VDD or VSS.
3 Measured with V = V .
In
SS
4 Measured with V = V .
In
DD
2
VDD–VOH (V)
Average of IOH
–6.0E-3
–5.0E-3
–40°C
25°C
125°C
IOH (A)
–4.0E-3
–3.0E-3
–2.0E-3
–1.0E-3
000E+0
0
0.3
0.5
0.8
VSupply–VOH
0.9
1.2
1.5
Figure 3-1. Typical IOH (Low Drive) vs VDD–VOH at VDD = 3 V
MC9S08AC128 Series Data Sheet, Rev. 1
16
Freescale Semiconductor
Preliminary — Subject to Change
Chapter 3 Electrical Characteristics and Timing Specifications
–20.0E-3
VDD–VOH (V)
Average of IOH
–18.0E-3
–16.0E-3
–14.0E-3
–12.0E-3
–10.0E-3
–8.0E-3
–6.0E-3
–4.0E-3
–2.0E-3
000.0E-3
IOH (A)
–40°C
25°C
125°C
0
0.3
0.5
0.8
VSupply–VOH
0.9
1.2
1.5
Figure 3-2. Typical IOH (High Drive) vs VDD–VOH at VDD = 3 V
Average of IOH
–7.0E-3
–40°C
25°C
125°C
–6.0E-3
–5.0E-3
IOH (A)
–4.0E-3
–3.0E-3
–2.0E-3
–1.0E-3
000E+0
0.00
0.30
0.50
0.80
1.00
1.30
2.00
VDD–VOH (V)
VSupply–VOH
Figure 3-3. Typical IOH (Low Drive) vs VDD–VOH at VDD = 5 V
VDD–VOH (V)
Average of IOH
–30.0E-3
–25.0E-3
–40°C
25°C
125°C
IOH (A)
–20.0E-3
–15.0E-3
–10.0E-3
–5.0E-3
000.0E+3
0.00
0.30
0.50
0.80
1.00
1.30
2.00
VSupply–VOH
Figure 3-4. Typical IOH (High Drive) vs VDD–VOH at VDD = 5 V
MC9S08AC128 MCU Series Data Sheet, Rev. 1
Freescale Semiconductor
17
Preliminary — Subject to Change
Chapter 3 Electrical Characteristics and Timing Specifications
3.7
Supply Current Characteristics
Table 3-7. Supply Current Characteristics
Num
C
Parameter
Symbol
1
C
Run supply current measured at
(CPU clock = 2 MHz, fBus = 1 MHz)
2
C
Run supply current measured at
(CPU clock = 16 MHz, fBus = 8 MHz)
VDD
(V)
Typ1
Max
5
0.750
0.9503
3
0.570
0.770
5
4.9
5.105
3
3.5
3.70
1.0
2
RIDD
4
RIDD
Stop2 mode supply current
3
5
C
3
S2IDD
Stop3 mode supply current
4
5
6
7
1
2
3
4
5
6
7
5
C
C
C
C
S3IDD
RTI adder to stop2 or stop36
3
Adder to stop3 for oscillator enabled7
(OSCSTEN =1)
mA
–40 to 125°C
mA
–40 to 125°C
25
160
μA
–40 to 85°C
–40 to 125°C
0.8
23
150
μA
–40 to 85°C
–40 to 125°C
1.2
27
1803
μA
–40 to 85°C
–40 to 125°C
1.0
25
170
μA
–40 to 85°C
–40 to 125°C
300
500
500
nA
–40 to 85°C
–40 to 125°C
3
300
500
500
nA
–40 to 85°C
–40 to 125°C
5
110
180
180
μA
–40 to 85°C
–40 to 125°C
3
90
160
160
μA
–40 to 85°C
–40 to 125°C
5,3
5
8
8
μA
μA
–40 to 85°C
–40 to 125°C
S3IDDLVD
S3IDDOSC
Temp
(°C)
5
S23IDDRTI
LVD adder to stop3 (LVDE = LVDSE = 1)
Unit
Typical values are based on characterization data at 25°C unless otherwise stated. See Figure 3-5 through Figure 3-7 for
typical curves across voltage/temperature.
All modules except ADC active, ICG configured for FBE, and does not include any dc loads on port pins
Every unit tested to this parameter. All other values in the Max column are guaranteed by characterization.
All modules except ADC active, ICG configured for FBE, and does not include any dc loads on port pins
Every unit tested to this parameter. All other values in the Max column are guaranteed by characterization.
Most customers are expected to find that auto-wakeup from stop2 or stop3 can be used instead of the higher current wait
mode. Wait mode typical is 560 μA at 3 V with fBus = 1 MHz.
Values given under the following conditions: low range operation (RANGE = 0) with a 32.768kHz crystal, low power mode
(HGO = 0), clock monitor disabled (LOCD = 1).
MC9S08AC128 Series Data Sheet, Rev. 1
18
Freescale Semiconductor
Preliminary — Subject to Change
Chapter 3 Electrical Characteristics and Timing Specifications
18
20 MHz, ADC off, FEE, 25°C
16
20 MHz, ADC off, FBE, 25°C
14
12
10
IDD
8
8 MHz, ADC off, FEE, 25°C
8 MHz, ADC off, FBE, 25°C
6
4
1 MHz, ADC off, FEE, 25°C
1 MHz, ADC off, FBE, 25°C
2
0
2.2
2.6
3.0
3.4
3.8
4.2
4.6
5.0
5.4
VDD
Note: External clock is square wave supplied by function generator. For FEE mode, external reference frequency is 4 MHz
Figure 3-5. Typical Run IDD for FBE and FEE Modes, IDD vs. VDD
MC9S08AC128 MCU Series Data Sheet, Rev. 1
Freescale Semiconductor
19
Preliminary — Subject to Change
Chapter 3 Electrical Characteristics and Timing Specifications
–40°C
25°C
55°C
85°C
Stop2 IDD (A)
Average of Measurement IDD
–8.0E-3
–7.0E-3
–6.0E-3
IDD (A)
–5.0E-3
–4.0E-3
–3.0E-3
–2.0E-3
–1.0E-3
000E+0
1.8
2
2.5
3
3.5
4
4.5
5
VDD (V)
Figure 3-6. Typical Stop 2 IDD
–40°C
25°C
55°C
85°C
Stop3 IDD (A)
Average of Measurement IDD
–8.0E-3
–7.0E-3
–6.0E-3
IDD (A)
–5.0E-3
–4.0E-3
–3.0E-3
–2.0E-3
–1.0E-3
000E+0
1.8
2
2.5
3
3.5
4
4.5
5
VDD (V)
Figure 3-7. Typical Stop3 IDD
MC9S08AC128 Series Data Sheet, Rev. 1
20
Freescale Semiconductor
Preliminary — Subject to Change
Chapter 3 Electrical Characteristics and Timing Specifications
3.8
ADC Characteristics
Table 3-8. 5 Volt 10-bit ADC Operating Conditions
Symb
Min
Typ1
Max
Unit
Absolute
VDDAD
2.7
—
5.5
V
Delta to VDD (VDD–VDDAD)2
ΔVDDAD
–100
0
+100
mV
Delta to VSS (VSS–VSSAD)2
ΔVSSAD
–100
0
+100
mV
Ref voltage high
VREFH
2.7
VDDAD
VDDAD
V
Ref voltage low
VREFL
VSSAD
VSSAD
VSSAD
V
IDDAD
—
0.011
1
μA
Input voltage
VADIN
VREFL
—
VREFH
V
Input capacitance
CADIN
—
4.5
5.5
pF
Input resistance
RADIN
—
3
5
kΩ
RAS
—
—
—
—
5
10
kΩ
—
—
10
0.4
—
8.0
0.4
—
4.0
3.266
—
3.638
—
mV/°
C
1.396
—
V
Characteristic
Supply voltage
Ground voltage
Supply current
Analog source resistance
External to MCU
Conditions
Stop, reset, module off
10-bit mode
fADCK > 4MHz
fADCK < 4MHz
8-bit mode (all valid fADCK)
ADC conversion clock frequency
High speed (ADLPC = 0)
Low power (ADLPC = 1)
Temp Sensor
Slope
Temp Sensor
Voltage
fADCK
–40 °C to 25 °C
m
25 °C to 125 °C
25 °C
VTEMP25
MHz
—
—
1
Typical values assume VDDAD = 5.0 V, Temp = 25°C, fADCK = 1.0MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
2 dc potential difference.
MC9S08AC128 MCU Series Data Sheet, Rev. 1
Freescale Semiconductor
21
Preliminary — Subject to Change
Chapter 3 Electrical Characteristics and Timing Specifications
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
ZADIN
Pad
leakage
due to
input
protection
ZAS
RAS
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
RADIN
ADC SAR
ENGINE
+
VADIN
VAS
+
–
CAS
–
RADIN
INPUT PIN
INPUT PIN
RADIN
RADIN
INPUT PIN
CADIN
Figure 3-8. ADC Input Impedance Equivalency Diagram
MC9S08AC128 Series Data Sheet, Rev. 1
22
Freescale Semiconductor
Preliminary — Subject to Change
Chapter 3 Electrical Characteristics and Timing Specifications
Table 3-9. 5 Volt 10-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD)
C
Symb
Min
Typ1
Max
Unit
Supply current
ADLPC = 1
ADLSMP = 1
ADCO = 1
T
IDDAD
—
133
—
μA
Supply current
ADLPC = 1
ADLSMP = 0
ADCO = 1
T
IDDAD
—
218
—
μA
Supply current
ADLPC = 0
ADLSMP = 1
ADCO = 1
T
IDDAD
—
327
—
μA
Supply current
ADLPC = 0
ADLSMP = 0
ADCO = 1
T
IDDAD
—
582
—
μA
—
—
1
mA
2
3.3
5
MHz
1.25
2
3.3
—
20
—
—
40
—
—
3.5
—
—
23.5
—
—
±1
±2.5
—
±0.5
±1.0
—
±0.5
±1.0
—
±0.3
±0.5
Characteristic
ADC asynchronous clock source
tADACK = 1/fADACK
Conditions
VDDAD < 5.5 V
P
High speed (ADLPC = 0)
P
fADACK
Low power (ADLPC = 1)
Conversion time
(Including sample time)
Short sample (ADLSMP = 0)
Sample time
Short sample (ADLSMP = 0)
P
tADC
Long sample (ADLSMP = 1)
P
tADS
Long sample (ADLSMP = 1)
Total unadjusted error
Includes quantization
Differential non-linearity
10-bit mode
P
ETUE
8-bit mode
10-bit mode
P
DNL
8-bit mode
ADCK
cycles
ADCK
cycles
LSB2
LSB2
Monotonicity and no-missing-codes guaranteed
Integral non-linearity
10-bit mode
C
INL
8-bit mode
Zero-scale error
VADIN = VSSA
10-bit mode
Full-scale error
VADIN = VDDA
10-bit mode
Quantization error
10-bit mode
P
EZS
8-bit mode
P
EFS
8-bit mode
D
EQ
8-bit mode
—
±0.5
±1.0
—
±0.3
±0.5
—
±0.5
±1.5
—
±0.5
±0.5
—
±0.5
±1.5
—
±0.5
±0.5
—
—
±0.5
—
—
±0.5
LSB2
LSB2
LSB2
LSB2
MC9S08AC128 MCU Series Data Sheet, Rev. 1
Freescale Semiconductor
23
Preliminary — Subject to Change
Chapter 3 Electrical Characteristics and Timing Specifications
Table 3-9. 5 Volt 10-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD)
Characteristic
Conditions
Input leakage error
Pad leakage3 * RAS
10-bit mode
C
Symb
Min
Typ1
Max
Unit
D
EIL
—
±0.2
±2.5
LSB2
—
±0.1
±1
8-bit mode
1
Typical values assume VDDAD = 5.0V, Temp = 25C, fADCK=1.0 MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
2
1 LSB = (VREFH – VREFL)/2N
3 Based on input pad leakage current. Refer to pad electricals.
3.9
Internal Clock Generation Module Characteristics
ICG
EXTAL
XTAL
RS
RF
C1
Crystal or Resonator
C2
Table 3-10. ICG DC Electrical Specifications (Temperature Range = –40 to 125°C Ambient)
Characteristic
Load capacitors
Feedback resistor
Low range (32k to 100 kHz)
High range (1M – 16 MHz)
Series resistor
Low range
Low Gain (HGO = 0)
High Gain (HGO = 1)
High range
Low Gain (HGO = 0)
High Gain (HGO = 1)
≥ 8 MHz
4 MHz
1 MHz
1
2
Symbol
Min
Typ1
Max
C1
C2
See Note 2
RF
10
1
RS
Unit
MΩ
MΩ
—
—
0
100
—
—
—
0
—
—
—
—
0
10
20
—
—
—
kΩ
Typical values are based on characterization data at VDD = 5.0V, 25°C or is typical recommended value.
See crystal or resonator manufacturer’s recommendation.
MC9S08AC128 Series Data Sheet, Rev. 1
24
Freescale Semiconductor
Preliminary — Subject to Change
Chapter 3 Electrical Characteristics and Timing Specifications
3.9.1
ICG Frequency Specifications
Table 3-11. ICG Frequency Specifications
(VDDA = VDDA (min) to VDDA (max), Temperature Range = –40 to 125°C Ambient)
Num
1
2
C
Characteristic
Oscillator crystal or resonator (REFS = 1)
(Fundamental mode crystal or ceramic resonator)
Low range
High range
High Gain, FBE (HGO = 1,CLKS = 10)
High Gain, FEE (HGO = 1,CLKS = 11)
Low Power, FBE (HGO = 0, CLKS = 10)
Low Power, FEE (HGO = 0, CLKS = 11)
Input clock frequency (CLKS = 11, REFS = 0)
Low range
High range
1
Min
Typ1
Max
Unit
flo
32
—
100
kHz
fhi_byp
fhi_eng
flp_byp
flp_eng
1
2
1
2
—
—
16
10
8
8
MHz
MHz
MHz
MHz
flo
fhi_eng
32
2
—
—
100
10
kHz
MHz
fExtal
0
—
40
MHz
fICGIRCLK
182.25
243
303.75
kHz
tdc
40
—
60
%
fICGOUT
fExtal (min)
flo (min)
—
—
3
—
3
Input clock frequency (CLKS = 10, REFS = 0)
4
Internal reference frequency (untrimmed)
5
Duty cycle of input clock (REFS = 0)
6
Output clock ICGOUT frequency
CLKS = 10, REFS = 0
All other cases
7
Minimum DCO clock (ICGDCLK) frequency
fICGDCLKmin
8
Maximum DCO clock (ICGDCLK) frequency
fICGDCLKmax
2
9
Self-clock mode (ICGOUT) frequency
10
Self-clock mode reset (ICGOUT) frequency
11
Loss of reference frequency
Low range
High range
12
Loss of DCO frequency 4
13
2
Symbol
Crystal start-up time
Low range
High range
—
fExtal (max)
fICGDCLKmax(
max)
MHz
MHz
40
MHz
fICGDCLKmax
MHz
10.5
MHz
fSelf
fICGDCLKmin
fSelf_reset
5.5
fLOR
5
50
25
500
kHz
fLOD
0.5
1.5
MHz
—
—
ms
8
3
5, 6
t
CSTL
—
—
t
CSTH
430
4
14
FLL lock time , 7
Low range
High range
tLockl
tLockh
—
—
2
2
ms
15
FLL frequency unlock range
nUnlock
–4*N
4*N
counts
16
FLL frequency lock range
nLock
–2*N
2*N
counts
CJitter
—
0.2
% fICG
ACCint
—
—
±2
±2
%
, 8 measured
17
at fICGOUT Max
ICGOUT period jitter,
Long term jitter (averaged over 2 ms interval)
18
Internal oscillator deviation from trimmed
frequency9
VDD = 2.7 – 5.5 V, (constant temperature)
VDD = 5.0 V ±10%, –40° C to 125°C
± 0.5
±0.5
Typical values are based on characterization data at VDD = 5.0V, 25°C unless otherwise stated.
Self-clocked mode frequency is the frequency that the DCO generates when the FLL is open-loop.
MC9S08AC128 MCU Series Data Sheet, Rev. 1
Freescale Semiconductor
25
Preliminary — Subject to Change
Chapter 3 Electrical Characteristics and Timing Specifications
3
4
5
6
7
8
9
Loss of reference frequency is the reference frequency detected internally, which transitions the ICG into self-clocked mode if it
is not in the desired range.
Loss of DCO frequency is the DCO frequency detected internally, which transitions the ICG into FLL bypassed external mode
(if an external reference exists) if it is not in the desired range.
This parameter is characterized before qualification rather than 100% tested.
Proper PC board layout procedures must be followed to achieve specifications.
This specification applies to the period of time required for the FLL to lock after entering FLL engaged internal or external modes.
If a crystal/resonator is being used as the reference, this specification assumes it is already running.
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fICGOUT.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry via VDDA and VSSA and variation in crystal oscillator frequency increase the CJitter percentage for
a given interval.
See Figure 3-9
Average of Percentage Error
Variable
3V
5V
Figure 3-9. Internal Oscillator Deviation from Trimmed Frequency
MC9S08AC128 Series Data Sheet, Rev. 1
26
Freescale Semiconductor
Preliminary — Subject to Change
Chapter 3 Electrical Characteristics and Timing Specifications
3.10
AC Characteristics
This section describes ac timing characteristics for each peripheral system. For detailed information about how clocks for the
bus are generated, see Chapter 10, “Internal Clock Generator (S08ICGV4).”
3.10.1
Control Timing
Table 3-12. Control Timing
Num
C
Parameter
Symbol
Min
Typ1
Max
Unit
—
20
MHz
1
Bus frequency (tcyc = 1/fBus)
fBus
dc
2
Real-time interrupt internal oscillator period
tRTI
700
1300
μs
3
External reset pulse width2
(tcyc = 1/fSelf_reset)
textrst
1.5 x
tSelf_reset
—
ns
4
Reset low drive3
trstdrv
34 x tcyc
—
ns
5
Active background debug mode latch setup time
tMSSU
25
—
ns
6
Active background debug mode latch hold time
tMSH
25
—
ns
7
IRQ pulse width
Asynchronous path2
Synchronous path4
tILIH, tIHIL
100
1.5 x tcyc
—
—
ns
KBIPx pulse width
Asynchronous path2
Synchronous path3
tILIH, tIHIL
100
1.5 x tcyc
—
—
ns
Port rise and fall time (load = 50 pF)5
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
tRise, tFall
—
—
3
30
8
9
ns
1
Typical values are based on characterization data at VDD = 5.0V, 25°C unless otherwise stated.
This is the shortest pulse that is guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed to
override reset requests from internal sources.
3 When any reset is initiated, internal circuitry drives the reset pin low for about 34 bus cycles and then samples the level on
the reset pin about 38 bus cycles later to distinguish external reset requests from internal requests.
4 This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.
5
Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range –40°C to 125°C.
2
textrst
RESET PIN
Figure 3-10. Reset Timing
MC9S08AC128 MCU Series Data Sheet, Rev. 1
Freescale Semiconductor
27
Preliminary — Subject to Change
Chapter 3 Electrical Characteristics and Timing Specifications
BKGD/MS
RESET
tMSH
tMSSU
Figure 3-11. Active Background Debug Mode Latch Timing
tIHIL
IRQ/KBIP7-KBIP4
IRQ/KBIPx
tILIH
Figure 3-12. IRQ/KBIPx Timing
3.10.2
Timer/PWM (TPM) Module Timing
Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the
optional external source to the timer counter. These synchronizers operate from the current bus rate clock.
Table 3-13. TPM Input Timing
Function
Symbol
Min
Max
Unit
External clock frequency
fTPMext
dc
fBus/4
MHz
External clock period
tTPMext
4
—
tcyc
External clock high time
tclkh
1.5
—
tcyc
External clock low time
tclkl
1.5
—
tcyc
tICPW
1.5
—
tcyc
Input capture pulse width
MC9S08AC128 Series Data Sheet, Rev. 1
28
Freescale Semiconductor
Preliminary — Subject to Change
Chapter 3 Electrical Characteristics and Timing Specifications
tTPMext
tclkh
TPMxCLK
tclkl
Figure 3-13. Timer External Clock
tICPW
TPMxCHn
TPMxCHn
tICPW
Figure 3-14. Timer Input Capture Pulse
MC9S08AC128 MCU Series Data Sheet, Rev. 1
Freescale Semiconductor
29
Preliminary — Subject to Change
Chapter 3 Electrical Characteristics and Timing Specifications
3.11
SPI Characteristics
Table 3-14 and Figure 3-15 through Figure 3-18 describe the timing requirements for the SPI system.
Table 3-14. SPI Electrical Characteristic
Num1
C
Characteristic2
Symbol
Min
Max
Unit
Master
Slave
fop
fop
fBus/2048
dc
fBus/2
fBus/4
Hz
Master
Slave
tSCK
tSCK
2
4
2048
—
tcyc
tcyc
Master
Slave
tLead
tLead
—
1/2
1/2
—
tSCK
tSCK
Master
Slave
tLag
tLag
—
1/2
1/2
—
tSCK
tSCK
Clock (SPSCK) high time
Master and Slave
tSCKH
1/2 tSCK – 25
—
ns
Clock (SPSCK) low time Master
and Slave
tSCKL
1/2 tSCK – 25
—
ns
Master
Slave
tSI(M)
tSI(S)
30
30
—
—
ns
ns
Master
Slave
tHI(M)
tHI(S)
30
30
—
—
ns
ns
Operating frequency3
1
2
3
4
5
6
7
Cycle time
Enable lead time
Enable lag time
Data setup time (inputs)
Data hold time (inputs)
8
Access time, slave4
tA
0
40
ns
9
Disable time, slave5
tdis
—
40
ns
10
Data setup time (outputs)
Master
Slave
tSO
tSO
25
25
—
—
ns
ns
tHO
tHO
–10
–10
—
—
ns
ns
11
Data hold time (outputs)
Master
Slave
1
Refer to Figure 3-15 through Figure 3-18.
All timing is shown with respect to 20% VDD and 70% VDD, unless noted; 100 pF load on all SPI
pins. All timing assumes slew rate control disabled and high drive strength enabled for SPI output
pins.
3 Maximum baud rate must be limited to 5 MHz due to pad input characteristics.
4
Time to data active from high-impedance state.
5 Hold time to high-impedance state.
2
MC9S08AC128 Series Data Sheet, Rev. 1
30
Freescale Semiconductor
Preliminary — Subject to Change
Chapter 3 Electrical Characteristics and Timing Specifications
SS1
(OUTPUT)
1
2
SCK
(CPOL = 0)
(OUTPUT)
3
5
4
SCK
(CPOL = 1)
(OUTPUT)
5
4
6
MISO
(INPUT)
7
MSB IN2
BIT 6 . . . 1
10
MOSI
(OUTPUT)
LSB IN
10
MSB OUT2
11
BIT 6 . . . 1
LSB OUT
NOTES:
1. SS output mode (MODFEN = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 3-15. SPI Master Timing (CPHA = 0)
SS(1)
(OUTPUT)
1
2
SCK
(CPOL = 0)
(OUTPUT)
3
5
4
SCK
(CPOL = 1)
(OUTPUT)
5
4
6
MISO
(INPUT)
7
MSB IN(2)
10
MOSI
(OUTPUT)
BIT 6 . . . 1
LSB IN
11
MSB OUT(2)
BIT 6 . . . 1
LSB OUT
NOTES:
1. SS output mode (MODFEN = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 3-16. SPI Master Timing (CPHA = 1)
MC9S08AC128 MCU Series Data Sheet, Rev. 1
Freescale Semiconductor
31
Preliminary — Subject to Change
Chapter 3 Electrical Characteristics and Timing Specifications
SS
(INPUT)
3
1
SCK
(CPOL = 0)
(INPUT)
5
4
2
SCK
(CPOL = 1)
(INPUT)
5
4
8
MISO
(OUTPUT)
11
10
BIT 6 . . . 1
MSB OUT
SLAVE
SEE
NOTE
SLAVE LSB OUT
7
6
MOSI
(INPUT)
9
BIT 6 . . . 1
MSB IN
LSB IN
NOTE:
1. Not defined but normally MSB of character just received
Figure 3-17. SPI Slave Timing (CPHA = 0)
SS
(INPUT)
1
3
2
SCK
(CPOL = 0)
(INPUT)
5
4
SCK
(CPOL = 1)
(INPUT)
5
4
10
MISO
(OUTPUT)
SEE
NOTE
8
MOSI
(INPUT)
SLAVE
11
MSB OUT
6
BIT 6 . . . 1
9
SLAVE LSB OUT
7
MSB IN
BIT 6 . . . 1
LSB IN
NOTE:
1. Not defined but normally LSB of character just received
Figure 3-18. SPI Slave Timing (CPHA = 1)
MC9S08AC128 Series Data Sheet, Rev. 1
32
Freescale Semiconductor
Preliminary — Subject to Change
Chapter 3 Electrical Characteristics and Timing Specifications
3.12
FLASH Specifications
This section provides details about program/erase times and program-erase endurance for the Flash memory.
Program and erase operations do not require any special power sources other than the normal VDD supply. For more detailed
information about program/erase operations, see Chapter 4, “Memory.”
Table 3-15. Flash Characteristics
Num
C
1
P
2
Characteristic
Symbol
Min
Supply voltage for program/erase
Vprog/erase
P
Supply voltage for read operation
3
P
4
Typ1
Max
Unit
2.7
5.5
V
VRead
2.7
5.5
V
Internal FCLK frequency2
fFCLK
150
200
kHz
P
Internal FCLK period (1/FCLK)
tFcyc
5
6.67
μs
5
P
Byte program time (random location)(2)
tprog
9
tFcyc
6
C
Byte program time (burst mode)(2)
tBurst
4
tFcyc
7
P
Page erase time3
tPage
4000
tFcyc
8
P
Mass erase time(2)
tMass
20,000
tFcyc
9
C
Program/erase endurance4
TL to TH = –40°C to + 125°C
T = 25°C
10
C
Data retention5
tD_ret
10,000
—
—
100,000
—
—
cycles
15
100
—
years
1
Typical values are based on characterization data at VDD = 5.0 V, 25°C unless otherwise stated.
The frequency of this clock is controlled by a software setting.
3
These values are hardware state machine controlled. User code does not need to count cycles. This information
supplied for calculating approximate time to program and erase.
4 Typical endurance for Flash was evaluated for this product family on the 9S12Dx64. For additional information on
how Freescale Semiconductor defines typical endurance, please refer to Engineering Bulletin EB619/D, Typical
Endurance for Nonvolatile Memory.
5
Typical data retention values are based on intrinsic capability of the technology measured at high temperature and
de-rated to 25°C using the Arrhenius equation. For additional information on how Freescale Semiconductor defines
typical data retention, please refer to Engineering Bulletin EB618/D, Typical Data Retention for Nonvolatile Memory.
2
MC9S08AC128 MCU Series Data Sheet, Rev. 1
Freescale Semiconductor
33
Preliminary — Subject to Change
Chapter 3 Electrical Characteristics and Timing Specifications
3.13
EMC Performance
Electromagnetic compatibility (EMC) performance is highly dependant on the environment in which the MCU resides. Board
design and layout, circuit topology choices, location and characteristics of external components as well as MCU software
operation all play a significant role in EMC performance. The system designer should consult Freescale applications notes such
as AN2321, AN1050, AN1263, AN2764, and AN1259 for advice and guidance specifically targeted at optimizing EMC
performance.
3.13.1
Radiated Emissions
Microcontroller radiated RF emissions are measured from 150 kHz to 1 GHz using the TEM/GTEM Cell method in accordance
with the IEC 61967-2 and SAE J1752/3 standards. The measurement is performed with the microcontroller installed on a
custom EMC evaluation board while running specialized EMC test software. The radiated emissions from the microcontroller
are measured in a TEM cell in two package orientations (North and East). For more detailed information concerning the
evaluation results, conditions and setup, please refer to the EMC Evaluation Report for this device.
The maximum radiated RF emissions of the tested configuration in all orientations are less than or equal to the reported
emissions levels.
Table 3-16. Radiated Emissions
Parameter
Symbol
Conditions
Frequency
fOSC/fBUS
VRE_TEM
VDD = 5.0 V
TA = +25oC
package type
80 LQFP
0.15 – 50 MHz
32kHz crystal
20MHz Bus
Radiated emissions,
electric field
1
50 – 150 MHz
Level1
(Max)
Unit
30
dBμV
32
150 – 500 MHz
19
500 – 1000 MHz
7
IEC Level
1
—
SAE Level
4
—
Data based on qualification test results.
3.13.2
Conducted Transient Susceptibility
Microcontroller transient conducted susceptibility is measured in accordance with an internal Freescale test method. The
measurement is performed with the microcontroller installed on a custom EMC evaluation board and running specialized EMC
test software designed in compliance with the test method. The conducted susceptibility is determined by injecting the transient
susceptibility signal on each pin of the microcontroller. The transient waveform and injection methodology is based on IEC
61000-4-4 (EFT/B). The transient voltage required to cause performance degradation on any pin in the tested configuration is
greater than or equal to the reported levels unless otherwise indicated by footnotes below the table.
MC9S08AC128 Series Data Sheet, Rev. 1
34
Freescale Semiconductor
Preliminary — Subject to Change
Chapter 3 Electrical Characteristics and Timing Specifications
Table 3-17.
Parameter
Symbol
Conducted susceptibility, electrical
fast transient/burst (EFT/B)
1
VCS_EFT
Conditions
VDD = 5.5V
TA = +25oC
package type
80 LQFP
fOSC/fBUS
4MHz
crystal
20MHz Bus
Result
Amplitude1
(Min)
A
TBD
B
TBD
C
TBD
D
TBD
Unit
kV
Data based on qualification test results. Not tested in production.
The susceptibility performance classification is described in Table 3-18.
Table 3-18. Susceptibility Performance Classification
Result
Performance Criteria
A
No failure
The MCU performs as designed during and after exposure.
B
Self-recovering
failure
C
Soft failure
The MCU does not perform as designed during exposure. The MCU does not return to
normal operation until exposure is removed and the RESET pin is asserted.
D
Hard failure
The MCU does not perform as designed during exposure. The MCU does not return to
normal operation until exposure is removed and the power to the MCU is cycled.
E
Damage
The MCU does not perform as designed during and after exposure. The MCU cannot
be returned to proper operation due to physical damage or other permanent
performance degradation.
The MCU does not perform as designed during exposure. The MCU returns
automatically to normal operation after exposure is removed.
MC9S08AC128 MCU Series Data Sheet, Rev. 1
Freescale Semiconductor
35
Preliminary — Subject to Change
Chapter 3 Electrical Characteristics and Timing Specifications
MC9S08AC128 Series Data Sheet, Rev. 1
36
Freescale Semiconductor
Preliminary — Subject to Change
Chapter 4
Ordering Information and Mechanical Drawings
4.1
Ordering Information
This section contains ordering numbers for MC9S08AC128 Series devices. See below for an example of the device numbering
system.
Table 4-1. Device Numbering System
1
2
4.2
Available Packages2
Memory
Device Number1
FLASH
RAM
Type
MC9S08AC128
128K
8K
80 LQFP, 64 QFP, 44-LQFP
MC9S08AC96
96K
6K
80 LQFP, 64 QFP, 44-LQFP
See Table 1-1 for a complete description of modules included on each device.
See Table 4-2 for package information.
Orderable Part Numbering System
MC 9 S08 AC 128 C XX E
Pb free indicator
Package designator (See Table 4-2)
Status
(MC = Fully Qualified)
Memory
(9 = FLASH-based)
Core
Family
4.3
Temperature range
(C = –40°C to 85°C)
(M = –40°C to 125°C)
Approximate memory size (in KB)
Mechanical Drawings
Table 4-2 provides the available package types and their document numbers. The latest package outline/mechanical drawings
are available on the MC9S08AC128 Series Product Summary pages at http://www.freescale.com.
To view the latest drawing, either:
• Click on the appropriate link in Table 4-2, or
• Open a browser to the Freescale® website (http://www.freescale.com), and enter the appropriate document number (from
Table 4-2) in the “Enter Keyword” search box at the top of the page.
Table 4-2. Package Information
Pin Count
Type
Designator
Document No.
80
64
LQFP
LK
98ASS23237W
QFP
FU
98ASB42844B
44
LQFP
FG
98ASS23225W
MC9S08AC128 Series Data Sheet, Rev. 1
Freescale Semiconductor
37
Preliminary — Subject to Change
MC9S08AC128 MCU Series Data Sheet, Rev. 1
38
Freescale Semiconductor
Preliminary — Subject to Change
Chapter 5
Revision History
To provide the most up-to-date information, the version of our documents on the World Wide Web will be
the most current. Your printed copy may be an earlier revision. To verify you have the latest information
available, refer to:
http://freescale.com/
The following revision history table summarizes changes contained in this document.
Revision
Number
1
Revision
Date
Description of Changes
9/2008
Initial release of a separate data sheet and reference manual. Removed PTH7,
clarified SPI as one full and one master-only, added missing RoHS logo, updated
back cover addresses, and incorporated general release edits and updates.
Added some finalized electrical characteristics.
MC9S08AC128 MCU Series Data Sheet, Rev. 1
Freescale Semiconductor
39
Preliminary — Subject to Change
Chapter 5 Revision History
MC9S08AC128 MCU Series Data Sheet, Rev. 1
40
Freescale Semiconductor
Preliminary — Subject to Change
Preliminary — Subject to Change
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09/2008
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Preliminary — Subject to Change