FREESCALE MPC17517DTBR2

Freescale Semiconductor
Advance Information
Document Number: MPC17517
Rev. 2.0, 7/2006
1.0 A 6.8 V Dual Motor Driver IC
The 17517 is a monolithic triple totem-pole-output power IC
designed to be used in portable electronic applications to control
small DC motors and solenoids. The 17517 can operate efficiently
with supply voltages as low as 2.0 V to as high as 6.8 V. Its low
RDS(ON) totem-pole output MOSFETs (0.46 Ω typical) can provide
continuous drive currents of 1.0 A and handle peak currents up to
3.0 A. It is easily interfaced to low-cost MCUs via parallel 3.0 V- or
5.0 V-compatible logic. The device can be pulse width modulated
(PWM-ed) at up to 200 kHz.
The 17517 can drive two motors in two directions one at a time or
drive one motor in two directions and one solenoid with synchronous
rectification of freewheeling currents one at a time. Two-motor
operation is accomplished by hooking one motor between OUTA and
OUTB and hooking the other motor between OUTB and OUTC. Motor
plus solenoid operation is accomplished by hooking a motor between
OUTA and OUTB and a solenoid between OUTC and GND.
This device contains an integrated charge pump and level shifter
(for gate drive voltages), integrated shoot-through current protection
(cross-conduction suppression logic and timing), and undervoltage
detection and shutdown circuitry.
The 17517 has four operating modes: Forward, Reverse, Brake,
and Tri-Stated (High Impedance).
17517
DUAL MOTOR DRIVER
DTB SUFFIX
98ASH70247A
16-PIN TSSOP
ORDERING INFORMATION
Device
Temperature
Range (TA)
Package
MPC17517DTB/R2
-20°C to 65°C
16 TSSOP
Features
• 2.0 V to 6.8 V Continuous Operation
• Output Current 1.0 A (DC), 3.0 A (Peak)
• MOSFETs < 600 mΩ RDS(ON) @ 25°C Guaranteed
• 3.0 V/ 5.0 V TTL- / CMOS-Compatible Inputs
• PWM Frequencies up to 200 kHz
• Undervoltage Shutdown
5.0 V
5.0 V
17517
VDD
C1L
C1H
C2L
C2H
Cres
VM
OUTC
OUTA
Solenoid
MCU
EN1
EN2
IN1
IN2
MOTOR
OUTB
GND
Figure 1. 17517 Simplified Application Diagram
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2006. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
C2L
C2H
OSC, Charge Pump
C1H
C1L
Low Voltage
Detector
VMAB
VC
VMC
IN2
Control Logic
IN1
Level Shifter Predriver
VG
OUTC
OUTB
EN1
OUTA
EN2
GND
Figure 2. 17517 Simplified Internal Block Diagram
17517
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Analog Integrated Circuit Device Data
Freescale Semiconductor
PIN CONNECTIONS
PIN CONNECTIONS
VDD
1
16
OUTC
VM
2
15
GND
OUTA
3
14
OUTB
CRES
4
13
VM
C2H
5
12
C1H
C2L
6
11
C1L
IN1
7
10
EN2
IN2
8
9
EN1
Figure 3. 17517 Pin Connections
Table 1. 17517 Pin Definitions
A functional description of each pin can be found in the Functional Pin Description section beginning on page 9.
Pin Number
Pin Name
Formal Name
Definition
1
VDD
Control Circuit Power Supply
2, 13
VM
Motor Drive Power Supply
3
OUTA
Output A
4
CRES
Charge Pump Output Capacitor
Connection
5
C2H
Charge Pump 2H
Charge pump bucket capacitor 2 (positive pole).
6
C2L
Charge Pump 2L
Charge pump bucket capacitor 2 (negative pole).
7
IN1
Input Control 1
Control signal input 1 pin.
8
IN2
Input Control 2
Control signal input 2 pin.
9
EN1
Enable Control Signal Input 1
Enable control signal input 1 pin.
10
EN2
Enable Control Signal Input 2
Enable control signal input 2 pin.
11
C1L
Charge Pump 1L
Charge pump bucket capacitor 1 (negative pole).
12
C1H
Charge Pump 1H
Charge pump bucket capacitor 1 (positive pole).
14
OUTB
Output B
Driver output B pin.
15
GND
Ground
Ground connection.
16
OUTC
Output C
Driver output C pin.
Positive power source connection for control circuit.
Motor power supply voltage input pins.
Driver output A pin.
Charge pump reservoir capacitor pin.
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3
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Ratings
Symbol
Value
Unit
VM
-0.5 to 8.0
V
CRES
-0.5 to 14
V
Logic Supply Voltage
VDD
-0.5 to 7.0
V
Signal Input Voltage
VIN
-0.5 to VDD + 0.5
V
ELECTRICAL RATINGS
Motor Supply Voltage
Charge Pump Output Voltage
V
Driver Output Current
A
Continuous
IO
1.0
IOPK
3.0
Human Body Model
VESD1
± 2000
Machine Model
VESD2
± 100
TSTG
-65 to 150
°C
Operating Junction Temperature
TJ
-20 to 150
°C
Operating Ambient Temperature
TA
-20 to 65
°C
RθJA
190
°C/W
PD
657
mW
TSOLDER
245
°C
Peak (1)
ESD Voltage
(2)
V
THERMAL RATINGS
Storage Temperature Range
Thermal Resistance
Power Dissipation
(3)
(4)
Soldering Temperature
(5)
Notes
1. TA = 25°C, 10 ms pulse width at 200 ms intervals.
2.
ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω), ESD2 testing is performed in
accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω).
3.
4.
37 mm x 50 mm Cu area (1.6 mm FR-4 PCB).
Maximum at TA = 25°C.
5.
Soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
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ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics
Characteristics noted under conditions TA = 25°C, VDD = VM = 5.0 V, GND = 0 V unless otherwise noted. Typical values noted
reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
Motor Supply Voltage
VM
2.0
5.0
6.8
V
Logic Supply Voltage
VDD
2.7
5.0
5.7
V
C1, C2, C3
0.01
0.1
1.0
µF
VMSTBY
–
–
1.0
µA
VDDSTBY
–
–
1.0
mA
POWER
Capacitor for Charge Pump
Standby Power Supply Current
I
Motor Supply Standby Current
Logic Supply Standby Current
(6)
I
Operating Power Supply Current
I
mA
VDD
–
–
3.0
RES
–
–
0.7
1.5
2.0
2.5
–
0.46
0.60
12
13
13.5
10
11.2
–
VIN
0
–
VDD
V
High-Level Input Voltage
VIH
VDD x 0.7
–
–
V
Low-Level Input Voltage
VIL
–
–
VDD x 0.3
V
High-Level Input Current
IIH
–
–
1.0
µA
Low-Level Input Current
IIL
-1.0
–
–
µA
Logic Supply Current
(7)
IC
Charge Pump Circuit Supply Current
Low-Voltage Detection Circuit
Detection Voltage (VDD)
VDDDET
(8)
Driver Output ON Resistance (9)
RDS(ON)
V
W
GATE DRIVE
VC
RES
Gate Drive Voltage (10)
No Current Load
Gate Drive Ability (Internally Supplied)
I
V
V
CRESLOAD
CRES = -1.0 mA
V
CONTROL LOGIC
Logic Input Voltage
Logic Input Function (2.7 V < VDD < 5.7 V)
Notes
6.
7.
8.
9.
10.
IV
I
DDSTBY includes current to the predriver circuit.
VDD includes current to the predriver circuit.
Detection voltage is defined as when the output becomes high-impedance after VDD drops below the detection threshold. When the gate
V
V
voltage CRES is applied from an external source, CRES = 7.5 V.
IO = 1.0 A source + sink.
Input logic signal not present.
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5
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions TA = 25°C, VDD = VM = 5.0 V, GND = 0 V unless otherwise noted. Typical values noted
reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
fIN
–
–
200
kHz
INPUT (IN1, IN2, EN1, EN2)
Pulse Input Frequency
Input Pulse Rise Time
Input Pulse Fall Time
(11)
(13)
tR
–
–
1.0
(12)
µs
1.0
(12)
µs
tF
–
–
Turn-ON Time
tPLH
–
0.1
0.5
Turn-OFF Time
tPHL
–
0.1
0.5
tVGON
tV DET
–
0.1
3.0
ms
–
–
10
ms
OUTPUT
µs
Propagation Delay Time
Charge Pump Wake-Up Time (14)
Low-Voltage Detection Time
Notes
11.
12.
13.
14.
DD
Time is defined between 10% and 90%.
That is, the input waveform slope must be steeper than this.
Time is defined between 90% and 10%.
When C1 = C2 = C3 = 0.1 µF.
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Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
TIMING DIAGRAMS
IN1, IN2,
EN1, EN2
VDDDETon
50%
tPHL
tPLH
OUTA,
OUTB,
OUTC
2.5 V/3.5 V
VDD
0.8 V/
1.5 V
VDDDEToff
50%
tV
tV
DDDET
DDDET
90%
90%
10%
Figure 4. tPLH, tPHL, and tPZH Timing
0%
(<1.0 µA)
IM
Figure 5. Low-Voltage Detection Timing
VDD
t VGON
V
11 V
CRES
Figure 6. Charge Pump Timing
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7
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
Table 5. Truth Table
INPUT
IN1
IN2
OUTPUT
EN1
EN2
OUTA
OUTB
OUTC
L
L
Z
Z
Z
SHUTDOWN MODE
X
X
CHANNEL 1 (A–B) DRIVING MODE
H
H
H
L
L
L
Z
H
L
H
L
H
L
Z
L
H
H
L
L
H
Z
L
L
H
L
Z
Z
Z
CHANNEL 2 (B–C) DRIVING MODE
H
H
L
H
Z
L
L
H
L
L
H
Z
H
L
L
H
L
H
Z
L
H
L
L
L
H
Z
Z
Z
HALF-BRIDGE (C) DRIVING MODE
H
H
H
H
Z
Z
Z
H
L
H
H
Z
Z
H
L
H
H
H
Z
Z
L
L
L
H
H
Z
Z
Z
H = High.
L = Low.
Z = High impedance.
X = Don’t care.
17517
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Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 17517 is a triple totem-pole output H-Bridge power IC
designed to drive small dc motors used in portable
electronics. The 17517 can operate efficiently with supply
voltages as low as 2.0 V to as high as 6.8 V, and provide
continuos motor drive currents of 1.0 A while handling peak
currents up to 3.0 A. It is easily interfaced to low cost MCUs
via parallel 3.0 V- or 5.0 V-compatible logic. The device can
be pulse width modulated (PWM-ed) at up to 200 kHz. The
17517 can drive two motors in two directions one at a time; or
it can drive one motor in two directions and one solenoid with
synchronous rectification of freewheeling currents one at a
time. Two-motor operation is accomplished by hooking one
motor between OUTA and OUTB, and the other motor
between OUTB and OUTC. Motor + solenoid operation is
accomplished by hooking a motor between OUTA and OUTB
and placing a solenoid between OUTC and GND. Table 5,
Truth Table, page 8, describes the operating states versus
the input conditions.
As shown in Figure 2, 17517 Simplified Internal Block
Diagram, page 2, the 17517 is a monolithic triple totem-pole
output bridge with built-in charge pump circuitry. Each of the
six MOSFETs forming the triple totem-pole output has an
RDS(ON) of ≤ 0.6 Ω (guaranteed by design). The IC has an
integrated charge pump and level shifter (for gate drive
voltages). Additionally, the IC has a built-in shoot-through
current protection circuit and undervoltage lockout function.
This IC has four operating modes: Forward, Reverse, Brake,
and Tri-Stated (High Impedance).
FUNCTIONAL PIN DESCRIPTION
DRIVER OUTPUT (OUTA, OUTB, OUTC)
These pins provide the connection to the internal power
MOSFET triple-totem-pole H-bridge of the IC.
GROUND (GND)
Power and signal ground pin.
CHARGE PUMP OUTPUT CAPACITOR (CRES)
This pin provides the connection for the external reservoir
capacitor (output of the charge pump). Alternatively, this pin
can also be used as an input to supply gate-drive voltage
from an external source via a series current-limiting resistor.
The voltage at the CRES pin will be approximately three
times the VDD voltage, as the internal charge pump utilizes a
voltage tripler circuit. The VDDRES voltage is used by the IC to
supply gate drive for the internal power MOSFETs.
MOTOR DRIVE POWER SUPPLY (VM)
The two VM pins carry the main supply voltage and current
into the power sections of the IC. This supply then becomes
controlled and /or modulated by the IC as it delivers the power
to the load attached between OUTA and OUTB.
The VM pins must be connected together on the printed
circuit board with as short as possible traces offering as low
impedance as possible between pins.
CONTROL SIGNAL INPUT AND ENABLE CONTROL
SIGNAL INPUT (IN1, IN1, EN1, EN2)
These pins are input control pins used to control the
outputs. These pins are 3.0 V/ 5.0 V CMOS-compatible
inputs with hysteresis. These pins work together to control
OUTA, OUTB, and OUTC (refer to Table 5, Truth Table).
CHARGE PUMP BUCKET CAPACITOR (C1L, C1H,
C2L, C2H)
These two pairs of pins, the C1L and C1H and the C2L and
C2H, connect to the external bucket capacitors required by
the internal charge pump. The typical value for the bucket
capacitors is 0.1 µF.
CONTROL CIRCUIT POWER SUPPLY (VDD)
This pin carries the logic supply voltage and current into
the logic sections of the IC. VDD has an undervoltage
threshold. If the supply voltage drops below the undervoltage
threshold, the output power stage switches to a tri-state
condition. When the supply voltage returns to a level that is
above the threshold, the power stage automatically resumes
normal operation according to the established condition of
the input pins.
17517
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Freescale Semiconductor
9
TYPICAL APPLICATIONS
INTRODUCTION
TYPICAL APPLICATIONS
INTRODUCTION
Figure 7 shows a typical application for the 17517. When applying the gate voltage to the CRES pin from an external source,
be sure to connect it via a resistor equal to, or greater than, RG = VCRES / 0.02 Ω.
5.0 V
17517
VC
RES
< 14 V
RG > VCRES /0.02 Ω
NC
NC
NC
NC
C1L
C1H
C2L
C2H
VDD
VM
OUTA
CRES
RG
0.01 µF
OUTB
EN1
EN2
MCU
OUTC
IN1
IN1
GND
NC = No Connect
Figure 7. 17517 Typical Application Diagram
CEMF SNUBBING TECHNIQUES
PCB LAYOUT
Care must be taken to protect the IC from potentially
damaging CEMF spikes induced when commutating currents
in inductive loads. Typical practice is to provide snubbing of
voltage transients by placing a capacitor or zener at the
supply pin (VM) (see Figure 8).
When designing the printed circuit board (pcb), connect
sufficient capacitance between power supply and ground
pins to ensure proper filtering from transients. For all highcurrent paths, use wide copper traces and shortest possible
distances.
5.0 V
5.0 V
17517
VDD
VM
5.0 V
5.0 V
17517
VDD
VM
C1L
C1L
C1H
C1H
C2L
C2H
OUT
C2L
C2H
CRES
CRES
OUT
OUT
GND
OUT
GND
Figure 8. CEMF Snubbing Techniques
17517
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Analog Integrated Circuit Device Data
Freescale Semiconductor
PACKAGING
PACKAGE DIMENSIONS
PACKAGING
PACKAGE DIMENSIONS
For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below.
DTB SUFFIX
16-PIN
PLASTIC PACKAGE
98ASH70247A
ISSUE B
17517
Analog Integrated Circuit Device Data
Freescale Semiconductor
11
PACKAGING
PACKAGE DIMENSIONS
DTB SUFFIX
16-PIN
PLASTIC PACKAGE
98ASH70247A
ISSUE B
17517
12
Analog Integrated Circuit Device Data
Freescale Semiconductor
REVISION HISTORY
REVISION HISTORY
REVISION
2.0
DATE
7/2006
DESCRIPTION OF CHANGES
• Implemented Revision History page
• Converted to Freescale format and updated to the prevailing form and style
17517
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13
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MPC17517
Rev. 2.0
7/2006
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