MOTOROLA MPC17510EJ

Freescale Semiconductor, Inc.
MOTOROLA
Document order number: MPC17510
Rev 1.0, 03/2004
SEMICONDUCTOR TECHNICAL DATA
Advance Information
17510
1.2 A 15 V H-Bridge Motor Driver IC
Freescale Semiconductor, Inc...
The 17510 is a monolithic H-Bridge designed to be used in portable
electronic applications such as digital and SLR cameras to control small DC
motors.
1.2 A 15 V H-BRIDGE MOTOR
DRIVER IC
The 17510 can operate efficiently with supply voltages as low as 2.0 V to
as high as 15 V. Its low RDS(ON) H-Bridge output MOSFETs (0.45 Ω typical)
can provide continuous motor drive currents of 1.2 A and handle peak currents
up to 3.8 A. It is easily interfaced to low-cost MCUs via parallel 5.0 V
compatible logic. The device can be pulse width modulated (PWM-ed) at up to
200 kHz.
This device contains an integrated charge pump and level shifter (for gate
drive voltages), integrated shoot-through current protection (cross-conduction
suppression logic and timing), and undervoltage detection and shutdown
circuitry.
The 17510 has four operating modes: Forward, Reverse, Brake, and
Tri-Stated (High Impedance).
MTB SUFFIX
EJ (Pb-FREE) SUFFIX
CASE 948K-01
24-LEAD TSSOP
Features
• 2.0 V to 15 V Continuous Operation
• Output Current 1.2 A (DC), 3.8 A (Peak)
• 450 mΩ RDS(ON) H-Bridge MOSFETs
• 5.0 V TTL-/CMOS-Compatible Inputs
• PWM Frequencies up to 200 kHz
• Undervoltage Shutdown
• Cross-Conduction Suppression
• Pb-Free Packaging Designated by Suffix Code EJ
ORDERING INFORMATION
Device
Temperature
Range (TA)
Package
MPC17510EJ/R2
-30°C to 65°C
24 TSSOPW
Simplified Application Diagram
17510 Simplified Application Diagram
5.0 V
15 V
17510
VDD
C1L
C1H
C2L
C2H
CRES
MCU
VM
GOUT
OUT1
MOTOR
EN
GIN
IN1
IN2
OUT2
GND
This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Motorola, Inc. 2004
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C2H C2L C1H C1L
CRES
GOUT
Charge Pump
VM
LowVoltage
Detector
VDD
OUT1
Freescale Semiconductor, Inc...
IN1
IN2
Level
Shifter
Predriver
H-Bridge
OUT2
Control
Logic
EN
GIN
PGND
LGND
No Connect
Figure 1. 17510 Simplified Internal Block Diagram
17510
2
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OUT1
1
24
GIN
LGND
2
23
VDD
CRES
3
22
NC
NC
4
21
VM
OUT1
5
20
NC
PGND
6
19
PGND
NC
7
18
OUT2
VM
8
17
OUT2
IN1
9
16
EN
IN2
10
15
GOUT
C1H
11
14
C2H
C1L
12
13
C2L
TERMINAL FUNCTION DESCRIPTION
Terminal
Terminal
Name
Formal Name
1, 5
OUT1
Output 1
2
LGND
Logic Ground
3
CRES
Charge Pump Output
Capacitor Connection
4, 7,
20, 22
NC
No Connect
17, 18
OUT2
Output 2
6, 19
PGND
Power Ground
8, 21
VM
Motor Drive Power Supply
9
IN1
Input Control 1
Control signal input 1 terminal.
10
IN2
Input Control 2
Control signal input 2 terminal.
11
C1H
Charge Pump 1H
Charge pump bucket capacitor 1 (positive pole).
12
C1L
Charge Pump 1L
Charge pump bucket capacitor 1 (negative pole).
13
C2L
Charge Pump 2L
Charge pump bucket capacitor 2 (negative pole).
14
C2H
Charge Pump 2H
Charge pump bucket capacitor 2 (positive pole).
15
GOUT
Gate Driver Output
16
EN
Enable Control
Enable control signal input terminal.
23
VDD
Logic Supply
Control circuit power supply terminal.
24
GIN
Gate Driver Input
Definition
Driver output 1 terminals.
Logic ground.
Charge pump reservoir capacitor terminal.
No connection to these terminals.
Driver output 2 terminals.
Power ground.
Motor power supply voltage input terminals.
Output gate driver signal to external MOSFET switch.
LOW = True control signal for GOUT terminal.
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MAXIMUM RATINGS
All voltages are with respect to ground unless otherwise noted. Exceeding the ratings may cause a malfunction or permanent
damage to the device.
Rating
Symbol
Value
Unit
VM
-0.5 to 16
V
-0.5 to 13
V
Motor Supply Voltage
VC
Charge Pump Output Voltage (Note 1)
RES
Logic Supply Voltage
VDD
-0.5 to 6.0
V
Signal Input Voltage (EN, IN1, IN2, GIN)
VIN
-0.5 to VDD +0.5
V
IO
1.2
IOPK
3.8
Human Body Model (Note 3)
VESD1
±1900
Machine Model (Note 4)
VESD2
±130
TSTG
-65 to 150
°C
Operating Junction Temperature
TJ
-30 to 150
°C
Operating Ambient Temperature
TA
-30 to 65
°C
Power Dissipation (Note 5)
PD
1.0
W
RθJA
120
°C/W
TSOLDER
260
°C
A
Driver Output Current
Freescale Semiconductor, Inc...
Continuous
Peak (Note 2)
V
ESD Voltage
Storage Temperature
Thermal Resistance
Soldering Temperature (Note 6)
Notes
1. When supplied externally, connect via 3.0 kΩ resistor.
2. TA = 25°C, 10 ms pulse at 200 ms interval.
3.
ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω).
4.
ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω).
5.
TA = 25°C, RθJA = 120°C/W, 37 mm x 50 mm Cu area (1.6 mm FR-4 PCB).
6.
Soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause
malfunction or permanent damage to the device.
17510
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STATIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions TA = 25°C, VM = 15 V, VDD = 5.0 V, GND = 0 V unless otherwise noted. Typical values noted
reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
Motor Supply Voltage
VM
2.0
–
15
V
Logic Supply Voltage
VDD
4.0
–
5.5
V
C1, C2, C3
0.001
–
0.1
µF
–
–
1.0
µA
–
0.3
1.0
mA
–
3.3
4.0
mA
POWER
Capacitor for Charge Pump
Freescale Semiconductor, Inc...
Standby Power Supply Current (Note 7)
Motor Supply Standby Current
I
Logic Supply Standby Current
IV
VMSTBY
DDSTBY
IV
Logic Supply Current (Note 8)
DD
V
Low-Voltage Detection Circuit
Detection Voltage (VDD) (Note 9)
VDDDET
1.5
2.5
3.5
Detection Voltage (VM)
VMDET
4.0
5.0
6.0
–
0.45
0.55
Ω
RDS(ON)
Driver Output ON Resistance (Note 10)
VM = 2.0 V, 8.0 V, 15 V
GATE DRIVE
VC
Gate Drive Voltage (Note 11)
No Current Load
VC
Gate Drive Ability (Internally Supplied)
I
V
RES
12
13
13.5
10
11.2
–
V
RESload
CRES = -1.0 mA
V
Gate Drive Output
V
V
V
CRES
IOUT = -50 µA
VGOUThigh
IIN = 50 µA
VGOUTlow
LGND
LGND +0.1
LGND+0.5
VIN
0
–
VDD
V
High-Level Input Voltage
VIH
VDD x 0.7
–
–
V
Low-Level Input Voltage
VIL
–
–
VDD x 0.3
V
High-Level Input Current
IIH
–
–
1.0
µA
Low-Level Input Current
IIL
-1.0
–
–
µA
EN/ GIN Terminal
IIL
-200
-50
–
µA
CRES -0.5
CRES - 0.1
CONTROL LOGIC
Logic Input Voltage (EN, IN1, IN2, GIN)
Logic Input Function (4.0 V < VDD < 5.5 V)
Notes
7. Excluding pull-up resistor current, including current of gate-drive circuit.
8. fIN = 100 kHz.
9.
Detection voltage is defined as when the output becomes high-impedance after VDD drops below the detection threshold. When the gate
V
V
voltage CRES is applied from an external source, CRES = 7.5 V.
10.
IO = 1.2 A source + sink.
11.
Input logic signal not present.
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DYNAMIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions TA = 25°C, VM = 15 V, VDD = 5.0 V, GND = 0 V unless otherwise noted. Typical values noted
reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
Pulse Input Frequency
fIN
–
–
200
kHz
Input Pulse Rise Time (Note 12)
tR
–
–
1.0
(Note 13)
µs
Input Pulse Fall Time (Note 14)
tF
–
–
1.0
(Note 13)
µs
Turn-ON Time
tPZH
–
0.3
1.0
Turn-ON Time
tPLH
–
1.2
2.0
tPHL
–
0.5
1.0
Turn-ON Time
tTON
–
–
10
Turn-OFF Time
tTOFF
–
–
10
fOSC
100
200
400
kHz
–
0.1
1.0
ms
–
–
10
ms
INPUT (EN, IN1, IN2, GIN)
Freescale Semiconductor, Inc...
OUTPUT
µs
Propagation Delay Time
Turn-OFF Time
µs
GOUT Output Delay Time (Note 15)
Charge Pump Circuit
Oscillator Frequency
tVC
Rise Time (Note 16)
t
Low-Voltage Detection Time
Notes
12.
13.
14.
15.
16.
17510
6
RESon
VDDDET
Time is defined between 10% and 90%.
That is, the input waveform slope must be steeper than this.
Time is defined between 90% and 10%.
Load is 500 pF.
Time to charge CRES to 11 V after application of VDD.
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Timing Diagrams
VDDDETon
IN1, IN2, EN
(GIN)
VDD
50%
50%
1.5 V
tPZH*,
tPLH
(tTON)
Freescale Semiconductor, Inc...
tV
tV
DDDET
tPHL
(tTOFF)
DDDET
90%
OUTn
(GOUT)
VDDDEToff
3.5 V
90%
IM
0%
(<1.0 µA)
10%
* The last state is “Z”.
Figure 2. tPLH, tPHL, and tPZH Timing
Figure 3. Low-Voltage Detection Timing
Table 1. Truth Table
INPUT
OUTPUT
EN
IN1
IN2
GIN
OUT1
OUT2
GOUT
H
L
L
X
Z
Z
X
H
H
L
X
H
L
X
H
L
H
X
L
H
X
H
H
H
X
L
L
X
L
X
X
X
L
L
L
H
X
X
L
X
X
H
H
X
X
H
X
X
L
H = High.
L = Low.
Z = High impedance.
X = Don’t care.
The GIN terminal and EN terminal are pulled up to VDD with internal resistance.
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SYSTEM/APPLICATION INFORMATION
INTRODUCTION
Freescale Semiconductor, Inc...
The 17510 is a monolithic H-Bridge power IC applicable to
small DC motors used in portable electronics. The 17510 can
operate efficiently with supply voltages as low as 2.0 V to as
high as 15 V, and it can provide continuos motor drive currents
of 1.2 A while handling peak currents up to 3.8 A. It is easily
interfaced to low-cost MCUs via parallel 5.0 V-compatible logic.
The device can be pulse width modulated (PWM-ed) at up to
200 kHz. The 17510 has four operating modes: Forward,
Reverse, Brake, and Tri-Stated (High Impedance).
Basic protection and operational features (direction, dynamic
braking, PWM control of speed and torque, main power supply
undervoltage detection and shutdown, logic power supply
undervoltage detection and shutdown), in addition to the 1.0 A
rms output current capability, make the 17510 a very attractive,
cost-effective solution for controlling a broad range of small DC
motors. In addition, a pair of 17510 devices can be used to
control bipolar stepper motors. The 17510 can also be used to
excite transformer primary windings with a switched square
wave to produce secondary winding AC currents.
As shown in Figure 1, 17510 Simplified Internal Block
Diagram, page 2, the 17510 is a monolithic H-Bridge with builtin charge pump circuitry. For a DC motor to run, the input
conditions need to be set as follows: ENable input logic HIGH,
one INput logic LOW, and the other INput logic HIGH (to define
output polarity). The 17510 can execute dynamic braking by
setting both IN1 and IN2 logic HIGH, causing both low-side
MOSFETs in the output H-Bridge to turn ON. Dynamic braking
can also implemented by taking the ENable logic LOW. The
output of the H-Bridge can be set to an open-circuit highimpedance (Z) condition by taking both IN1 and IN2 logic LOW.
(refer to Table 1, Truth Table, page 7).
The 17510 outputs are capable of providing a continuous DC
load current of up to 1.2 A. An internal charge pump supports
PWM frequencies to 200 kHz. The EN terminal also controls the
charge pump, turning it off when EN = LOW, thus allowing the
17510 to be placed in a power-conserving sleep mode.
FUNCTIONAL TERMINAL DESCRIPTION
OUT1 and OUT2
The OUT1 and OUT2 terminals provide the connection to the
internal power MOSFET H-Bridge of the IC. A typical load
connected between these terminals would be a small DC motor.
These outputs will connect to either VM or PGND, depending
on the states of the control inputs (refer to Table 1, Truth Table,
page 7).
PGND and LGND
The power and logic ground terminals (PGND and LGND)
should be connected together with a very low-impedance
connection.
CRES
The CRES terminal provides the connection for the external
reservoir capacitor (output of the charge pump). Alternatively
this terminal can also be used as an input to supply gate-drive
voltage from an external source via a series current-limiting
resistor. The voltage at the CRES terminal will be approximately
three times the VDD voltage, as the internal charge pump
utilizes a voltage tripler circuit. The VCRES voltage is used by
the IC to supply gate drive for the internal power MOSFET
H-Bridge.
VM
The VM terminals carry the main supply voltage and current
into the power sections of the IC. This supply then becomes
controlled and/or modulated by the IC as it delivers the power
to the load attached between OUT1 and OUT2. All VM
17510
8
terminals must be connected together on the printed circuit
board with as short as possible traces offering as low
impedance as possible between terminals.
VM has an undervoltage threshold. If the supply voltage
drops below the undervoltage threshold, the output power
stage switches to a tri-state condition. When the supply voltage
returns to a level that is above the threshold, the power stage
automatically resumes normal operation according to the
established condition of the input terminals.
IN1, IN2, and EN
The IN1, IN2, and EN terminals are input control terminals
used to control the outputs. These terminals are 5.0 V CMOScompatible inputs with hysteresis. The IN1, IN2, and EN work
together to control OUT1 and OUT2 (refer to Table 1, Truth
Table).
GIN
The GIN input controls the GOUT terminal. When GIN is set
logic LOW, GOUT supplies a level-shifted high-side gate drive
signal to an external MOSFET. When GIN is set logic HIGH,
GOUT is set to GND potential.
C1L and C1H, C2L and C2H
These two pairs of terminals, the C1L and C1H and the C2L
and C2H, connect to the external bucket capacitors required by
the internal charge pump. The typical value for the bucket
capacitors is 0.1 µF.
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GOUT
The GOUT output terminal provides a level-shifted, high-side
gate drive signal to an external MOSFET with Ciss up to 500 pF.
VDD
undervoltage threshold. If the supply voltage drops below the
undervoltage threshold, the output power stage switches to a
tri-state condition. When the supply voltage returns to a level
that is above the threshold, the power stage automatically
resumes normal operation according to the established
condition of the input terminals.
The VDD terminal carries the 5.0 V supply voltage and
current into the logic sections of the IC. VDD has an
APPLICATIONS
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Typical Application
Figure 4 shows a typical application for the 17510.
5.0 V
17510
VDD
C1L
C1H
C2L
C2H
CRES
MCU
VM
GOUT
OUT1
Motor
EN
GIN
IN1
IN2
Solenoid
OUT2
GND
Figure 4. 17510 Typical Application Diagram
CEMF Snubbing Techniques
Care must be taken to protect the IC from potentially
damaging CEMF spikes induced when commutating currents in
inductive loads. Typical practice is to provide snubbing of
voltage transients by placing a capacitor or zener at the supply
terminal (VM) (see Figure 5).
5.0 V
15 V
17510
VM
VDD
5.0 V
15 V
17510
VM
VDD
C1L
OUT1
C1H
C2L
C2H
CRES OUT2
C1L
OUT1
C1H
C2L
C2H
CRES OUT2
GND
GND
Figure 5. CEMF Snubbing Techniques
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PACKAGE DIMENSIONS
MTB SUFFIX
EJ (Pb-FREE) SUFFIX
24-LEAD TSSOP WIDE BODY
PLASTIC PACKAGE
CASE 948K-01
ISSUE O
24X
K
REF
0.10 (0.004)
Freescale Semiconductor, Inc...
0.15 (0.006) T U
M
T U
V
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH OR
GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH
OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE
ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED AT
DATUM PLANE -W-.
S
S
2X
L/2
24
13
B
-U-
L
PIN 1
IDENT.
1
0.15 (0.006) T U
S
12
S
A
-V-W-
C
0.10 (0.004)
-T-
G
SEATING
PLANE
DETAIL E
D
H
N
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
7.70
7.90
5.50
5.70
--1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.27
0.37
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
7.60 BSC
0°
8°
INCHES
MIN
MAX
0.303
0.311
0.216
0.224
--0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.011
0.015
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.299 BSC
0°
8°
0.25 (0.010)
M
N
F
DETAIL E
17510
10
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NOTES
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17510
11
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MPC17510
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