To Top / Lineup / Index FUJITSU SEMICONDUCTOR DATA SHEET DS05-11147-1E MEMORY Un-buffered 8 M × 64 BIT SYNCHRONOUS DYNAMIC RAM SO-DIMM MB8508S064CE-100/-100L 144-pin, 2 Clock, 1-bank, based on 8 M × 8 Bit SDRAMs with SPD ■ DESCRIPTION The Fujitsu MB8508S064CE is a fully decoded, CMOS Synchronous Dynamic Random Access Memory (SDRAM) Module consisting of eight MB81F64842C devices which organized as two banks of 8 M × 8 bits and a 2K-bit serial EEPROM on a 144-pin glass-epoxy substrate. The MB8508S064CE features a fully synchronous operation referenced to a positive edge clock whereby all operations are synchronized at a clock input which enables high performance and simple user interface coexistence. The MB8508S064CE is optimized for those applications requiring high speed, high performance and large memory storage, and high density memory organizations. This module is ideally suited for workstations, PCs, laser printers, and other applications where a simple interface is needed. ■ PRODUCT LINE & FEATURES Parameter MB8508S064CE -100 Clock Frequency -100L 100 MHz max. Burst Mode Cycle Time 10 ns min. Access Time from Clock 8.5 ns max. (CL = 3) Operating Current 680 mA max. Power Down Mode Current (ICC2P) 16 mA max. 8 mA max. Self Refresh Current (ICC6) 8 mA max. 4 mA max. • Unbuffered 144-pin SO-DIMM Socket Type (Lead pitch: 0.8 mm) • Conformed to JEDEC Standard (2 CLK) • Organization: 8,388,608 words × 64 bits • Memory: MB81F64842C (8 M × 8, 4-bank) × 8 pcs. • 3.3 V ±0.3 V Supply Voltage • All input/output LVTTL compatible • 4096 Refresh Cycle every 65.6 ms • • • • Auto and Self Refresh CKE Power Down Mode DQM Byte Masking (Read/Write) Serial Presence Detect (SPD) with Serial EEPROM: JEDEC Standard SPD Format • Module size: 1.25” (height) × 2.66” (length) × 0.15” (thickness) • CL-tRCD-tRP: 3-3-3 clk min. @100 MHz, 2-2-2 clk min. @66 MHz To Top / Lineup / Index MB8508S064CE-100/-100L ■ PACKAGE 144-pin plastic SO DIMM (socket type) (MDS-144P-P09) Package and Ordering Information – 144-pin SO-DIMM, order as MB8508S064CE-100DG (DG = Std. power ver., Gold Pad) -100LDG (LDG = Low power ver., Gold Pad) 2 To Top / Lineup / Index MB8508S064CE-100/-100L ■ PIN ASSIGNMENTS Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name 1 VSS 49 DQ13 97 DQ22 2 VSS 50 DQ45 98 3 DQ0 51 DQ14 99 DQ23 4 DQ32 52 DQ46 100 DQ55 5 DQ1 53 DQ15 101 VCC 6 DQ33 54 DQ47 102 VCC 7 DQ2 55 VSS 103 A6 8 DQ34 56 VSS 104 A7 9 DQ3 57 N.C. 105 A8 10 DQ35 58 N.C. 106 BA0 11 VCC 59 N.C. 107 VSS 12 VCC 60 N.C. 108 VSS 13 DQ4 61 CLK0 109 A9 14 DQ36 62 CKE0 110 BA1 15 DQ5 63 VCC 111 A10 16 DQ37 64 VCC 112 A11 17 DQ6 65 RAS 113 VCC 18 DQ38 66 CAS 114 VCC 19 DQ7 67 WE 115 DQMB2 20 DQ39 68 N.C. 116 DQMB6 21 VSS 69 CS0 117 DQMB3 22 VSS 70 N.C. 118 DQMB7 23 DQMB0 71 N.C. 119 VSS 24 DQMB4 72 N.C. 120 VSS 25 DQMB1 73 N.C. 121 DQ24 26 DQMB5 74 CLK1 122 DQ56 27 VCC 75 VSS 123 DQ25 28 VCC 76 VSS 124 DQ57 29 A0 77 N.C. 125 DQ26 30 A3 78 N.C. 126 DQ58 31 A1 79 N.C. 127 DQ27 32 A4 80 N.C. 128 DQ59 33 A2 81 VCC 129 VCC 34 A5 82 VCC 130 VCC 35 VSS 83 DQ16 131 DQ28 36 VSS 84 DQ48 132 DQ60 37 DQ8 85 DQ17 133 DQ29 38 DQ40 86 DQ49 134 DQ61 39 DQ9 87 DQ18 135 DQ30 40 DQ41 88 DQ50 136 DQ62 41 DQ10 89 DQ19 137 DQ31 42 DQ42 90 DQ51 138 DQ63 43 DQ11 91 VSS 139 VSS 44 DQ43 92 VSS 140 VSS 45 VCC 93 DQ20 141 SDA 46 VCC 94 DQ52 142 SCL 47 DQ12 95 DQ21 143 VCC 48 DQ44 96 DQ53 144 VCC DQ54 3 To Top / Lineup / Index MB8508S064CE-100/-100L TOP VIEW 67.60 mm Chip 0 Chip 1 Chip 2 Chip 3 1 59 61 143 2 60 62 144 Chip 5 Chip 6 31.75 mm Chip 4 Chip 7 (MDS-144P-P09) ■ PIN DESCRIPTIONS 4 Symbol I/O A0 to A11 I BA0, BA1 Function Symbol I/O Function Address Input CS0 I I Bank Address DQ0 to DQ63 RAS I Row Address Strobe VCC — Power Supply (+3.3 V) CAS I Column Address Strobe VSS — Ground (0 V) WE I Write Enable N.C. — No Connection DQMB0 to DQMB7 I Data (DQ) Mask SCL I Serial PD Clock CLK0, CLK1 I Clock Input CKE0 I Clock Enable SDA I/O Chip Select I/O Data Input/Data Output Serial PD Address/Data Input/Output To Top / Lineup / Index MB8508S064CE-100/-100L ■ SERIAL-PD INFORMATION Byte Hex Value Function Described -100/100L 0 Defines Number of Bytes Written into Serial Memory at Module Manufacture 1 Total Number of Bytes of SPD Memory Device 2 Fundamental Memory Type 3 Number of Row Addresses 4 Number of Column Addresses 5 Number of Module Banks 6 Data Width 7 Data Width (Continuation) 8 Interface Type 9 SDRAM Cycle Time (Highest CAS Latency) 10 SDRAM Access from Clock (Highest CAS Latency) 11 DIMM Configuration Type 12 Refresh Rate/Type 13 Primary SDRAM Width 14 Error Checking SDRAM Width 15 Minimum Clock Delay for Back to Back Random Column Addresses 16 Burst Lengths Supported 17 Number of Banks on Each SDRAM Device 18 CAS Latency 19 CS Latency 20 Write Latency 21 SDRAM Module Attributes 22 SDRAM Device Attributes 23 SDRAM Cycle Time (2nd. Highest CAS Latency) 24 SDRAM Access from Clock (2nd. Highest CAS Latency) 25 SDRAM Cycle Time (3rd. Highest CAS Latency) 26 SDRAM Access from Clock (3rd. Highest CAS Latency) 27 Precharge to Activate Min. (tRP) 28 Row Activate to Row Activate Min. (tRRD) 29 RAS to CAS Delay Min. (tRCD) 30 Activate to Precharge Minimum Time (tRAS) 31 Module Bank Density 32 to 61 Unused Storage Locations 62 SPD Data Revision Code 63 Checksum for Byte 0 to 62 64 to 98 Manufacturer’s Information: Unused Storage 99 to 125 Vendor Specific Data: Unused Storage 126 Intel Specification Frequency 127 Intel Specification Details for 66 MHZ Support 128+ Unused Storage Locations 128 Byte 80h 256 Byte SDRAM 12 9 1 bank 64 bit +0 LVTTL 10 ns 8.5 ns Non-Parity Self, Normal ×8 0 1 Cycle 08h 04h 0Ch 09h 01h 40h 00h 01h A0h 85h 00h 80h 08h 00h 01h 1, 2, 4, 8, Page 4 bank 2, 3 0 0 UN-buffer *1 15 ns 9 ns No Support No Support 30 ns 20 ns 30 ns 60 ns 64 MByte — 1 *2 — — 66 MHZ CL=2, 3 — 8Fh 04h 06h 01h 01h 00h 0Eh F0h 90h 00h 00h 1Eh 14h 1Eh 3Ch 10h 00h 01h 57h 00h 00h 66h CFh — Note: Any write operation must NOT be executed into the addresses of Byte 0 to Byte 127. Some or all data stored into Byte 0 to Byte 127 may be broken. *1. SDRAM Device Attributes Bit7 Bit6 Bit5 Bit4 TBD TBD Upper VCC tolerance 0 = 10% Lower VCC tolerance 0 = 10% 0 0 0 0 Bit3 Supports Write 1 /Read Burst 1 Bit2 Bit1 Bit0 Supports Precharge All Supports AutoPrecharge Supports Early RAS Precharge 1 1 0 *2.Checksum for Bytes 0 to 62 This byte is the checksum for bytes 0 through 62. This byte contains the value of the low 8-bits of the arithmetic sum of bytes 0 through 62. 5 To Top / Lineup / Index MB8508S064CE-100/-100L ■ BLOCK DIAGRAM A0 to A11, BA0, BA1 RAS CAS WE Add. RAS CAS WE 8 M × 8 DQM Chip 0 DQMB0 10 Ω CKE CS CLK DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQMB4 Add. RAS CAS WE DQM 8M×8 Chip 4 CKE CS CLK DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 CLK0 10 Ω Add. RAS CAS WE DQM DQMB1 CLK 8M×8 Chip 1 CKE CS Add. RAS CAS WE DQM DQMB2 10 Ω 8M×8 Chip 2 CKE CS CLK DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQMB5 Add. RAS CAS WE DQM CLK 8M×8 Chip 5 CKE CS DQMB6 Add. RAS CAS WE DQM 8M×8 Chip 6 CKE CS CLK DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 CLK1 10 Ω Add. RAS CAS WE DQM DQMB3 CLK 8M×8 Chip 3 CKE CS DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 CKE0 CS0 SERIAL EEPROM SCL SCL A0 6 SDA A1 A2 SDA DQMB7 Add. RAS CAS WE DQM CLK 8M×8 Chip 7 CKE CS DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 To Top / Lineup / Index MB8508S064CE-100/-100L ■ ABSOLUTE MAXIMUM RATINGS (See WARNING) Parameter Value Symbol Min. Max. Unit Supply Voltage* VCC –0.5 +4.6 V Input Voltage* VIN –0.5 +4.6 V Output Voltage* VOUT –0.5 +4.6 V Storage Temperature TSTG –55 +125 °C Power Dissipation PD — 8.0 W Output Current (D.C.) IOUT –50 +50 mA * : Voltages referenced to VSS (= 0 V) WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. ■ RECOMMENDED OPERATING CONDITIONS Parameter Notes Supply Voltage *1 Value Symbol Unit Min. Typ. Max. VCC 3.0 3.3 3.6 V VSS 0 0 0 V Input High Voltage, All Inputs *1, 2 VIH 2.0 — VCC +0.5 V Input Low Voltage, All Inputs *1, 3 VIL –0.5 — 0.8 V TA 0 — +70 °C Ambient Temperature *1. Voltages referenced to VSS (= 0 V) VIH 4.6 V 50% of pulse amplitude VIH VIHmin VIL Pulse width ≤ 5 ns VILmax VIL 50% of pulse amplitude Pulse width ≤ 5 ns *2. Overshoot limit: VIH (max) = 4.6 V for pulse width <= 5 ns acceptable, pulse width measured at 50% of pulse amplitude. –1.5V *3. Undershoot limit: VIL (min) = VSS –1.5 V for pulse width <= 5 ns acceptable, pulse width measured at 50% of pulse amplitude. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating conditionranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 7 To Top / Lineup / Index MB8508S064CE-100/-100L ■ CAPACITANCE (VCC = +3.3 V, f = 1 MHz, TA = +25°C) Parameter Input Capacitance Input/Output Capacitance 8 Symbol Value Min. Max. Unit A0 to A11, BA0, BA1 CIN1 — 48 pF RAS, CAS, WE CIN2 — 42 pF CS0 CIN3 — 49 pF CKE0 CIN4 — 40 pF CLK0, CLK1 CIN5 — 32 pF DQMB0 to DQMB7 CIN6 — 13 pF SCL CSCL — 6 pF SDA CSDA — 7 pF DQ0 to DQ63 CDQ — 10 pF To Top / Lineup / Index MB8508S064CE-100/-100L ■ DC CHARACTERISTICS (At recommended operating conditions unless otherwise noted.) Notes 1, 2 Value Parameter Operating Current (Average Power Supply Current) Precharge Standby Current (Power Supply Current) Active Standby Current (Power Supply Current) Notes Symbol *3 Condition Min. Unit Max. Std. ver. Low ver. ICC1S Burst: Length = 1 tRC = min for BL = 1 tCK = min One Bank Active, Outputs Open Addresses changed up to 1-time during tCK (min.) 0 V ≤ VIN ≤ VIL (max.) VIH (min.) ≤ VIN ≤ VCC — ICC2P CKE = VIL, All Banks Idle tCK = min, Power Down Mode 0 V ≤ VIN ≤ VIL (max.) VIH (min.) ≤ VIN ≤ VCC — 16 8 mA ICC2PS CKE = VIL, All Banks Idle CLK = H or L, Power Down Mode 0 V ≤ VIN ≤ VIL (max.) VIH (min.) ≤ VIN ≤ VCC — 8 4 mA ICC2N CKE = VIH, All Banks Idle, tCK = min NOP commands only, Input signals (except to CMD) are changed 1-time during 3 clock cycles 0 V ≤ VIN ≤ VIL (max.) VIH (min.) ≤ VIN ≤ VCC — 80 mA ICC2NS CKE = VIH, All Banks Idle CLK = H or L, Input signal are stable 0 V ≤ VIN ≤ VIL (max.) VIH (min.) ≤ VIN ≤ VCC — 16 mA ICC3P CKE = VIL, Any Bank Active tCK = min. 0 V ≤ VIN ≤ VIL (max.) VIH (min.) ≤ VIN ≤ VCC — 16 8 mA ICC3PS CKE = VIL, Any Bank Active CLK = H or L 0 V ≤ VIN ≤ VIL (max.) VIH (min.) ≤ VIN ≤ VCC — 8 4 mA ICC3N CKE = VIH, Any Bank Active tCK = min., NOP commands only, Input signals (except to CMD) are changed 1-time during 3 clock cycles 0 V ≤ VIN ≤ VIL (max.) VIH (min.) ≤ VIN ≤ VCC — 120 mA ICC3NS CKE = VIH, Any Bank Active CLK = H or L 0 V ≤ VIN ≤ VIL (max.) VIH (min.) ≤ VIN ≤ VCC — 16 mA *3 *3 680 mA (Continued) 9 To Top / Lineup / Index MB8508S064CE-100/-100L (Continued) Value Parameter Notes Symbol Condition Min. Unit Max. Std. ver. Low ver. ICC4 tCK = min, Burst Length = 4 Outputs Open, All Banks Active Gapless Data 0 V ≤ VIN ≤ VIL (max.) VIH (min.) ≤ VIN ≤ VCC — 480 mA ICC5 Auto Refresh tCK = min tRC = min 0 V ≤ VIN ≤ VIL (max.) VIH (min.) ≤ VIN ≤ VCC — 1360 mA ICC6 Self-Refresh tCK = min. CKE ≤ 0.2 V 0 V ≤ VIN ≤ VIL (max.) VIH (min.) ≤ VIN ≤ VCC — Input Leakage Current (All Inputs) II (L) 0 V ≤ VIN ≤ VCC All other pins not under test = 0 V –30 30 µA Output Leakage Current IO (L) 0 V ≤ VIN ≤ VCC Output is disabled (Hi-Z) –5 5 µA Burst Mode Current (Average Power Supply Current) Auto-refresh Current (Average Power Supply Current) Self-refresh Current (Average Power Supply Current) *3 *3 *3 8 4 mA LVTTL Output High Voltage *4 VOH IOH = –2.0 mA 2.4 — V LVTTL Output Low Voltage *4 VOL IOL = +2.0 mA — 0.4 V Notes: *1. An initial pause (DESL on NOP) of 200 µs is required after power-on followed by a minimum of eight Auto-refresh cycles. *2. DC characteristics is the Serial PD standby state (VIN = VSS or VCC). *3. ICC depends on the output termination, load conditions, clock cycle rate and signal clock rate. The specified values are obtained with the output open and no termination register. *4. Voltages referenced to VSS = VSSQ (= 0 V). 10 To Top / Lineup / Index MB8508S064CE-100/-100L ■ AC CHARACTERISTICS (1) BASE CHARACTERISTICS (At recommended operating conditions unless otherwise noted.) Notes 1, 2, 3 No. Parameter Notes Symbol MB8508S064CE -100/100L Min. Max. Unit CL = 3 tCK3 10 — ns CL = 2 tCK2 15 — ns Clock High Time tCH 3.5 — ns 3 Clock Low Time tCL 3.5 — ns 4 Input Setup Time tSI 3 — ns 5 Input Hold Time tHI 1 — ns 6 Output Valid from Clock (tCLK = min) CL = 3 tAC3 — 8.5 CL = 2 tAC2 — 9 7 Output in Low-Z *6 tLZ 0 — ns 8 Output in High-Z *6 CL = 3 tHZ3 3 8.5 ns CL = 2 tHZ2 3 9 ns 9 Output Hold Time *6 tOH 3 — ns 10 Time between Refresh tREF — 65.6 ms 11 Transition Time tT 0.5 2 ns 12 CKE Setup Time for Power Down Exit Time tCKSP 3 — ns 1 Clock Period 2 *4, *5 ns (2) BASE VALUES FOR CLOCK COUNT/LATENCY No. Parameter Notes Symbol MB8508S064CE -100/100L Unit Min. Max. tRC 90 — ns 1 RAS Cycle Time 2 RAS Precharge Time tRP 30 — ns 3 RAS Active Time tRAS 60 110000 ns 4 RAS to CAS Delay Time tRCD 30 — ns 5 Write Recovery Time tWR 10 — ns 6 RAS to RAS Bank Active Delay Time tRRD 20 — ns 7 Data-in to Precharge Lead Time tDPL 10 — ns 8 Data-in to Active/Refresh Command Period CL = 3 tDAL3 2 cyc + tRP — ns CL = 2 tDAL2 1 cyc + tRP — ns 9 Mode Register Set Cycle Time tRSC 20 — ns *7 *8 11 To Top / Lineup / Index MB8508S064CE-100/-100L (3) CLOCK COUNT FORMULA (*9) Clock ≥ Base Value Clock Period (Round off a whole number) (4) LATENCY (The latency values on these parameters are fixed regardless of clock period.) No. Parameter Symbol MB8508S064CE -100/100L Unit 1 CKE to Clock Disable ICKE 1 Cycle 2 DQM to Output in High-Z IDQZ 2 Cycle 3 DQM to Input Data Delay IDQD 0 Cycle 4 Last Output to Write Command Delay IOWD 2 Cycle 5 Write Command to Input Data Delay IDWD 0 Cycle 6 Precharge to Output in High-Z Delay CL = 3 IROH3 3 Cycle CL = 2 IROH2 2 Cycle 7 Burst Stop Command to Output in High-Z Delay CL = 3 IBSH3 3 Cycle CL = 2 IBSH2 2 Cycle 8 CAS to CAS Delay (min) ICCD 1 Cycle 9 CAS Bank Delay (min) ICBD 1 Cycle Notes: *1. An initial pause (DESL on NOP) of 200 µs is required after power-up followed by a minimum of eight Auto-refresh cycles. *2. 1.4 V or VREF is the reference level for measuring timing of signals. Transition times are measured between VIH (min) and VIL (max). *3. AC characteristics assume tT = 1 ns and 50 pF of capacitive load. *4. Maximum value of CL = 2 depends on tCK. *5. tAC also specifies the access time at burst mode except for first access. *6. Specified where output buffer is no longer driven. tOH, tLZ, and tHZ define the times at which the output level achieves ±200 mV. *7. Actual clock count of tRC (IRC) will be sum of clock count of tRAS (IRAS) and tRP (IRP). *8. Operation within the tRCD (min) ensures that access time is determined by tRCD (min) + tAC (max); if tRCD is greater than the specified tRCD (min), access time is determined by tAC. *9. All base values are measured from the clock edge at the command input to the clock edge for the next command input. All clock counts are calculated by a simple formula: clock count equals base value divided by clock period (round off to a whole number). *Source: See MB81F64842C Data Sheet for details on the electrical. 12 To Top / Lineup / Index MB8508S064CE-100/-100L ■ AC OPERATING TEST CONDITION (Example of AC Test Load Circuit) 1.4 V 50 Ω Z = 50 Ω I/O 50 pF 13 To Top / Lineup / Index MB8508S064CE-100/-100L ■ SERIAL PRESENCE DETECT(SPD) FUNCTION 1. PIN DESCRIPTIONS SCL (Serial Clock) SCL input is used to clock all data input/output of SPD SDA (Serial Data) SDA is a common pin used for all data input/output of SPD. The SDA pull-up resistor is required due to the open-drain output. SA0, SA1, SA2 (Address) Address inputs are used to set the least significant three bits of the eight bits slave address. The address inputs must be fixed to select a particular module and the fixed address of each module must be different each other. For this module, any address inputs are not required because all addresses (SA0, SA1, SA2) are driven to VSS on the module. 2. SPD OPERATIONS CLOCK and DATA CONVENTION Data states on the SDA can change only during SCL = Low. SDA state changes during SCL = High are indicated start and stop conditions. Refer to Fig. 1 below. START CONDITION All commands are preceded by a start condition, which is a transition of SDA state from High to Low when SCL = High. SPD will not respond to any command until this condition has been met. STOP CONDITION All read or write operation must be terminated by a stop condition, which is a transition of SDA state from Low to High when SCL = High. The stop condition is also used to make the SPD into the state of standby power mode after a read sequence. Fig. 1 – START AND STOP CONDITIONS SCL SDA START START = High to Low transition of SDA state when SCL is High STOP = Low to High transition of SDA state when SCL is High 14 STOP To Top / Lineup / Index MB8508S064CE-100/-100L ACKNOWLEDGE Acknowledge is a software convention used to indicate successful data transfer. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle the receiver will put the SDA line to Low in order to acknowledge that it received the eight bits of data. The SPD will respond with an acknowledge when it received the start condition followed by slave address issued by master. In the read operation, the SPD will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is issued by master, the SPD will continue to transmit data. If an acknowledge is not detected, the SPD will terminated further data transmissions. The master must then issue a stop condition to return the SPD to the standby power mode. In the write operation, upon receipt of eight bits of data the SPD will respond with an acknowledge, and await the next eight bits of data, again responding with an acknowledge until the stop condition is issued by master. SLAVE ADDRESS ADDRESSING Following a start condition, the master must output the eight bits slave address. The most significant four bits of the slave address are device type identifier. For the SPD this is fixed as 1010[B]. Refer to the Fig. 2 below. The next three significant bits are used to select a particular device. A system could have up to eight SPD devices —namely up to eight modules— on the bus. The eight addresses for eight SPD devices are defined by the state of the SA0, SA1 and SA2 inputs. For this module, the three bits are fixed as 000[B] because all addresses are driven to VSS on the module. Therefore, no address inputs are required. The last bit of the slave address defines the operation to be performed. When R/W bit is “1”, a read operation is selected, when R/W bit is “0”, a write operation is selected. Following the start condition, the SPD monitors the SDA line comparing the slave address being transmitted with its slave address (device type and state of SA0, SA1, and SA2 inputs). Upon a correct compare the SPD outputs an acknowledge on the SDA line. Depending on the state of the R/W bit, the SPD will execute a read or write operation. Fig. 2 – SLAVE ADDRESS DEVICE TYPE IDENTIFIER 1 0 1 DEVICE ADDRESS 0 SA2 SA1 SA0 R/W 15 To Top / Lineup / Index MB8508S064CE-100/-100L 3. READ OPERATIONS CURRENT ADDRESS READ Internally the SPD contains an address counter that maintains the address of the last data accessed, incremented by one. Therefore, if the last access (either a read or write operation) was to address(n), the next read operation would access data from address(n+1). Upon receipt of the slave address with the R/W bit = “1”, the SPD issues an acknowledge and transmits the eight bits of data during the next eight clock cycles. The master terminates this transmission by issuing a stop condition, omitting the ninth clock cycle acknowledge. Refer to Fig. 3 for the sequence of address, acknowledge and data transfer. Fig. 3 – CURRENT ADDRESS READ BUS ACTIVITY : MASTER S T A R T S T O P SLAVE ADDRESS SDA LINE A C K BUS ACTIVITY : SPD DATA RANDOM READ Random Read operations allow the master to access any memory location in a random manner. Prior to issuing the slave address with the R/W bit = “1”, the master must first perform a “dummy” write operation on the SPD. The master issues the start condition, and the slave address followed by the word address. After the word address acknowledge, the master immediately reissues the start condition and the slave address with the R/ W bit = “1”. This will be followed by an acknowledge from the SPD and then by the eight bits of data. The master terminates this transmission by issuing a stop condition, omitting the ninth clock cycle acknowledge. Refer to Fig. 4 for the sequence of address, acknowledge and data transfer. Fig. 4 – RANDOM READ BUS ACTIVITY : MASTER S T A R T SLAVE ADDRESS S T A R T WORD ADDRESS S T O P SLAVE ADDRESS SDA LINE BUS ACTIVITY : SPD 16 A C K A C K A C K DATA To Top / Lineup / Index MB8508S064CE-100/-100L SEQUENTIAL READ Sequential Read can be initiated as either a current address read or random read. The first data are transmitted as with the other read mode, however, the master now responds with an acknowledge, indicating it requires additional data. The SPD continues to output data for each acknowledge received. The master terminates this transmission by issuing a stop condition, omitting the ninth clock cycle acknowledge. Refer to Fig. 5 for the sequence of address, acknowledge and data transfer. The data output is sequential, with the data from address(n) followed by the data from address(n+1). The address counter for read operations increments all address bits, allowing the entire memory contents to be serially read during one operation. At the end of the address space (address 255), the counter “rolls over” to address0 and the SPD continues to output data for each acknowledge received. Fig. 5 – SEQUENTIAL READ SLAVE ADDRESS A C K BUS ACTIVITY : MASTER A C K S T O P A C K SDA LINE BUS ACTIVITY : SPD A C K DATA (n) DATA (n+1) DATA (n+2) DATA (n+x) 4. DC CHARACTERISTICS Parameter Symbol Condition Input Leakage Current SILI Output Leakage Current Output Low Voltage Note *1 Value Unit Min. Max. 0 V ≤ VIN ≤ VCC –10 10 µA SILO 0 V ≤ VOUT ≤ VCC –10 10 µA SVOL IOL = 3.0 mA — 0.4 V Note: *1. Referenced to VSS. 17 To Top / Lineup / Index MB8508S064CE-100/-100L 5. AC CHARACTERISTICS No. Parameter Value Symbol Unit Min. Max. fSCL — 100 KHz 1 SCL Clock Frequency 2 Noise Suppression Time Constant at SCL, SDA Inputs TI — 100 ns 3 SCL Low to SDA Data Out Valid tAA — 3.5 µs 4 Time the Bus Must Be Free Before a New Transmission Can Start tBUF 4.7 — µs 5 Start Condition Hold Time tHD:STA 4.0 — µs 6 Clock Low Period tLOW 4.7 — µs 7 Clock High Period tHIGH 4.0 — µs 8 Start Condition Setup Time tSU:STA 4.7 — µs 9 Data in Hold Time tHD:DAT 0 — µs 10 Data in Setup Time tSU:DAT 250 — ns 11 SDA and SCL Rise Time tR — 1 µs 12 SDA and SCL Fall Time tF — 300 ns 13 Stop Condition Setup Time tSU:STO 4.7 — µs 14 Data Out Hold Time tDH 100 — ns 15 Write Cycle Time tWR — 15 ms Fig. 6 – TIMING WAVEFORM tF tR tHIGH tLOW SCL tSU : STA tHD : DAT tSU : DAT tHD : STA SDA (input) tBUF tAA SDA (output) 18 tSU : STO tDH To Top / Lineup / Index MB8508S064CE-100/-100L ■ PACKAGE DIMENSION 144-pin plastic SO DIMM (socket type) (MDS-144P-P09) 3.80(.150)MAX 67.60±0.13(2.661±.005) 4.00±0.10 (.157±.004) Details of "A" part 31.75±0.13 (1.250±.005) "A" "B" 1 143 23.20±0.05 (.913±.002) 24.50(.965)TYP Pin No.1 INDEX 4.00(.157)MIN 29.00±0.10 (1.142±.004) 63.60±0.10(2.504±.004) 23.20±0.05 (.913±.002) 3.70±0.13 (.146±.005) 2.10±0.10 (.083±.004) 2 6.00±0.08 (.236±.003) NOTCHES FULL R 2.10±0.10 (.083±.004) C 0.80±0.03 (.031±.001) 32.80±0.05 (1.291±.002) 1997 FUJITSU LIMITED M144009SC-1-2 4.00±0.10 (.157±.004) 1.50±0.10 (.059±.004) 4.60±0.13 (.181±.005) 1.00±0.10 (.039±.004) 32.80±0.05 (1.291±.002) 4.60±0.13 (.181±.005) Details of "B" part 0.60±0.05 (.024±.002) 144 3.30±0.13 (.130±.005) 2.50±0.10 (.098±.004) NOTCHES FULL R 20.00±0.10 (.787±.004) Ø1.80±0.05 (Ø.071±.002) 0.25(.010)MAX 2.55(.100)MIN Dimension in mm (inches). 19 To Top / Lineup / Index MB8508S064CE-100/-100L FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-8588, Japan Tel: 81(44) 754-3763 Fax: 81(44) 754-3329 http://www.fujitsu.co.jp/ North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, USA Tel: (408) 922-9000 Fax: (408) 922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: (800) 866-8608 Fax: (408) 922-9179 http://www.fujitsumicro.com/ Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 D-63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. http://www.fujitsu-ede.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220 http://www.fmap.com.sg/ F9812 FUJITSU LIMITED Printed in Japan 20 Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.