MICRON MT18LD472AG-6

OBSOLETE
2, 4 MEG x 72
NONBUFFERED DRAM DIMMs
MT9LD272A(X), MT18LD472A(X)
DRAM
MODULE
For the latest data sheet revisions, please refer to the Micron
Web site: www.micron.com/mti/msp/html/datasheet.html
FEATURES
PIN ASSIGNMENT (Front View)
• JEDEC-standard, eight-CAS#, ECC pinout in a 168-pin,
dual in-line memory module (DIMM)
• 16MB (2 Meg x 72) and 32MB (4 Meg x 72)
• Nonbuffered
• High-performance CMOS silicon-gate process
• Single +3.3V ±0.3V power supply
• All inputs, outputs and clocks are TTL-compatible
• Refresh modes: RAS#-ONLY, CAS#-BEFORE-RAS#
(CBR) and HIDDEN
• 2,048-cycle refresh distributed across 32ms
• FAST-PAGE-MODE (FPM) or Extended Data-Out
(EDO) PAGE MODE access cycles
• Serial presence-detect (SPD)
OPTIONS
168-Pin DIMM
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
MARKING
• Package
168-pin DIMM (gold)
G
• Timing
50ns access
60ns access
-5*
-6
• Access Cycles
FAST PAGE MODE
EDO PAGE MODE
None
X
*EDO version only
KEY TIMING PARAMETERS
EDO Operating Mode
SPEED
-5
-6
tRC
tRAC
tPC
tAA
tCAC
tCAS
84ns
104ns
50ns
60ns
20ns
25ns
25ns
30ns
13ns
15ns
8ns
10ns
FPM Operating Mode
SPEED
-6
tRC
tRAC
tPC
tAA
tCAC
tRP
110ns
60ns
35ns
30ns
15ns
40ns
NOTE: Pin symbols in parentheses are not used on these modules but may be used
for other modules in this product family. They are for reference only.
2, 4 Meg x 72 Nonbuffered DRAM DIMMs
DM60.p65 – Rev. 6/98
1
SYMBOL
VSS
DQ0
DQ1
DQ2
DQ3
VDD
DQ4
DQ5
DQ6
DQ7
DQ8
VSS
DQ9
DQ10
DQ11
DQ12
DQ13
VDD
DQ14
DQ15
CB0
CB1
VSS
NC
NC
VDD
WE0#
CAS0#
CAS1#
RAS0#
OE0#
VSS
A0
A2
A4
A6
A8
A10
NC (A12)
VDD
VDD
RFU
PIN
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
SYMBOL
VSS
OE2#
RAS2#
CAS2#
CAS3#
WE2#
VDD
NC
NC
CB2
CB3
VSS
DQ16
DQ17
DQ18
DQ19
VDD
DQ20
NC
RFU
NC
VSS
DQ21
DQ22
DQ23
VSS
DQ24
DQ25
DQ26
DQ27
VDD
DQ28
DQ29
DQ30
DQ31
VSS
NC
NC
NC
SDA
SCL
VDD
PIN
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
SYMBOL
VSS
DQ32
DQ33
DQ34
DQ35
VDD
DQ36
DQ37
DQ38
DQ39
DQ40
VSS
DQ41
DQ42
DQ43
DQ44
DQ45
VDD
DQ46
DQ47
CB4
CB5
VSS
NC
NC
VDD
RFU
CAS4#
CAS5#
NC
RFU
VSS
A1
A3
A5
A7
A9
NC (A11)
NC (A13)
VDD
RFU
RFU
PIN SYMBOL
127
VSS
128
RFU
129 NC/RAS3#*
130
CAS6#
131
CAS7#
132
RFU
133
VDD
134
NC
135
NC
136
CB6
137
CB7
138
VSS
139
DQ48
140
DQ49
141
DQ50
142
DQ51
143
VDD
144
DQ52
145
NC
146
RFU
147
NC
148
VSS
149
DQ53
150
DQ54
151
DQ55
152
VSS
153
DQ56
154
DQ57
155
DQ58
156
DQ59
157
VDD
158
DQ60
159
DQ61
160
DQ62
161
DQ63
162
VSS
163
NC
164
NC
165
SA0
166
SA1
167
SA2
168
VDD
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1998, Micron Technology, Inc.
OBSOLETE
2, 4 MEG x 72
NONBUFFERED DRAM DIMMs
PART NUMBERS
EDO PAGE MODE
EDO Operating Mode
EDO PAGE MODE, designated by the “X” version, is an
accelerated FAST-PAGE-MODE cycle. The primary advantage of EDO is the availability of data-out even after CAS#
goes back HIGH. EDO provides for CAS# precharge time
(tCP) to occur without the output data going invalid. This
elimination of CAS# output control provides for pipelined
READs.
FAST-PAGE-MODE modules have traditionally turned
the output buffers off (High-Z) with the rising edge of
CAS#. EDO-PAGE-MODE DRAMs operate like FASTPAGE-MODE DRAMs, except data will remain valid or
become valid after CAS# goes HIGH during READs, provided RAS# and OE# are held LOW. If OE# is pulsed while
RAS# and CAS# are LOW, data will toggle from valid data
to High-Z and back to the same valid data. If OE# is toggled
or pulsed after CAS# goes HIGH while RAS# remains
LOW, data will transition to and remain High-Z.
During an application, if the DQ outputs are wire OR’d,
OE# must be used to disable idle banks of DRAMs. Alternatively, pulsing WE# to the idle banks during CAS# HIGH
time will also High-Z the outputs. Independent of OE#
control, the outputs will disable after tOFF, which is referenced from the rising edge of RAS# or CAS#, whichever
occurs last. (Refer to the 4 Meg x 4 [MT4LC4M4E8] DRAM
data sheet for additional information on EDO functionality.)
PART NUMBER
MT9LD272AG-5 X
MT9LD272AG-6 X
MT18LD472AG-5 X
MT18LD472AG-6 X
CONFIGURATION
2 Meg x 72 ECC
2 Meg x 72 ECC
4 Meg x 72 ECC
4 Meg x 72 ECC
SPEED
50ns
60ns
50ns
60ns
CONFIGURATION
2 Meg x 72 ECC
4 Meg x 72 ECC
SPEED
60ns
60ns
FPM Operating Mode
PART NUMBER
MT9LD272AG-6
MT18LD472AG-6
GENERAL DESCRIPTION
The MT9LD272A(X) and MT18LD472A(X) are randomly
accessed 16MB and 32MB memories organized in a x72
configuration. They are specially processed to operate from
3V to 3.6V for low-voltage memory systems.
During READ or WRITE cycles, each bit is uniquely
addressed through the 21/22 address bits, which are entered 11 bits (A0 -A10) at RAS# time and 10/11 bits (A0A10) at CAS# time.
READ and WRITE cycles are selected with the WE#
input. A logic HIGH on WE# dictates read mode, while a
logic LOW on WE# dictates write mode. During a WRITE
cycle, data-in (D) is latched by the falling edge of WE# or
CAS#, whichever occurs last. An EARLY WRITE occurs
when WE# is taken LOW prior to CAS# falling. A LATE
WRITE or READ-MODIFY-WRITE occurs when WE# falls
after CAS# was taken LOW. During EARLY WRITE cycles,
the data-outputs (Q) will remain High-Z regardless of the
state of OE#. During LATE WRITE or READ-MODIFYWRITE cycles, OE# must be taken HIGH to disable the dataoutputs prior to applying input data. If a LATE WRITE or
READ-MODIFY-WRITE is attempted while keeping OE#
LOW, no WRITE will occur, and the data-outputs will drive
read data from the accessed location.
Returning RAS# and CAS# HIGH terminates a memory
cycle and decreases chip current to a reduced standby level.
Also, the chip is preconditioned for the next cycle during
the RAS# HIGH time. Correct memory cell data is preserved by maintaining power and executing any RAS#
cycle (READ, WRITE) or RAS# REFRESH cycle (RAS#ONLY, CBR or HIDDEN) so that all combinations of RAS#
addresses (A0-A9/A10) are executed at least every tREF,
regardless of sequence. The CBR REFRESH cycle will invoke the internal refresh counter for automatic RAS# addressing.
FAST PAGE MODE
SERIAL PRESENCE-DETECT OPERATION
FAST-PAGE-MODE operations allow faster data operations (READ or WRITE) within a row-address-defined
page boundary. The FAST-PAGE-MODE cycle is always
initiated with a row address strobed in by RAS#, followed
by a column address strobed in by CAS#. Additional columns may be accessed by providing valid column
addresses, strobing CAS# and holding RAS# LOW , thus
executing faster memory cycles. Returning RAS# HIGH
terminates the FAST-PAGE-MODE operation.
This module family incorporates serial presence-detect
(SPD). The SPD function is implemented using a 2,048-bit
EEPROM. This nonvolatile storage device contains 256
bytes. The first 128 bytes can be programmed by Micron to
identify the module type and various DRAM organizations
and timing parameters. The remaining 128 bytes of storage
are available for use by the customer. System READ/
WRITE operations between the master (system logic) and
the slave EEPROM device (DIMM) occur via a standard IIC
bus using the DIMM’s SCL (clock) and SDA (data) signals,
2, 4 Meg x 72 Nonbuffered DRAM DIMMs
DM60.p65 – Rev. 6/98
REFRESH
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1998, Micron Technology, Inc.
OBSOLETE
2, 4 MEG x 72
NONBUFFERED DRAM DIMMs
together with SA(2:0), which provide eight unique DIMM/
EEPROM addresses.
SPD ACKNOWLEDGE
Acknowledge is a software convention used to indicate
successful data transfers. The transmitting device, either
master or slave, will release the bus after transmitting eight
bits. During the ninth clock cycle, the receiver will pull the
SDA line LOW to acknowledge that it received the eight bits
of data (Figure 3).
The SPD device will always respond with an acknowledge after recognition of a start condition and its slave
address. If both the device and a write operation have been
selected, the SPD device will respond with an acknowledge
after the receipt of each subsequent eight-bit word. In the
read mode the SPD device will transmit eight bits of data,
release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition
is generated by the master, the slave will continue to transmit data. If an acknowledge is not detected, the slave will
terminate further data transmissions and await the stop
condition to return to standby power mode.
SPD CLOCK AND DATA CONVENTIONS
Data states on the SDA line can change only during SCL
LOW. SDA state changes during SCL HIGH are reserved
for indicating start and stop conditions (Figures 1 and 2).
SPD START CONDITION
All commands are preceded by the start condition, which
is a HIGH-to-LOW transition of SDA when SCL is HIGH.
The SPD device continuously monitors the SDA and SCL
lines for the start condition and will not respond to any
command until this condition has been met.
SPD STOP CONDITION
All communications are terminated by a stop condition,
which is a LOW-to-HIGH transition of SDA when SCL is
HIGH. The stop condition is also used to place the SPD
device into standby power mode.
SCL
SCL
SDA
SDA
DATA STABLE
DATA
CHANGE
START
BIT
DATA STABLE
STOP
BIT
Figure 2
DEFINITION OF START AND STOP
Figure 1
DATA VALIDITY
SCL from Master
8
9
Data Output
from Transmitter
Data Output
from Receiver
Acknowledge
Figure 3
ACKNOWLEDGE RESPONSE FROM RECEIVER
2, 4 Meg x 72 Nonbuffered DRAM DIMMs
DM60.p65 – Rev. 6/98
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1998, Micron Technology, Inc.
OBSOLETE
2, 4 MEG x 72
NONBUFFERED DRAM DIMMs
FUNCTIONAL BLOCK DIAGRAM
MT9LD272A(X) (16MB)
DQ0-DQ7
DQ8-DQ15
CB0-CB7
DQ0-DQ7
WE0#
WE#
OE0#
OE#
RAS0#
RAS#
CAS0#
CAS#
DQ0-DQ7
WE#
U1
WE#
U2
OE#
RAS#
CAS1#
CAS#
CAS#
U4
CAS#
U5
OE#
RAS#
A0–A10
DQ0-DQ7
WE#
OE#
RAS#
A0–A10
DQ24-DQ31
DQ0-DQ7
WE#
U3
OE#
A0–A10
DQ16-DQ23
RAS#
A0–A10
11
11
11
11
DQ32-DQ39
DQ40-DQ41
DQ48-DQ55
DQ56-DQ63
CAS#
CAS2#
A0–A10
11
CAS3#
A0-A10
DQ0-DQ7
WE2#
WE#
OE2#
OE#
DQ0-DQ7
U6
RAS2#
RAS#
CAS4#
CAS#
DQ0-DQ7
WE#
WE#
U7
U8
OE#
OE#
RAS#
A0–A10
CAS#
DQ0-DQ7
WE#
RAS#
A0–A10
CAS#
U9
OE#
RAS#
A0–A10
CAS#
A0–A10
CAS5#
11
CAS6#
11
11
11
CAS7#
SPD
SCL
A0
A1
A2
SDA
VDD
U1-U9
VSS
U1-U9
U1-U9 = MT4LC2M8B1 FAST PAGE MODE
U1-U9 = MT4LC2M8E7 EDO PAGE MODE
SA0 SA1 SA2
2, 4 Meg x 72 Nonbuffered DRAM DIMMs
DM60.p65 – Rev. 6/98
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1998, Micron Technology, Inc.
OBSOLETE
2, 4 MEG x 72
NONBUFFERED DRAM DIMMs
FUNCTIONAL BLOCK DIAGRAM
MT18LD472A(X) (32MB)
DQ0-DQ3
DQ4-DQ7
DQ0-DQ3
WE0#
WE#
OE0#
OE#
DQ0-DQ3
WE#
U1
DQ8-DQ11
DQ0-DQ3
WE#
U2
OE#
DQ12-DQ15
CB4-CB7
DQ0-DQ3
DQ0-DQ3
WE#
U3
OE#
WE#
U4
OE#
DQ16-DQ19
DQ0-DQ3
WE#
U5
OE#
DQ20-DQ23
DQ0-DQ3
WE#
U6
OE#
DQ24-DQ27
DQ0-DQ3
WE#
U7
OE#
DQ28-DQ31
DQ0-DQ3
WE#
U8
OE#
U9
OE#
RAS0#
RAS#
RAS#
RAS#
RAS#
RAS#
RAS#
RAS#
RAS#
RAS#
CAS0#
CAS# A0–A10
CAS# A0–A10
CAS# A0–A10
CAS# A0–A10
CAS# A0–A10
CAS# A0–A10
CAS# A0–A10
CAS# A0–A10
CAS# A0–A10
11
11
11
11
11
11
11
11
11
DQ32-DQ35
DQ36-DQ39
DQ40-DQ43
DQ44-DQ47
CB4-CB7
DQ48-DQ51
DQ52-DQ55
DQ56-DQ59
DQ06-DQ63
CAS1#
CAS2#
CAS3#
A0-A10
DQ0-DQ3
WE2#
WE#
OE2#
OE#
DQ0-DQ3
WE#
U10
DQ0-DQ3
WE#
U11
OE#
DQ0-DQ3
DQ0-DQ3
WE#
U12
OE#
WE#
U13
OE#
DQ0-DQ3
WE#
U14
OE#
DQ0-DQ3
WE#
U15
OE#
DQ0-DQ3
WE#
U16
OE#
DQ0-DQ3
WE#
U17
OE#
U18
OE#
RAS2#
RAS#
RAS#
RAS#
RAS#
RAS#
RAS#
RAS#
RAS#
RAS#
CAS4#
CAS# A0–A10
CAS# A0–A10
CAS# A0–A10
CAS# A0–A10
CAS# A0–A10
CAS# A0–A10
CAS# A0–A10
CAS# A0–A10
CAS# A0–A10
11
11
11
11
11
11
11
11
11
CAS5#
CAS6#
CAS7#
SPD
U1-U18 = MT4LC4M4B1 FAST PAGE MODE
SCL
SDA
A0
A1
A2
SA0
SA1
SA2
2, 4 Meg x 72 Nonbuffered DRAM DIMMs
DM60.p65 – Rev. 6/98
VDD
U1-U18
VSS
U1-U18
U1-U18 = MT4LC4M4E8 EDO PAGE MODE
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1998, Micron Technology, Inc.
OBSOLETE
2, 4 MEG x 72
NONBUFFERED DRAM DIMMs
PIN DESCRIPTIONS
PIN NUMBERS
30, 45
SYMBOL
RAS0#, RAS2#
TYPE
Input
28, 29, 46, 47, 112,
113, 130, 131
CAS0#-CAS7#
Input
27, 48
WE0#, WE2#
Input
31, 44
OE0#, OE2#
Input
33-38, 117-121
A0-A10
Input
2-5, 7-11, 13-17, 19-20,
55-58, 60, 65-67, 69-72,
74-77, 86-89,91-95,
97-101, 103-104,
139-142, 144, 149-151,
153-156, 158-161
21-22, 52-53, 105-106,
136-137
42, 62, 111, 115,
125-126, 128, 132, 146
6, 18, 26, 40, 41, 49, 59,
73, 84, 90, 102, 110,
124, 133, 143, 157, 168
1, 12, 23, 32, 43, 54, 64,
68, 78, 85, 96, 107, 116,
127, 138, 148, 152, 162
DQ0-DQ63
Input/
Output
CB0-CB7
Input/Output
RFU
–
VDD
Supply
Reserved for Future Use: These pins should be left
unconnected.
Power Supply: +3.3V ±0.3V.
VSS
Supply
Ground.
82
SDA
Input/Output
83
SCL
Input
Serial Clock for Presence-Detect. SCL is used to
synchronize the presence-detect data transfer to and
from the module.
165-167
SA0-SA2
Input
Presence-Detect Address Inputs. These pins are used to
configure the presence-detect device.
2, 4 Meg x 72 Nonbuffered DRAM DIMMs
DM60.p65 – Rev. 6/98
DESCRIPTION
Row-Address Strobe: RAS# is used to clock-in the rowaddress bits. Two RAS# inputs allow for one x72 bank or
two x36 banks.
Column-Address Strobe: CAS# is used to clock-in the
column-address bits, enable the DRAM output buffers
and strobe the data inputs on WRITE cycles. Eight CAS#
inputs allow byte access control for any memory bank
configuration.
Write Enable: WE# is the READ/WRITE control for the
DQ pins. If WE# is LOW prior to CAS# going LOW, the
access is an EARLY WRITE cycle. If WE# is HIGH while
CAS# is LOW, the access is a READ cycle, provided OE#
is also LOW. If WE# goes LOW after CAS# goes LOW,
then the cycle is a LATE WRITE cycle. A LATE WRITE
cycle is generally used in conjunction with a READ cycle
to form a READ-MODIFY-WRITE cycle.
Output Enable: OE# is the input/output control for the DQ
pins. These signals may be driven, allowing LATE WRITE
cycles.
Address Inputs: These inputs are multiplexed and clocked
by RAS# and CAS#.
Data I/O: For WRITE cycles, DQ0-DQ63 act as inputs to
the addressed DRAM location. For READ access cycles,
DQ0-DQ63 act as outputs for the addressed DRAM
location.
Check Bits.
Serial Presence-Detect Data. SDA is a bidirectional pin
used to transfer addresses and data into and data out of
the presence-detect portion of the module.
6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1998, Micron Technology, Inc.
OBSOLETE
2, 4 MEG x 72
NONBUFFERED DRAM DIMMs
SERIAL PRESENCE-DETECT MATRIX
BYTE
0
1
2
DESCRIPTION
NUMBER OF BYTES USED BY MICRON
TOTAL NUMBER OF SPD MEMORY BYTES
MEMORY TYPE
ENTRY (VERSION)
128
256
FAST PAGE MODE
EDO PAGE MODE
BIT7
1
0
0
0
BIT6
0
0
0
0
BIT5
0
0
0
0
BIT4
0
0
0
0
BIT3
0
1
0
0
BIT2
0
0
0
0
BIT1
0
0
0
1
BIT0
0
0
1
0
HEX
80
08
01
02
3
4
NUMBER OF ROW ADDRESSES
NUMBER OF COLUMN ADDRESSES
11
10 (16MB)
11 (32MB)
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
1
1
1
1
0
1
0B
0A
0B
5
6
7
8
9
NUMBER OF BANKS
DATA WIDTH
DATA WIDTH (continued)
VOLTAGE INTERFACE
RAS# ACCESS TIME (tRAC)
1
x72
NONE
LVTTL
50ns (-5)
60ns (-6)
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
0
1
0
1
0
0
1
0
0
01
48
00
01
32
3C
10
CAS# ACCESS TIME (tCAC)
13ns (-5)
15ns (-6)
0
0
0
0
0
0
0
0
1
1
1
1
0
1
1
1
0D
0F
11
12
13
MODULE CONFIGURATION TYPE
REFRESH RATES
DRAM WIDTH (PRIMARY DRAM)
ECC
15.625µs/NORMAL
x8 (16MB)
x4 (32MB)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
0
0
0
0
0
0
0
02
00
08
04
14
ERROR CHECKING DRAM DATA WIDTH
x8 (16MB)
x4 (32MB)
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
x
0
0
0
0
0
x
x
x
–
0
0
0
0
0
1
1
0
0
0
0
1
0
0
0
0
x
0
0
0
0
0
x
x
x
–
0
0
0
0
1
0
0
1
1
1
1
1
0
0
0
0
x
0
0
0
0
0
x
x
x
–
0
0
0
0
1
0
0
1
1
1
0
1
0
0
0
0
x
0
0
0
0
0
x
x
x
–
1
0
0
0
1
0
0
0
1
1
1
1
0
0
0
0
x
0
0
0
0
0
x
x
x
–
0
1
0
0
0
1
1
0
1
1
1
1
0
0
0
1
x
0
0
0
1
0
x
x
x
–
0
0
0
0
1
1
0
1
1
1
0
1
0
1
1
0
x
0
1
1
0
0
x
x
x
–
0
0
0
0
0
0
1
1
1
0
0
1
1
0
1
0
x
1
0
1
0
0
x
x
x
–
08
04
00
00
3A
46
45
33
3F
3E
2C
FF
01
02
03
04
xx
01
02
03
04
00
xx
xx
xx
–
15-61
62
63
RESERVED
SPD REVISION
CHECKSUM FOR BYTES 0-62
64
65-71
72
MANUFACTURER’S JEDEC ID CODE
MANUFACTURER’S JEDEC CODE (CONT.)
MANUFACTURING LOCATION
73-90
91
MODULE PART NUMBER (ASCII)
PCB IDENTIFICATION CODE
92
93
94
95-98
99-125
IDENTIFICATION CODE (CONT.)
YEAR OF MANUFACTURE IN BCD
WEEK OF MANUFACTURE IN BCD
MODULE SERIAL NUMBER
MANUFACTURE SPECIFIC DATA (RSVD)
NOTE:
REV. 0
16MB -5 (EDO)
16MB -6 (EDO)
16MB -6 (FPM)
32MB -5 (EDO)
32MB -6 (EDO)
32MB -6 (FPM)
MICRON
1
2
3
4
0
1. “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW.”
2. x = Variable Data.
2, 4 Meg x 72 Nonbuffered DRAM DIMMs
DM60.p65 – Rev. 6/98
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1998, Micron Technology, Inc.
OBSOLETE
2, 4 MEG x 72
NONBUFFERED DRAM DIMMs
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only, and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
ABSOLUTE MAXIMUM RATINGS*
Voltage on VDD Pin Relative to VSS ................. -1V to +4.6V
Voltage on Inputs or I/O Pins
Relative to VSS ................................................ -1V to +4.6V
Operating Temperature, TA (ambient) .......... 0°C to +70°C
Storage Temperature (plastic) .................... -55°C to +125°C
Power Dissipation ............................................................. 9W
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(Notes: 1) (VDD = +3.3V ±0.3V)
PARAMETER/CONDITION
SYMBOL
SIZE
MIN
MAX
UNITS
SUPPLY VOLTAGE
VDD
ALL
3
3.6
V
INPUT HIGH VOLTAGE: Logic 1; All inputs
VIH
ALL
2
VDD + 0.3
V
30
30
INPUT LOW VOLTAGE: Logic 0; All inputs
INPUT LEAKAGE CURRENT:
Any input 0V ≤ VIN ≤ VDD + 0.3V
(All other pins not under test = 0V)
OUTPUT LEAKAGE CURRENT:
DQ is disabled; 0V ≤ VOUT ≤ VDD + 0.3V
VIL
ALL
-0.5
0.8
V
CAS0#-CAS7#
II1
II2
WE0#, WE2#,
OE0#, OE2#
RAS0#-RAS3#
II3
-4
-6
-18
-36
-10
-18
-10
-18
4
6
18
36
10
18
10
18
µA
A0-A10
16MB
32MB
16MB
32MB
16MB
32MB
16MB
32MB
IOZ
16MB
32MB
-5
-5
5
5
µA
VOH
ALL
2.4
–
V
VOL
ALL
–
0.4
V
DQ0-DQ63,
CB0-CB7
OUTPUT LEVELS:
Output High Voltage (IOUT = -2mA)
Output Low Voltage (IOUT = 2mA)
2, 4 Meg x 72 Nonbuffered DRAM DIMMs
DM60.p65 – Rev. 6/98
8
II4
NOTES
µA
µA
µA
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1998, Micron Technology, Inc.
OBSOLETE
2, 4 MEG x 72
NONBUFFERED DRAM DIMMs
ICC OPERATING CONDITIONS AND MAXIMUM LIMITS
(Notes: 1, 5, 6) (VDD = +3.3V ±0.3V)
MAX
PARAMETER/CONDITION
SYMBOL
SIZE
-5*
-6
UNITS
STANDBY CURRENT: TTL
(RAS# = CAS# = VIH)
ICC1
16MB
32MB
9
18
9
18
mA
STANDBY CURRENT: CMOS
(RAS# = CAS# = VDD - 0.2V)
ICC2
16MB
32MB
9
9
9
9
mA
OPERATING CURRENT: Random READ/WRITE
Average power supply current
(RAS#, CAS#, address cycling: tRC = tRC [MIN])
ICC3
16MB
32MB
990
1,980
900
1,800
mA
3, 24
OPERATING CURRENT: FAST PAGE MODE
Average power supply current
(RAS# = VIL, CAS#, address cycling: tPC = tPC [MIN])
ICC4
16MB
32MB
–
–
720
1,440
mA
3, 24
ICC5
(X only)
16MB
32MB
990
1,980
900
1,800
mA
3, 24
REFRESH CURRENT: RAS#-ONLY
Average power supply current
(RAS# cycling, CAS# = VIH: tRC = tRC [MIN])
ICC6
16MB
32MB
990
1,980
900
1,800
mA
3, 24
REFRESH CURRENT: CBR
Average power supply current
(RAS#, CAS#, address cycling: tRC = tRC [MIN])
ICC7
16MB
32MB
990
1,980
900
1,800
mA
3, 4
OPERATING CURRENT: EDO PAGE MODE (“X” version only)
Average power supply current
(RAS# = VIL, CAS#, address cycling: tPC = tPC [MIN])
NOTES
* EDO version only
2, 4 Meg x 72 Nonbuffered DRAM DIMMs
DM60.p65 – Rev. 6/98
9
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1998, Micron Technology, Inc.
OBSOLETE
2, 4 MEG x 72
NONBUFFERED DRAM DIMMs
CAPACITANCE
PARAMETER
SYMBOL
MAX
16MB 32MB
UNITS
NOTES
Input Capacitance: A0-A10
CI1
51
96
pF
2
Input Capacitance: WE0#, WE2#, OE0#, OE2#
CI2
39
67
pF
2
Input Capacitance: RAS0#, RAS2#
CI3
39
67
pF
2
Input Capacitance: CAS0#-CAS7#
CI4
17
24
pF
2
Input Capacitance: SCL, SA0-SA2
CI5
6
6
pF
2
Input/Output Capacitance: DQ0-DQ63, CB0-CB7, SDA
CIO
10
10
pF
2
FAST PAGE MODE
AC ELECTRICAL CHARACTERISTICS
(Notes: 5, 6, 7, 8, 9, 12, 29) (VDD = +3.3V ±0.3V)
AC CHARACTERISTICS - FAST PAGE MODE OPTION
PARAMETER
Access time from column address
Column-address hold time (referenced to RAS#)
Column-address setup time
Row-address setup time
Column address to WE# delay time
Access time from CAS#
Column-address hold time
CAS# pulse width
CAS# hold time (CBR Refresh)
CAS# to output in Low-Z
CAS# precharge time
Access time from CAS# precharge
CAS# to RAS# precharge time
CAS# hold time
CAS# setup time (CBR Refresh)
CAS# to WE# delay time
WRITE command to CAS# lead time
Data-in hold time
Data-in setup time
Output disable
Output enable
OE# hold time from WE# during READ-MODIFY-WRITE cycle
Output buffer turn-off delay
OE# setup prior to RAS# during HIDDEN REFRESH cycle
FAST-PAGE-MODE READ or WRITE cycle time
2, 4 Meg x 72 Nonbuffered DRAM DIMMs
DM60.p65 – Rev. 6/98
-6
SYMBOL
tAA
tAR
tASC
tASR
tAWD
tCAC
tCAH
tCAS
tCHR
tCLZ
tCP
tCPA
tCRP
tCSH
tCSR
tCWD
tCWL
tDH
tDS
tOD
tOE
tOEH
tOFF
tORD
tPC
10
MIN
MAX
30
45
0
0
55
15
10
15
10
3
10
10,000
35
5
60
5
40
15
10
0
3
15
3
0
35
15
15
15
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
23
14
4
25
15
4
23
22
22
21
19, 25, 26
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1998, Micron Technology, Inc.
OBSOLETE
2, 4 MEG x 72
NONBUFFERED DRAM DIMMs
FAST PAGE MODE
AC ELECTRICAL CHARACTERISTICS
(Notes: 5, 6, 7, 8, 9, 12, 29) (VDD = +3.3V ±0.3V)
AC CHARACTERISTICS - FAST PAGE MODE OPTION
PARAMETER
FAST-PAGE-MODE READ-WRITE cycle time
Access time from RAS#
RAS# to column-address delay time
Row-address hold time
RAS# pulse width
RAS# pulse width (FAST PAGE MODE)
Random READ or WRITE cycle time
RAS# to CAS# delay time
READ command hold time (referenced to CAS#)
READ command setup time
Refresh period (2,048 cycles)
RAS# precharge time
RAS# to CAS# precharge time
READ command hold time (referenced to RAS#)
RAS# hold time
READ-WRITE cycle time
RAS# to WE# delay time
WRITE command to RAS# lead time
Transition time (rise or fall)
WRITE command hold time
WRITE command hold time (referenced to RAS#)
WE# command setup time
WRITE command pulse width
WE# hold time (CBR Refresh)
WE# setup time (CBR Refresh)
2, 4 Meg x 72 Nonbuffered DRAM DIMMs
DM60.p65 – Rev. 6/98
-6
SYMBOL
tPRWC
tRAC
tRAD
tRAH
tRAS
tRASP
tRC
tRCD
tRCH
tRCS
tREF
tRP
tRPC
tRRH
tRSH
tRWC
tRWD
tRWL
tT
tWCH
tWCR
tWCS
tWP
tWRH
tWRP
11
MIN
85
MAX
60
15
10
60
60
110
20
0
0
10,000
125,000
32
40
0
0
15
155
85
15
2
10
45
0
10
10
10
50
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
13
17
16
18
18
23
23
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1998, Micron Technology, Inc.
OBSOLETE
2, 4 MEG x 72
NONBUFFERED DRAM DIMMs
EDO PAGE MODE
AC ELECTRICAL CHARACTERISTICS
(Notes: 5, 6, 7, 8, 9, 12, 29) (VDD = +3.3V ±0.3V)
AC CHARACTERISTICS - EDO PAGE MODE OPTION
PARAMETER
Access time from column address
Column-address setup to CAS# precharge
Column-address hold time (referenced to RAS#)
Column-address setup time
Row-address setup time
Column-address to WE# delay time
Access time from CAS#
Column-address hold time
CAS# pulse width
CAS# hold time (CBR Refresh)
CAS# to output in Low-Z
Data output hold after CAS# LOW
CAS# precharge time
Access time from CAS# precharge
CAS# to RAS# precharge time
CAS# hold time
CAS# setup time (CBR Refresh)
CAS# to WE# delay time
WRITE command to CAS# lead time
Data-in hold time
Data-in setup time
Output disable
Output enable
OE# hold time from WE# during
READ-MODIFY-WRITE cycle
OE# HIGH hold time from CAS# HIGH
OE# HIGH pulse width
OE# LOW to CAS# HIGH setup time
Output buffer turn-off delay
OE# setup prior to RAS#
during HIDDEN REFRESH cycle
EDO-PAGE-MODE READ or WRITE cycle time
EDO-PAGE-MODE READ-WRITE cycle time
Access time from RAS#
RAS# to column-address delay time
Row-address hold time
RAS# pulse width
RAS# pulse width (EDO PAGE MODE)
Random READ or WRITE cycle time
RAS# to CAS# delay time
READ command hold time (referenced to CAS#)
READ command setup time
Refresh period (2,048 cycles)
RAS# precharge time
2, 4 Meg x 72 Nonbuffered DRAM DIMMs
DM60.p65 – Rev. 6/98
-5
SYMBOL
tAA
tACH
tAR
tASC
tASR
tAWD
tCAC
tCAH
tCAS
tCHR
tCLZ
tCOH
tCP
tCPA
tCRP
tCSH
tCSR
tCWD
tCWL
tDH
tDS
tOD
tOE
tOEH
MIN
8
tOEHC
5
5
4
0
0
tOEP
tOES
tOFF
tORD
tPC
-6
MAX
25
12
38
0
0
42
NOTES
10/12*
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
5
5
0
0
ns
ns
ns
ns
ns
21
13
8
8
8
0
3
8
10,000
15
10
10
10
0
3
10
28
5
38
5
28
8
8
0
0
tRAC
12
12
12
9
9
50
50
84
11
0
0
tRAH
tRAS
tRASP
tRC
tRCD
tRCH
tRCS
tREF
5
45
5
35
10
10
0
0
30
12
15
15
15
25
56
10,000
125,000
60
12
10
60
60
104
14
0
0
32
tRP
10,000
35
50
tRAD
MAX
30
15
45
0
0
49
20
47
tPRWC
MIN
10,000
125,000
32
40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
23
14
4
15
4
23
22
22
21
19, 26
13
17
16
18
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1998, Micron Technology, Inc.
OBSOLETE
2, 4 MEG x 72
NONBUFFERED DRAM DIMMs
EDO PAGE MODE
AC ELECTRICAL CHARACTERISTICS
(Notes: 5, 6, 7, 8, 9, 12, 29) (VDD = +3.3V ±0.3V)
AC CHARACTERISTICS - EDO PAGE MODE OPTION
PARAMETER
RAS# to CAS# precharge time
READ command hold time (referenced to RAS#)
RAS# hold time
READ WRITE cycle time
RAS# to WE# delay time
WRITE command to RAS# lead time
Transition time (rise or fall)
WRITE command hold time
WRITE command hold time (referenced to RAS#)
WE# command setup time
Output disable delay from WE# (CAS# HIGH)
WRITE command pulse width
WE# pulse to disable at CAS# HIGH
WE# hold time (CBR Refresh)
WE# setup time (CBR Refresh)
2, 4 Meg x 72 Nonbuffered DRAM DIMMs
DM60.p65 – Rev. 6/98
-5
SYMBOL
tRPC
tRRH
tRSH
tRWC
tRWD
tRWL
tT
tWCH
tWCR
tWCS
tWHZ
tWP
tWPZ
tWRH
tWRP
13
MIN
5
0
13
116
67
13
2
8
38
0
0
5
10
8
8
-6
MAX
50
12
MIN
5
0
15
140
79
15
2
10
45
0
0
5
10
10
10
MAX
50
15
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
18
23
23
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1998, Micron Technology, Inc.
OBSOLETE
2, 4 MEG x 72
NONBUFFERED DRAM DIMMs
SERIAL PRESENCE-DETECT EEPROM OPERATING CONDITIONS
(Notes: 1) (VDD = +3.3V ±0.3V)
PARAMETER/CONDITION
SYMBOL
MIN
MAX
UNITS
SUPPLY VOLTAGE
VDD
3
3.6
V
INPUT HIGH VOLTAGE: Logic 1; All inputs
VIH
INPUT LOW VOLTAGE: Logic 0; All inputs
VIL
OUTPUT LOW VOLTAGE: IOUT = 3mA
VDD × 0.7 VDD + 0.5
V
-1
VDD × 0.3
V
VOL
–
0.4
V
INPUT LEAKAGE CURRENT: VIN = GND to VDD
ILI
–
10
µA
OUTPUT LEAKAGE CURRENT: VOUT = GND to VDD
ILO
–
10
µA
STANDBY CURRENT:
SCL = SDA = VDD - 0.3V; All other inputs = GND or 3.3V +10%
ISB
–
30
µA
POWER SUPPLY CURRENT:
SCL clock frequency = 100 KHz
ICC
–
2
mA
NOTES
SERIAL PRESENCE-DETECT EEPROM AC ELECTRICAL CHARACTERISTICS
(Notes: 1) (VDD = +3.3V ±0.3V)
PARAMETER/CONDITION
SCL LOW to SDA data-out valid
Time the bus must be free before a new transition can start
Data-out hold time
SDA and SCL fall time
Data-in hold time
Start condition hold time
Clock HIGH period
Noise suppression time constant at SCL, SDA inputs
Clock LOW period
SDA and SCL rise time
SCL clock frequency
Data-in setup time
Start condition setup time
Stop condition setup time
WRITE cycle time
2, 4 Meg x 72 Nonbuffered DRAM DIMMs
DM60.p65 – Rev. 6/98
SYMBOL
tAA
tBUF
tDH
tF
tHD:DAT
tHD:STA
tHIGH
tI
tLOW
tR
tSCL
tSU:DAT
tSU:STA
tSU:STO
tWR
14
MIN
0.3
4.7
300
MAX
3.5
300
0
4
4
100
4.7
1
100
250
4.7
4.7
10
UNITS
µs
µs
ns
ns
µs
µs
µs
ns
µs
µs
KHz
ns
µs
µs
ms
NOTES
28
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1998, Micron Technology, Inc.
OBSOLETE
2, 4 MEG x 72
NONBUFFERED DRAM DIMMs
NOTES
tAA (tRAC
and tCAC no longer applied). With or
without the tRAD (MAX) limit, tAA, tRAC and tCAC
must always be met.
18. Either tRCH or tRRH must be satisfied for a READ
cycle.
19. tOFF (MAX) defines the time at which the output
achieves the open circuit condition and is not
referenced to VOH or VOL.
20. A HIDDEN REFRESH may also be performed after
a WRITE cycle. In this case, WE# = LOW and
OE# = HIGH.
21. LATE WRITE and READ-MODIFY-WRITE cycles
must have both tOD and tOEH met (OE# HIGH
during WRITE cycle) in order to ensure that the
output buffers will be open during the WRITE cycle.
The DQs will provide the previously read data if
CAS# remains LOW and OE# is taken back LOW after
tOEH is met. If CAS# goes HIGH prior to OE# going
back LOW, the DQs will remain open.
22. These parameters are referenced to CAS# leading
edge in EARLY WRITE cycles and WE# leading edge
in LATE WRITE or READ-MODIFY-WRITE cycles.
23. tWCS, tRWD, tAWD and tCWD are not restrictive
operating parameters. tWCS applies to EARLY
WRITE cycles. tRWD, tAWD and tCWD apply to
READ-MODIFY-WRITE cycles. If tWCS ≥ tWCS
(MIN), the cycle is an EARLY WRITE cycle and the
data output will remain an open circuit throughout
the entire cycle. If tWCS < tWSC (MIN) and tRWD ≥
tRWD (MIN), tAWD ≥ tAWD (MIN) and tCWD ≥
tCWD (MIN), the cycle is a READ-MODIFY-WRITE
and the data output will contain data read from the
selected cell. If neither of the above conditions is met,
the state of data-out is indeterminate. OE# held HIGH
and WE# taken LOW after CAS# goes LOW result in a
LATE WRITE (OE#-controlled) cycle. tWCS, tRWD,
tCWD and tAWD are not applicable in a LATE
WRITE cycle.
24. Column address changed once each cycle.
25. The 3ns minimum parameter guaranteed by design.
26. With the FPM option, tOFF is determined by the first
RAS# or CAS# signal to transition HIGH. In comparison, tOFF on an EDO option is determined by the
latter of the RAS# and CAS# signals to transition
HIGH.
27. Applies to both FPM and EDO modules.
1. All voltages referenced to VSS.
2. This parameter is sampled. VDD = +3.3V; f = 1 MHz.
3. ICC is dependent on output loading. Specified values
are obtained with minimum cycle time and the
outputs open.
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to indicate
cycle time at which proper operation over the full
temperature range is ensured.
6. An initial pause of 100µs is required after power-up,
followed by eight RAS# REFRESH cycles (RAS#ONLY or CBR with WE# HIGH), before proper device
operation is ensured. The eight RAS# cycle wake-ups
should be repeated any time the tREF refresh
requirement is exceeded.
7. AC characteristics assume tT = 5ns for FPM and 2.5ns
for EDO.
8. VIH (MIN) and VIL (MAX) are reference levels for
measuring timing of input signals. Transition times
are measured between VIH and VIL (or between VIL
and VIH).
9. In addition to meeting the transition rate specification, all input signals must transit between VIH and
VIL (or between VIL and VIH) in a monotonic manner.
10. If CAS# = V IH, data output is High-Z.
11. If CAS# = V IL, data output may contain data from the
last valid READ cycle.
12. Measured with a load equivalent to two TTL gates
and 100pF and VOL = 0.8V and VOH = 2V.
13. Requires that tAA and tRAC are not violated.
14. Requires that tAA and tCAC are not violated.
15. If CAS# is LOW at the falling edge of RAS#, Q will be
maintained from the previous cycle. To initiate a new
cycle and clear the data-out buffer, CAS# must be
pulsed HIGH for tCP.
16. The tRCD (MAX) limit is no longer specified. tRCD
(MAX) was specified as a reference point only. If
tRCD was greater than the specified tRCD (MAX)
limit, then access time was controlled exclusively by
tCAC (tRAC [MIN] no longer applied). With or
without the tRCD (MAX) limit, tAA and tCAC must
always be met.
17. The tRAD (MAX) limit is no longer specified. tRAD
(MAX) was specified as a reference point only. If
tRAD was greater than the specified tRAD (MAX)
limit, then access time was controlled exclusively by
2, 4 Meg x 72 Nonbuffered DRAM DIMMs
DM60.p65 – Rev. 6/98
15
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1998, Micron Technology, Inc.
OBSOLETE
2, 4 MEG x 72
NONBUFFERED DRAM DIMMs
NOTES (continued)
28. The SPD EEPROM WRITE cycle time (tWR) is the
time from a valid stop condition of a write sequence
to the end of the EEPROM internal erase/program
cycle. During the WRITE cycle, the EEPROM bus
interface circuit are disabled, SDA remains HIGH due
to pull-up resistor, and the EEPROM does not
respond to its slave address.
2, 4 Meg x 72 Nonbuffered DRAM DIMMs
DM60.p65 – Rev. 6/98
29. If OE# is tied permanently LOW, LATE WRITE or
READ-MODIFY-WRITE operations are not possible.
30. VIH overshoot: VIH (MAX) = VDD + 2V for a pulse
width ≤ 10ns, and the pulse width cannot be greater
than one third of the cycle rate. VIL undershoot: VIL
(MIN) = -2V for a pulse width ≤ 10ns, and the pulse
width cannot be greater than one third of the cycle
rate.
16
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1998, Micron Technology, Inc.
OBSOLETE
2, 4 MEG x 72
NONBUFFERED DRAM DIMMs
READ CYCLE 27
tRC
tRP
tRAS
RAS#
V IH
V IL
tCSH
tRRH
tRSH
tRCD
tCRP
tCAS
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,, , ,
, ,
,
,
,,,,,,,,,,,,
,
,
,
,
,
, ,
,,,,
CAS#
V IH
V IL
tAR
tRAD
tASR
tRAH
tASC
tCAH
tACH
ADDR
V IH
V IL
ROW
ROW
COLUMN
tRCH
tRCS
WE#
V IH
V IL
tAA
tRAC
NOTE 1
tOFF
tCAC
tCLZ
DQ
V OH
V OL
OPEN
OE#
OPEN
VALID DATA
t OE
t OD
V IH
V IL
DON’T CARE
UNDEFINED
FAST PAGE MODE AND EDO PAGE MODE
TIMING PARAMETERS
-5*
SYMBOL
tAA
tACH (EDO)
tAR
tASC
tASR
MIN
12
38
15
45
0
0
0
0
ns
ns
tRAD
ns
ns
ns
tRAH
ns
ns
tRC
ns
ns
ns
tRCD
ns
ns
tRP
15
15
15
ns
ns
13
tCAH
(EDO)
8
8
(FPM)
tCLZ (EDO)
–
0
tCAS
tCLZ
(FPM)
(EDO)
–
5
38
tOD
(FPM)
(EDO)
–
0
tOD
(FPM)
–
tCRP
tCSH
MIN
tCSH
-5*
UNITS
ns
ns
ns
tCAC
tCAS
-6
MAX
25
tOE
10,000
–
MAX
30
15
10
10
15
0
10,000
10,000
3
5
45
12
–
12
60
0
3
SYMBOL
tOFF (EDO)
tOFF (FPM)
tRAC
tRAD
(EDO)
(FPM)
(EDO)
(FPM)
tRCD (EDO)
-6
MAX
12
–
50
9
–
9
50
84
tRAS
tRC
MIN
0
–
MIN
0
3
MAX
15
15
60
12
15
10,000
10
60
104
UNITS
ns
ns
ns
ns
ns
10,000
ns
ns
ns
–
11
110
14
ns
ns
–
0
0
20
0
0
ns
ns
ns
tRRH
30
0
40
0
ns
ns
tRSH
13
15
ns
tRCH
tRCS
(FPM)
*EDO version only
NOTE: 1. For EDO, tOFF is referenced from rising edge of RAS# or CAS#, whichever occurs last. For FPM, tOFF is referenced from rising edge of RAS# or
CAS#, whichever occurs first.
2, 4 Meg x 72 Nonbuffered DRAM DIMMs
DM60.p65 – Rev. 6/98
17
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1998, Micron Technology, Inc.
OBSOLETE
2, 4 MEG x 72
NONBUFFERED DRAM DIMMs
EARLY WRITE CYCLE 27
tRC
tRAS
RAS#
tRP
V IH
V IL
tCSH
tRSH
,
,
,
,
,, ,,, , ,,,
,
,
,
,,,,,,,,,,, ,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,
,, ,, ,,
tCRP
CAS#
tRCD
tCAS
V IH
V IL
tAR
tRAD
tASR
ADDR
V IH
V IL
tASC
tCAH
tACH
tRAH
ROW
ROW
COLUMN
tCWL
tRWL
tWCR
tWCS
tWCH
tWP
WE#
V IH
V IL
tDH
tDS
V
DQ V IOH
IOL
OE#
VALID DATA
V IH
V IL
,,
DON’T CARE
UNDEFINED
FAST PAGE MODE AND EDO PAGE MODE
TIMING PARAMETERS
-5*
SYMBOL
tACH (EDO)
tAR
tASC
tASR
tCAH
tCAS
(FPM)
tCAS
(EDO)
tCRP
tCSH
(FPM)
(EDO)
tCWL (FPM)
tCSH
tCWL
(EDO)
tDH
tDS
tRAD
(FPM)
MIN
12
-6
MAX
MIN
15
-5*
MAX
UNITS
ns
SYMBOL
tRAD (EDO)
MIN
9
-6
MAX
MIN
12
MAX
UNITS
ns
38
0
45
0
ns
ns
tRAH
0
8
–
0
10
15
ns
ns
ns
tRC
(FPM)
(EDO)
tRCD (FPM)
–
84
–
110
104
20
ns
ns
ns
ns
ns
tRCD
11
30
14
40
ns
ns
13
13
8
15
15
10
ns
ns
ns
38
0
45
0
ns
ns
–
5
10
5
ns
ns
8
5
–
10,000
10
5
10,000
10,000
9
50
tRAS
tRC
(EDO)
tRP
–
38
–
60
45
15
ns
ns
ns
tRSH
8
8
10
10
ns
ns
tWCR
0
–
0
15
ns
ns
tWP
tRWL
tWCH
tWCS
tWP
(FPM)
(EDO)
10,000
10
60
10,000
ns
ns
*EDO version only
2, 4 Meg x 72 Nonbuffered DRAM DIMMs
DM60.p65 – Rev. 6/98
18
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1998, Micron Technology, Inc.
OBSOLETE
2, 4 MEG x 72
NONBUFFERED DRAM DIMMs
FAST-PAGE-MODE READ CYCLE
tRASP
RAS#
V IH
V IL
tCSH
tRSH
tPC
tCRP
CAS#
tRP
tRCD
tCAS
tCP
tCAS
tCP
tCAS
tCP
,
,
,
,
,
,
,
,
,
,
,
,, ,,, , ,, , ,,,,
,
,
,
,
,
, ,
,
,
,,
,
,
,
,
,
,
,
,
,
,
,
,,
,
,, ,, , , , ,, ,,,
,
V IH
V IL
tAR
tRAD
tASR
ADDR
V IH
V IL
tRAH
tASC
ROW
tCAH
COLUMN
tCAH
COLUMN
tRCH
ROW
tRCS
tRRH
tRCH
tRCH
V IH
V IL
tAA
tAA
tRAC
tCPA
tOFF
tCLZ
V IOH
V IOL
tCAC
tAA
tCPA
tOFF
tCLZ
tCAC
tOFF
tCLZ
VALID
DATA
tOD
OPEN
tOE
OE#
tASC
COLUMN
tCAC
DQ
tCAH
tRCS
tRCS
WE#
tASC
tOE
VALID
DATA
tOD
tOE
VALID
DATA
tOD
OPEN
V IH
V IL
,
DON’T CARE
UNDEFINED
FAST PAGE MODE
TIMING PARAMETERS
-6
SYMBOL
tAA
tAR
tASC
tASR
MIN
tCAS
tCLZ
tCP
tCSH
tOD
2, 4 Meg x 72 Nonbuffered DRAM DIMMs
DM60.p65 – Rev. 6/98
SYMBOL
MIN
tOE
ns
tOFF
0
0
tPC
15
ns
ns
ns
tRAD
15
tRAH
10,000
ns
ns
tRCD
35
ns
ns
ns
10
60
20
ns
ns
tRP
ns
tRSH
10
15
3
10
tCPA
tCRP
UNITS
ns
45
tCAC
tCAH
-6
MAX
30
5
60
3
15
3
35
tRAC
tRASP
tRCH
tRCS
tRRH
19
MAX
UNITS
15
15
ns
ns
ns
60
ns
ns
125,000
ns
ns
ns
0
0
ns
ns
40
0
15
ns
ns
ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1998, Micron Technology, Inc.
OBSOLETE
2, 4 MEG x 72
NONBUFFERED DRAM DIMMs
EDO-PAGE-MODE READ CYCLE
tRASP
RAS#
tRP
V IH
V IL
tCSH
tRSH
tCAS
tPC
,,, ,,,, ,,, ,,, ,,,,,
, ,
,,,,,,
,
,
,,
,, ,,,,,, , ,,,,,,
,, ,
,, ,
,
tCRP
CAS#
tRCD
tCAS
tCAS
tCP
tCP
tCP
V IH
V IL
tAR
tRAD
tASR
ADDR
V IH
V IL
ROW
tACH
tACH
tACH
tASC
tRAH
tCAH
tASC
COLUMN
tCAH
tASC
COLUMN
tCAH
COLUMN
ROW
tRCS
WE#
tRCH
V IH
V IL
tAA
tRAC
tCPA
tCAC
tCAC
V OH
V OL
VALID
DATA
OPEN
tCAC
tCLZ
tOFF
tOEHC
VALID
DATA
tOE
OE#
tCPA
tCOH
tCLZ
DQ
tRRH
tAA
tAA
VALID
DATA
tOD
tOES
V IH
V IL
OPEN
tOE
tOD
tOES
tOEP
DON’T CARE
UNDEFINED
EDO PAGE MODE
TIMING PARAMETERS
-5
SYMBOL
tAA
tACH
tAR
tASC
tASR
MIN
tCAS
tCLZ
tCOH
tCP
MIN
UNITS
ns
SYMBOL
tOEHC
15
45
ns
ns
tOEP
0
0
0
0
tOFF
15
ns
ns
ns
tRAD
10,000
ns
ns
ns
ns
ns
tRASP
ns
ns
tRCS
ns
ns
ns
tRRH
13
8
8
10,000
0
3
8
tCPA
10
10
0
3
10
28
35
tCRP
5
5
tCSH
38
0
45
0
tOD
-5
MAX
30
12
38
tCAC
tCAH
-6
MAX
25
tOE
2, 4 Meg x 72 Nonbuffered DRAM DIMMs
DM60.p65 – Rev. 6/98
12
12
15
15
tOES
tPC
MIN
5
5
4
0
20
tRAC
tRAH
tRCD
tRCH
tRP
tRSH
20
-6
MAX
MIN
10
5
5
12
0
25
50
9
9
50
11
0
MAX
ns
ns
15
60
12
10
125,000
60
14
0
UNITS
ns
ns
ns
ns
ns
ns
125,000
ns
ns
ns
0
30
0
40
ns
ns
0
13
0
15
ns
ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1998, Micron Technology, Inc.
OBSOLETE
2, 4 MEG x 72
NONBUFFERED DRAM DIMMs
FAST/EDO-PAGE-MODE EARLY WRITE CYCLE 27
tRP
tRASP
V IH
V IL
RAS#
tCSH
tPC
tRSH
,
,
,
,
,
,,,,, ,,, ,, , ,
,
,
,
,
,
,
,
,
,
,
,,,,, , ,, ,, ,,,,,,
,,,,,,,,,,,,,,,,,,,,
, ,,
tCRP
tRCD
tCAS
tCP
tCAS
tCP
tCAS
tCP
V IH
V IL
CAS#
tAR
tRAD
tASR
V IH
V IL
ADDR
tRAH
tACH
tASC
ROW
tACH
tCAH
tASC
COLUMN
tASC
COLUMN
tCAH
COLUMN
tCWL
tWCS
tACH
tCAH
tCWL
tWCH
tWCS
tWCH
tWP
ROW
tCWL
tWCS
tWCH
tWP
tWP
V IH
V IL
WE#
tWCR
tDS
V
DQ V IOH
IOL
tDH
tDS
VALID DATA
tDH
tRWL
tDH
tDS
VALID DATA
VALID DATA
V IH
V IL
OE#
,
DON’T CARE
UNDEFINED
FAST PAGE MODE AND EDO PAGE MODE
TIMING PARAMETERS
-5*
SYMBOL
tACH
(EDO)
tAR
tASC
tASR
tCAH
tCAS
(EDO)
tCAS
(FPM)
tCP
tCRP
tCSH
tCSH
tCWL
tCWL
-6
MAX
MIN
-5*
MAX
UNITS
12
15
ns
38
0
0
45
0
0
ns
ns
ns
8
8
–
8
5
10,000
–
10
10
15
10
5
10,000
10,000
SYMBOL
tPC (FPM)
tRAD (EDO)
tRAD
(FPM)
tRAH
tRASP
ns
ns
tRCD
(EDO)
tRCD (FPM)
ns
ns
ns
tRP
tRSH
MIN
–
9
-6
MAX
–
9
50
11
–
MIN
35
12
MAX
15
10
125,000
60
14
20
UNITS
ns
ns
ns
ns
125,000
ns
ns
ns
30
13
40
15
ns
ns
13
8
38
15
10
45
ns
ns
ns
(EDO)
(FPM)
38
–
45
60
ns
ns
tRWL
(EDO)
(FPM)
8
–
8
10
15
10
ns
ns
ns
tWCR
tWP
(EDO)
0
5
0
5
ns
ns
0
20
0
25
ns
ns
tWP
(FPM)
–
10
ns
tDH
tDS
tPC
MIN
(EDO)
tWCH
tWCS
*EDO version only
2, 4 Meg x 72 Nonbuffered DRAM DIMMs
DM60.p65 – Rev. 6/98
21
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1998, Micron Technology, Inc.
OBSOLETE
2, 4 MEG x 72
NONBUFFERED DRAM DIMMs
READ-WRITE CYCLE 27
(LATE WRITE and READ-MODIFY-WRITE cycles)
tRWC
tRAS
RAS#
tRP
V IH
V IL
tCSH
tRSH
,
,
,
,
,
,
,
,
,
,,, , , ,, , ,, ,
,,,,,
,,,,,,
,
,
,
,
,
,
,
,
,
,,,, ,, ,, ,,,,,,
,,
tCRP
CAS#
tRCD
tAR
tRAD
tASR
ADDR
tCAS
V IH
V IL
V IH
V IL
tASC
tCAH
tRAH
tACH
ROW
COLUMN
tRCS
WE#
ROW
tRWD
tCWL
tCWD
tRWL
tAWD
tWP
V IH
V IL
tAA
tRAC
tCAC
tDS
t CLZ
V
DQ V IOH
IOL
VALID D OUT
OPEN
tOE
OE#
tDH
VALID D IN
tOD
OPEN
tOEH
V IH
V IL
DON’T CARE
FAST PAGE MODE AND EDO PAGE MODE
TIMING PARAMETERS
-5*
SYMBOL
tAA
tACH (EDO)
tAR
tASC
tASR
MIN
UNDEFINED
-6
MAX
25
MIN
-5*
MAX
30
12
38
0
0
15
45
0
0
UNITS
ns
ns
ns
ns
ns
SYMBOL
tOD (EDO)
tOD (FPM)
tOE
tOEH (EDO)
tOEH (FPM)
tAWD
(EDO)
42
49
ns
tRAC
tAWD
(FPM)
–
55
tRAD
15
ns
ns
ns
10,000
10,000
ns
ns
tRAS
tRCD
(EDO)
(FPM)
tCAC
13
tCAH
8
tCAS
10
8
–
(EDO)
(FPM)
0
–
5
0
3
5
ns
ns
ns
tRCD
(EDO)
(FPM)
38
–
45
60
ns
ns
tRSH
(EDO)
(FPM)
tCWL (EDO)
28
–
8
35
40
10
ns
ns
ns
tRWC
tDH
–
8
15
10
tDS
0
0
tCLZ
tCLZ
tCRP
tCSH
tCSH
tCWD
tCWD
tCWL
(FPM)
10,000
–
10
15
-6
MAX
12
–
12
8
–
MIN
0
3
9
–
9
50
11
MAX
15
15
15
10/12**
15
50
(EDO)
tRAD (FPM)
tRAH
(EDO)
(FPM)
tCAS
MIN
0
–
60
12
15
10
10,000
60
14
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
10,000
ns
ns
–
0
30
20
0
40
ns
ns
ns
(EDO)
13
116
15
140
ns
ns
(FPM)
(EDO)
tRWD (FPM)
–
67
–
155
79
85
ns
ns
ns
ns
ns
tRWL
tWP
(EDO)
13
5
15
5
ns
ns
ns
tWP
(FPM)
–
10
ns
tRCS
tRP
tRWC
tRWD
* EDO version only
**16MB DIMM
2, 4 Meg x 72 Nonbuffered DRAM DIMMs
DM60.p65 – Rev. 6/98
22
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1998, Micron Technology, Inc.
OBSOLETE
2, 4 MEG x 72
NONBUFFERED DRAM DIMMs
FAST/EDO-PAGE-MODE READ-WRITE CYCLE 27
(LATE WRITE and READ-MODIFY-WRITE cycles)
tRASP
tRP
V IH
V IL
RAS#
tCSH
tPRWC NOTE 1
t PC
tRSH
,
,
,
,
,
,
,
, , ,, ,, ,, ,
,
,
,
,
,
,, ,
,,
,,
,,
,
,
,
,
,
,,
,
,
,
,
,, ,, ,,
,
,
,
,,,
tCRP
tRCD
tCAS
tCP
tCAS
tCP
tCAS
tCP
V IH
V IL
CAS#
tAR
tRAD
tASR
V IH
V IL
ADDR
tRAH
tASC
ROW
tCAH
tASC
COLUMN
tCAH
tASC
COLUMN
tCAH
COLUMN
ROW
tRWD
tRCS
tRWL
tCWL
tCWL
tWP
tAWD
tWP
tAWD
tAWD
tCWD
tCWD
tCWD
V IH
V IL
WE#
tAA
tAA
tRAC
tDH
tCLZ
VALID
D IN
VALID
D OUT
tOD
VALID
D IN
VALID
D OUT
tOD
tOE
OE#
tDS
tCAC
tCLZ
VALID
D OUT
OPEN
tDH
tCPA
tDS
tCAC
tCLZ
V IOH
V IOL
tAA
tDH
tCPA
tDS
tCAC
DQ
tCWL
tWP
tOE
VALID
D IN
OPEN
tOD
tOE
tOEH
V IH
V IL
DON’T CARE
FAST PAGE MODE AND EDO PAGE MODE
TIMING PARAMETERS
-5*
SYMBOL
tAA
tAR
tASC
tASR
tAWD (EDO)
tAWD (FPM)
tCAC
tCAH
tCAS
tCLZ
13
(EDO)
(FPM)
0
–
8
tCP
MIN
tCPA
MAX
30
45
0
0
49
55
8
8
–
-5*
-6
MAX
25
38
0
0
42
–
(EDO)
(FPM)
tCAS
tCLZ
MIN
UNDEFINED
15
10
10,000
–
10
15
10,000
10,000
0
3
10
28
tOD
(FPM)
MAX
MIN
MAX
UNITS
–
–
12
3
15
15
ns
ns
ns
ns
ns
ns
ns
ns
60
tOE
tOEH
(EDO)
(FPM)
tPC (EDO)
tPC (FPM)
tPRWC (EDO)
tPRWC (FPM)
tOEH
-6
MIN
8
–
20
–
47
–
10/12**
15
25
35
56
85
ns
ns
tRAC
tRAD
(EDO)
9
12
ns
ns
ns
ns
ns
tRAD
(FPM)
–
9
50
15
10
60
ns
ns
ns
tRCD
(EDO)
tRCD (FPM)
11
–
14
20
ns
ns
0
30
13
0
40
15
ns
ns
ns
67
–
79
85
ns
ns
50
tRAH
tRASP
125,000
125,000
tCRP
5
5
ns
ns
tCSH
38
–
28
45
60
35
ns
ns
ns
tRCS
(FPM)
tCWL (EDO)
–
8
40
10
ns
ns
tRWD
tCWL
–
8
15
10
ns
ns
tRWL
tWP
(EDO)
13
5
15
5
ns
ns
0
0
0
0
ns
ns
tWP
(FPM)
–
10
ns
(EDO)
(FPM)
tCWD (EDO)
tCSH
tCWD
(FPM)
tDH
tDS
tOD
(EDO)
12
35
SYMBOL
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
15
tRP
tRSH
tRWD
* EDO version only
**16MB DIMM
NOTE: 1. tPC is for LATE WRITE cycles only.
2, 4 Meg x 72 Nonbuffered DRAM DIMMs
DM60.p65 – Rev. 6/98
(EDO)
(FPM)
23
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1998, Micron Technology, Inc.
OBSOLETE
2, 4 MEG x 72
NONBUFFERED DRAM DIMMs
EDO-PAGE-MODE READ EARLY WRITE CYCLE
(Pseudo READ-MODIFY-WRITE)
t RP
t RASP
RAS#
V IH
V IL
t CSH
t PC
t CRP
t RCD
t RSH
t PC
t CP
t CAS
t CP
t CAS
t CP
t CAS
,, ,, ,,, ,,,, ,,,
,
,,,,,
,
,, ,,,,
,,,
, ,
CAS#
V IH
V IL
t AR
t RAD
tASR
ADDR
V IH
V IL
t ACH
t RAH
t ASC
ROW
t CAH
t ASC
COLUMN (A)
t CAH
COLUMN (B)
V IH
V IL
t WCS
ROW
t WCH
t AA
t AA
t CPA
t RAC
t CAC
t CAC
t COH
DQ V IOH
V IOL
t CAH
COLUMN (N)
t RCH
t RCS
WE#
t ASC
OPEN
VALID DATA (A)
t DS
t DH
t WHZ
VALID
DATA (B)
VALID DATA
IN
t OE
OE#
V IH
V IL
DON’T CARE
UNDEFINED
EDO PAGE MODE
TIMING PARAMETERS
-5
SYMBOL
MIN
tAA
-6
MAX
MIN
UNITS
SYMBOL
30
tOE
tACH
12
15
ns
ns
tAR
38
0
0
45
0
0
ns
ns
ns
tRAC
ns
ns
tRASP
ns
ns
ns
tRCH
tRSH
tWCS
tASC
tASR
25
-5
MAX
tCAC
13
tCAH
8
tCAS
8
3
8
tCOH
tCP
tCPA
15
10
10,000
10
3
10
tCRP
5
5
ns
ns
tCSH
38
8
0
45
10
0
ns
ns
ns
tDH
tDS
28
10,000
2, 4 Meg x 72 Nonbuffered DRAM DIMMs
DM60.p65 – Rev. 6/98
35
tPC
tRAD
tRAH
tRCD
tRCS
tRP
tWCH
tWHZ
24
MIN
-6
MAX
MIN
12
20
UNITS
15
ns
ns
60
ns
ns
ns
125,000
ns
ns
25
50
9
9
50
11
MAX
12
10
125,000
60
14
0
0
30
0
0
40
ns
ns
ns
13
8
15
10
ns
ns
0
0
12
0
0
15
ns
ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1998, Micron Technology, Inc.
OBSOLETE
2, 4 MEG x 72
NONBUFFERED DRAM DIMMs
FAST-PAGE-MODE READ EARLY WRITE CYCLE
(Pseudo READ-MODIFY-WRITE)
tRASP
RAS#
tRP
V IH
V IL
tRSH
tCSH
tCRP
tRCD
tCAS
,, ,,
,
,
,
,
,, ,
,
,,,
CAS#
tPC
V IH
V IL
tAR
tRAD
tASR
ADDR
V IH
V IL
ROW
DQ
OE#
tCAH
ROW
COLUMN
tCWL
tRWL
tWP
tWCS
V IH
V IL
V OH
V OL
tCP
,
,
,
,
,
,
, , ,,
,
,
,
,
, ,
,
,
,,
COLUMN
tRCS
WE#
tCAS
tASC
tCAH
tASC
tRAH
tCP
tCAC
t CLZ
NOTE 1
t OFF
tDS
VALID
DATA
OPEN
tAA
t RAC
V IH
V IL
tWCH
tDH
VALID DATA
DON’T CARE
UNDEFINED
FAST PAGE MODE
TIMING PARAMETERS
-6
-6
SYMBOL
tAA
tAR
tASC
tASR
MIN
tRAD
15
ns
ns
tRAH
10
60
ns
ns
ns
tRCD
5
60
ns
ns
tRSH
15
10
0
ns
ns
ns
tWCH
15
10
tCAS
15
3
10
tCRP
tCSH
tCWL
tDH
tDS
MIN
3
tPC
tCAH
tCP
SYMBOL
tOFF
UNITS
ns
ns
ns
ns
45
0
0
tCAC
tCLZ
MAX
30
10,000
tRCS
tRP
tRWL
tWCS
tWP
UNITS
ns
60
ns
ns
ns
35
tRAC
tRASP
MAX
15
125,000
ns
ns
20
0
40
ns
ns
ns
15
15
ns
ns
10
0
10
ns
ns
ns
NOTE: 1. Do not drive data prior to tristate.
2, 4 Meg x 72 Nonbuffered DRAM DIMMs
DM60.p65 – Rev. 6/98
25
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1998, Micron Technology, Inc.
OBSOLETE
2, 4 MEG x 72
NONBUFFERED DRAM DIMMs
EDO READ CYCLE
(with WE#-controlled disable)
RAS#
V IH
V IL
tCSH
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,, , ,
,,,,,,,,,,,,,
,,,,,,,,
,
,
,
,
tRCD
tCRP
CAS#
tCAS
tCP
V IH
V IL
tAR
tRAD
tASR
ADDR
V IH
V IL
tRAH
tASC
ROW
tCAH
tASC
COLUMN
COLUMN
tRCS
WE#
tRCH
tWPZ
tRCS
V IH
V IL
tAA
tRAC
tCAC
tWHZ
tCLZ
DQ
V OH
V OL
OPEN
OPEN
VALID DATA
t OE
OE#
tCLZ
t OD
V IH
V IL
DON’T CARE
UNDEFINED
EDO PAGE MODE
TIMING PARAMETERS
-5
SYMBOL
MIN
tAA
tAR
tASC
tASR
tCAH
tCAS
tCLZ
MIN
25
38
45
0
0
0
0
tCAC
13
8
8
-5
-6
MAX
10,000
10
10
UNITS
30
ns
ns
tOD
tRAC
15
ns
ns
ns
tRCD
10,000
ns
ns
tRCS
tCRP
0
8
5
0
10
5
ns
ns
ns
tCSH
38
45
ns
tCP
2, 4 Meg x 72 Nonbuffered DRAM DIMMs
DM60.p65 – Rev. 6/98
SYMBOL
MAX
MAX
MIN
MAX
UNITS
0
12
12
0
15
15
ns
ns
60
tOE
tRAD
tRAH
tRCH
tWHZ
tWPZ
26
-6
MIN
9
9
50
12
10
ns
ns
ns
11
0
14
0
ns
ns
0
0
10
12
0
0
10
15
ns
ns
ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1998, Micron Technology, Inc.
OBSOLETE
2, 4 MEG x 72
NONBUFFERED DRAM DIMMs
RAS#-ONLY REFRESH CYCLE 27
tRC
tRAS
tRP
,
,
,
,
,
,,, ,, ,,,,,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
, , , , , ,
RAS#
V IH
V IL
tRPC
tCRP
CAS#
V IH
V IL
tASR
ADDR
tRAH
V IH
V IL
ROW
ROW
V
DQ V OH
OL
WE#
OPEN
V IH
V IL
CBR REFRESH CYCLE 27
(Addresses, OE# = DON’T CARE)
tRP
RAS#
tRAS
tRP
NOTE 1
tRAS
V IH
V IL
tRPC
,,,,,,,,,,,,,,,,,,,,
,
,,,
tCP
CAS#
V IH
V IL
DQ
V OH
V OL
tCSR
tCHR
OPEN
tWRP
WE#
tRPC
tCHR
tCSR
tWRH
tWRP
tWRH
V IH
V IL
,
DON’T CARE
UNDEFINED
FAST PAGE MODE AND EDO PAGE MODE
TIMING PARAMETERS
-5*
SYMBOL
tASR
tCHR
MIN
0
-6
MAX
MIN
0
-5*
MAX
UNITS
ns
SYMBOL
tRC (FPM)
8
8
10
10
ns
ns
tRC
5
5
10
ns
ns
ns
tRPC
tRAH
5
5
9
tRAS
50
ns
tCP
tCRP
tCSR
10,000
60
10,000
MIN
–
(EDO)
-6
MAX
MIN
110
MAX
UNITS
ns
84
30
104
40
ns
ns
tRPC
(FPM)
(EDO)
tWRH
–
5
8
0
5
10
ns
ns
ns
tWRP
8
10
ns
tRP
*EDO version only
2, 4 Meg x 72 Nonbuffered DRAM DIMMs
DM60.p65 – Rev. 6/98
27
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1998, Micron Technology, Inc.
OBSOLETE
2, 4 MEG x 72
NONBUFFERED DRAM DIMMs
HIDDEN REFRESH CYCLE 20, 27
(WE# = HIGH; OE# = LOW)
tRC
tRAS
RAS#
tRP
tRAS
V IH
V IL
,
,
,
,
,
,
,,
,
,,, ,, ,,,, , ,,,
,,
,,,,,,,,,, ,,,,
, ,
,
,
,,
tCRP
CAS#
tRSH
tRCD
tCHR
V IH
V IL
tAR
tRAD
tASR
ADDR
V IH
V IL
tRAH
tASC
ROW
tCAH
COLUMN
tAA
tRAC
tCAC
tOFF
tCLZ
V
DQ V IOH
IOL
OPEN
VALID DATA
OPEN
tOD
tOE
OE#
tORD
V IH
V IL
DON’T CARE
UNDEFINED
FAST PAGE MODE AND EDO PAGE MODE
TIMING PARAMETERS
-5*
SYMBOL
tAA
tAR
tASC
tASR
MIN
-6
MIN
-5*
MAX
30
SYMBOL
tOFF (EDO)
tORD
MIN
0
0
-6
38
45
UNITS
ns
ns
0
0
0
0
ns
ns
tRAC
tRAD
(FPM)
–
15
ns
ns
(EDO)
9
9
50
12
10
60
ns
ns
ns
tCAC
MAX
25
MAX
12
MIN
0
0
50
MAX
15
UNITS
ns
ns
60
10
10
ns
ns
ns
tRAD
8
8
tCLZ
(FPM)
tCLZ (EDO)
–
0
3
0
ns
ns
tRC
(FPM)
tRC (EDO)
–
84
110
104
ns
ns
tCRP
5
–
0
5
3
0
15
15
ns
ns
ns
tRCD
–
12
tRP
–
11
30
20
14
40
ns
ns
ns
12
–
ns
ns
13
15
ns
3
15
15
tRSH
–
13
tCAH
tCHR
tOD
(FPM)
tOD (EDO)
tOE
tOFF
(FPM)
15
tRAH
tRAS
tRCD
(FPM)
(EDO)
10,000
10,000
*EDO version only
2, 4 Meg x 72 Nonbuffered DRAM DIMMs
DM60.p65 – Rev. 6/98
28
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1998, Micron Technology, Inc.
OBSOLETE
2, 4 MEG x 72
NONBUFFERED DRAM DIMMs
SPD EEPROM
tF
tHIGH
tR
tLOW
SCL
t HD:STA
t SU:STA
t SU:DAT
t HD:DAT
t SU:STO
SDA IN
,,,,,,
tDH
tAA
tBUF
,
SDA OUT
UNDEFINED
SERIAL PRESENCE-DETECT EEPROM
TIMING PARAMETERS
SYMBOL
tAA
tBUF
tDH
tF
tHD:DAT
tHD:STA
2, 4 Meg x 72 Nonbuffered DRAM DIMMs
DM60.p65 – Rev. 6/98
MIN
0.3
4.7
300
MAX
3.5
300
0
4
UNITS
µs
µs
ns
ns
µs
µs
SYMBOL
tHIGH
tLOW
tR
tSU:DAT
tSU:STA
tSU:STO
29
MIN
4
4.7
MAX
1
250
4.7
4.7
UNITS
µs
µs
µs
ns
µs
µs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1998, Micron Technology, Inc.
OBSOLETE
2, 4 MEG x 72
NONBUFFERED DRAM DIMMs
168-PIN DIMM
DF-12 (16MB)
FRONT VIEW
5.256 (133.50)
5.244 (133.20)
.200 (5.08)
MAX
.079 (2.00) R
(2X)
1.005 (25.53)
.995 (25.27)
.700 (17.78)
TYP
.118 (3.00)
(2X)
.118 (3.00) TYP
.250 (6.35) TYP
.118 (3.00)
TYP
1.661 (42.18)
.039 (1.00) R(2X)
2.625 (66.68)
.128 (3.25)
(2X)
.118 (3.00)
.050 (1.27)
TYP
.039 (1.00)
TYP
PIN 1 (PIN 85 on backside)
.054 (1.37)
.046 (1.17)
PIN 84 (PIN 168 ON BACKSIDE)
4.550 (115.57)
168-PIN DIMM
DF-13 (32MB)
FRONT VIEW
5.256 (133.50)
5.244 (133.20)
.350 (8.89)
MAX
.079 (2.00) R
(2X)
1.005 (25.53)
.995 (25.27)
.118 (3.00)
(2X)
.700 (17.78)
TYP
.118 (3.00) TYP
.054 (1.37)
.046 (1.17)
.250 (6.35) TYP
.118 (3.00)
TYP
.039 (1.00) R(2X)
PIN 1
.050 (1.27)
TYP
.039 (1.00)
TYP
PIN 84
4.550 (115.57)
BACK VIEW
.128 (3.25) (2X)
.118 (3.00)
1.661 (42.18)
2.625 (66.68)
PIN 168
NOTE:
1. All dimensions in inches (millimeters)
2, 4 Meg x 72 Nonbuffered DRAM DIMMs
DM60.p65 – Rev. 6/98
PIN 85
MAX
or typical where noted.
MIN
30
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1998, Micron Technology, Inc.