OBSOLETE 4, 8 MEG x 36 PARITY DRAM SIMMs MT12D436 MT24D836 DRAM MODULE FEATURES • JEDEC- and industry-standard pinout in a 72-pin, single in-line memory module (SIMM) • 16MB (4 Meg x 36) and 32MB (8 Meg x 36) parity versions • High-performance CMOS silicon-gate process • Single 5V ±10% power supply • All inputs, outputs and clocks are TTL-compatible • Refresh modes: RAS#-ONLY, CAS#-BEFORE-RAS# (CBR) and HIDDEN • 2,048-cycle refresh distributed across 32ms • FAST PAGE MODE (FPM) access cycle • Multiple RAS# lines allow x18 or x36 widths OPTIONS MARKING • Timing 60ns access -6 • Packages 72 -pin SIMM 72 -pin SIMM (gold) 72-pin SIMM low profile (1.00") 72-pin SIMM (gold) low profile (1.00") PIN ASSIGNMENT (Front View) 72-Pin SIMM (DD-5) 4 Meg x 36 (shown) (DD-6) 8 Meg x 36 (DD-7) 4 Meg x 36 Low Profile PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN 1 Vss 19 A10 37 DQ18 55 2 DQ1 20 DQ5 38 DQ36 56 3 DQ19 21 DQ23 39 Vss 57 4 DQ2 22 DQ6 40 CAS0# 58 5 DQ20 23 DQ24 41 CAS2# 59 6 DQ3 24 DQ7 42 CAS3# 60 7 DQ21 25 DQ25 43 CAS1# 61 8 DQ4 26 DQ8 44 RAS0# 62 9 DQ22 27 DQ26 45 NC/RAS1#* 63 10 Vcc 28 A7 46 NC 64 11 NC 29 NC (A11) 47 WE# 65 12 A0 30 Vcc 48 NC 66 13 A1 31 A8 49 DQ10 67 14 A2 32 A9 50 DQ28 68 15 A3 33 NC/RAS3#* 51 DQ11 69 16 A4 34 RAS2# 52 DQ29 70 17 A5 35 DQ27 53 DQ12 71 18 A6 36 DQ9 54 DQ30 72 *32MB version only M G DM DG KEY TIMING PARAMETERS SPEED -6 tRC tRAC tPC tAA tCAC tRP 110ns 60ns 35ns 30ns 15ns 40ns PART NUMBERS PART NUMBER MT12D436G-xx MT12D436M-xx MT12D436DG-xx MT12D436DM-xx MT24D836G-xx MT24D836M-xx xx = speed CONFIGURATION 4 Meg x 36 4 Meg x 36 4 Meg x 36 4 Meg x 36 8 Meg x 36 8 Meg x 36 PLATING Gold Tin/Lead Gold Tin/Lead Gold Tin/Lead HEIGHT 1.190" 1.190" 1.000" 1.000" 1.190" 1.190" SYMBOL DQ13 DQ31 DQ14 DQ32 Vcc DQ33 DQ15 DQ34 DQ16 DQ35 DQ17 NC PRD1 PRD2 PRD3 PRD4 NC Vss NOTE: Symbols in parentheses are not used on these modules but may be used for other modules in this product family. They are for reference only. GENERAL DESCRIPTION The MT12D436 and MT24D836 are randomly accessed 16MB and 32MB solid-state memories organized in a x36 configuration. During READ or WRITE cycles, each bit is uniquely addressed through the 22 address bits, which are entered 11 bits (A0 -A10) at a time. RAS# is used to latch the first 11 bits and CAS# the latter 11 bits. A READ or WRITE 4, 8 Meg x 36 Parity DRAM SIMMs DM45.pm5 – Rev. 3/97 cycle is selected with the WE# input. A logic HIGH on WE# dictates READ mode, while a logic LOW on WE# dictates WRITE mode. During a WRITE cycle, data-in (D) is latched by the falling edge of CAS#. Since WE# goes LOW prior to CAS# going LOW, the output pin(s) remain open (High-Z) until the next CAS# cycle. 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. „1997, Micron Technology, Inc. OBSOLETE 4, 8 MEG x 36 PARITY DRAM SIMMs FAST PAGE MODE FAST PAGE MODE operations allow faster data operations (READ or WRITE) within a row-address-defined (A0 A10) page boundary. The FAST PAGE MODE cycle is always initiated with a row address strobed-in by RAS# followed by a column address strobed-in by CAS#. CAS# may be toggled-in by holding RAS# LOW and strobing-in different column addresses, thus executing faster memory cycles. Returning RAS# HIGH terminates the FAST PAGE MODE operation. the RAS# HIGH time. Memory cell data is retained in its correct state by maintaining power and executing any RAS# cycle (READ, WRITE) or RAS# refresh cycle (RAS# ONLY, CBR or HIDDEN) so that all 2,048 combinations of RAS# addresses (A 0-A10) are executed at least every 32ms, regardless of sequence. The CBR REFRESH cycle will invoke the refresh counter for automatic RAS# addressing. x18 CONFIGURATION For x18 applications, the corresponding DQ and CAS# pins must be connected together (DQ1 to DQ19, DQ2 to DQ20 and so forth, and CAS0# to CAS2# and CAS1# to CAS3#). Each RAS# is then a bank select for the x18 memory organization. REFRESH Returning RAS# and CAS# HIGH terminates a memory cycle and decreases chip current to a reduced standby level. Also, the chip is preconditioned for the next cycle during FUNCTIONAL BLOCK DIAGRAM MT12D436 (16MB) DQ1 DQ10 DQ9 DQ1-4 WE# DQ1-4 WE# D Q WE# DQ1-4 WE# U2 U1 DQ18 U9 DQ1-4 WE# U5 D Q WE# U6 U10 CAS0# CAS# CAS# CAS# CAS# CAS# CAS# RAS0# RAS# RAS# RAS# RAS# RAS# RAS# OE# A0-A10 OE# A0-A10 OE# A0-A10 OE# A0-A10 11 11 11 11 CAS1# A0-A10 11 A0-A10 11 WE# DQ19 DQ27 DQ1-4 WE# DQ1-4 WE# U3 D Q WE# DQ28 DQ36 DQ1-4 WE# U11 U4 DQ1-4 WE# U7 Q D WE# U12 U8 CAS2# CAS# CAS# CAS# CAS# CAS# CAS# RAS2# RAS# RAS# RAS# RAS# RAS# RAS# OE# A0-A10 OE# A0-A10 OE# A0-A10 OE# A0-A10 11 11 11 11 CAS3# A0-A10 11 A0-A10 11 A0-A10 VCC U1-U12 VSS U1-U12 4, 8 Meg x 36 Parity DRAM SIMMs DM45.pm5 – Rev. 3/97 U1-U8 = 4 Meg x 4 DRAMs U9-U12 = 4 Meg x 1 DRAMs 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. „1997, Micron Technology, Inc. OBSOLETE 4, 8 MEG x 36 PARITY DRAM SIMMs FUNCTIONAL BLOCK DIAGRAM MT24D836 (32MB) DQ1 DQ10 DQ9 DQ1 - 4 WE# DQ1 - 4 D Q WE# WE# U1 DQ18 DQ1 - 4 WE# U2 DQ1 - 4 WE# U17 D Q WE# U5 U6 U18 CAS0# CAS# CAS# CAS# CAS# CAS# CAS# RAS0# RAS# RAS# RAS# RAS# RAS# RAS# OE# A0-A10 OE# A0-A10 OE# A0-A10 OE# A0-A10 11 11 11 11 CAS1# A0-A10 11 DQ19 DQ27 DQ1 - 4 WE# WE# DQ1 - 4 D Q WE# WE# U3 11 DQ28 DQ36 DQ1 - 4 WE# U4 A0-A10 DQ1 - 4 WE# U7 U19 Q D WE# U8 U20 CAS2# CAS# CAS# CAS# CAS# CAS# CAS# RAS2# RAS# RAS# RAS# RAS# RAS# RAS# OE# A0-A10 OE# A0-A10 OE# A0-A10 OE# A0-A10 11 11 11 11 11 DQ9 DQ10 CAS3# A0-A10 A0-A10 11 A0-A10 DQ1 DQ1 - 4 WE# DQ1 - 4 RAS1# WE# U16 DQ1 - 4 WE# U11 U21 Q D WE# U12 U22 CAS# CAS# CAS# CAS# CAS# RAS# RAS# RAS# RAS# RAS# RAS# OE# A0-A10 OE# A0-A10 OE# A0-A10 OE# A0-A10 11 11 11 11 DQ1 - 4 WE# A0-A10 11 DQ27 DQ1 - 4 D Q WE# WE# U13 4, 8 Meg x 36 Parity DRAM SIMMs DM45.pm5 – Rev. 3/97 DQ1 - 4 CAS# DQ19 RAS3# Q WE# WE# U15 D DQ18 11 DQ28 DQ36 DQ1 - 4 WE# U14 A0-A10 DQ1 - 4 WE# U9 U23 D Q WE# U10 U24 CAS# CAS# CAS# CAS# CAS# CAS# RAS# RAS# RAS# RAS# RAS# RAS# OE# A0-A10 OE# A0-A10 OE# A0-A10 OE# A0-A10 11 11 11 11 VCC U1-U24 VSS U1-U24 A0-A10 11 A0-A10 11 U1-U16 = 4 Meg x 4 DRAMs U17-U24 = 4 Meg x 1 DRAMs 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. „1997, Micron Technology, Inc. OBSOLETE 4, 8 MEG x 36 PARITY DRAM SIMMs TRUTH TABLE ADDRESSES DATA-IN/OUT RAS# CAS# WE# tR tC DQ1-DQ36 Standby H H→X X X X High-Z READ L L H ROW COL Data-Out EARLY WRITE L L L ROW COL Data-In FUNCTION FAST-PAGE-MODE 1st Cycle L H→L H ROW COL Data-Out READ 2nd Cycle L H→L H n/a COL Data-Out FAST-PAGE-MODE 1st Cycle L H→L L ROW COL Data-In EARLY-WRITE 2nd Cycle L H→L L n/a COL Data-In RAS#-ONLY REFRESH L H X ROW n/a High-Z HIDDEN READ L→H→L L H ROW COL Data-Out REFRESH WRITE L→H→L L L ROW COL Data-In H→L L H X X High-Z CBR REFRESH JEDEC-DEFINED PRESENCE-DETECT – MT12D436 (16MB) SYMBOL PIN -6 PRD1 67 VSS PRD2 68 NC PRD3 69 NC PRD4 70 NC JEDEC-DEFINED PRESENCE-DETECT – MT24D836 (32MB) 4, 8 Meg x 36 Parity DRAM SIMMs DM45.pm5 – Rev. 3/97 SYMBOL PIN -6 PRD1 67 NC PRD2 68 VSS PRD3 69 NC PRD4 70 NC 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. „1997, Micron Technology, Inc. OBSOLETE 4, 8 MEG x 36 PARITY DRAM SIMMs *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to VSS .................... -1V to +7V Operating Temperature, TA (ambient) .......... 0°C to +70°C Storage Temperature (plastic) .................... -55°C to +125°C Power Dissipation ........................................................... 12W Short Circuit Output Current ..................................... 50mA DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (Notes: 1, 5, 6) (VCC = +5V ±10%) PARAMETER/CONDITION SYMBOL MIN MAX UNITS Supply Voltage VCC 4.5 5.5 V Input High (Logic 1) Voltage, all inputs VIH 2.4 5.5 V Input Low (Logic 0) Voltage, all inputs VIL -1.0 0.8 V NOTES INPUT LEAKAGE CURRENT RAS0#-RAS3# II1 -12 12 µA Any input 0V ≤ VIN ≤ 5.5V A0-A10, WE# II2 -48 48 µA 23 (All other pins not under test = 0V) CAS0#-CAS3# II3 -12 12 µA 23 OUTPUT LEAKAGE CURRENT (DQ is disabled; 0V ≤ VOUT ≤ 5.5V) DQ1-DQ36 IOZ -10 10 µA 23 VOH 2.4 OUTPUT LEVELS Output High Voltage (IOUT = -5mA) Output Low Voltage (IOUT = 4.2mA) V VOL 0.4 V MAX PARAMETER/CONDITION SYMBOL SIZE -6 UNITS NOTES STANDBY CURRENT: (TTL) (RAS# = CAS# = VIH) ICC1 16MB 32MB 22 44 mA STANDBY CURRENT: (CMOS) (RAS# = CAS# = other inputs = VCC -0.2V) ICC2 16MB 32MB 16 32 mA OPERATING CURRENT: Random READ/WRITE Average power supply current (RAS#, CAS#, address cycling: tRC = tRC [MIN]) ICC3 16MB 32MB 1,400 1,422 mA 3, 22 OPERATING CURRENT: FAST PAGE MODE Average power supply current (RAS# = VIL, CAS#, address cycling: tPC = tPC [MIN]) ICC4 16MB 32MB 1,040 1,062 mA 3, 22 REFRESH CURRENT: RAS#-ONLY Average power supply current (RAS# cycling, CAS# = VIH: tRC = tRC [MIN]) ICC5 16MB 32MB 1,400 1,422 mA 3, 22 REFRESH CURRENT: CBR Average power supply current (RAS#, CAS#, address cycling: tRC = tRC [MIN]) ICC6 16MB 32MB 1,400 1,422 mA 3, 4 4, 8 Meg x 36 Parity DRAM SIMMs DM45.pm5 – Rev. 3/97 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. „1997, Micron Technology, Inc. OBSOLETE 4, 8 MEG x 36 PARITY DRAM SIMMs CAPACITANCE MAX PARAMETER SYMBOL 16MB 32MB UNITS NOTES Input Capacitance: A0-A10 CI1 70 140 pF 2 Input Capacitance: WE# CI2 94 188 pF 2 Input Capacitance: RAS0#, RAS1#, RAS2#, RAS3# CI3 50 50 pF 2 Input Capacitance: CAS0#, CAS1#, CAS2#, CAS3# CI4 25 50 pF 2 Input/Output Capacitance: DQ1-DQ8, DQ10-DQ17, DQ19-DQ26, DQ28-DQ35 CIO1 10 18 pF 2 Input/Output Capacitance: DQ9, DQ18, DQ27, DQ36 CIO2 16 28 pF 2 AC ELECTRICAL CHARACTERISTICS (Notes: 5, 6, 7, 8, 9, 10, 11, 12) (VCC = +5V ±10%) AC CHARACTERISTICS PARAMETER Access time from column address Column-address hold time (referenced to RAS#) Column-address setup time Row-address setup time Access time from CAS# Column-address hold time CAS# pulse width CAS# hold time (CBR REFRESH) CAS# to output in Low-Z CAS# precharge time Access time from CAS# precharge CAS# to RAS# precharge time CAS# hold time CAS# setup time (CBR REFRESH) Write command to CAS# lead time Data-in hold time Data-in setup time Output buffer turn-off delay FAST-PAGE-MODE READ or WRITE cycle time Access time from RAS# RAS# to column-address delay time Row-address hold time RAS# pulse width RAS# pulse width (FAST PAGE MODE) Random READ or WRITE cycle time RAS# to CAS# delay time Read command hold time (referenced to CAS#) Read command setup time Refresh period (2,048 cycles) RAS# precharge time RAS# to CAS# precharge time 4, 8 Meg x 36 Parity DRAM SIMMs DM45.pm5 – Rev. 3/97 -6 SYMBOL tAA tAR tASC tASR tCAC tCAH tCAS tCHR tCLZ tCP tCPA tCRP tCSH tCSR tCWL tDH tDS tOFF tPC tRAC tRAD tRAH tRAS tRASP tRC tRCD tRCH tRCS tREF tRP tRPC 6 MIN MAX 30 45 0 0 15 10 15 15 3 10 10,000 35 10 60 10 15 10 0 3 35 15 60 15 10 60 60 110 20 0 0 10,000 125,000 32 40 0 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns NOTES 4 21 13 4 18 18 17, 21 15 14 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. „1997, Micron Technology, Inc. OBSOLETE 4, 8 MEG x 36 PARITY DRAM SIMMs AC ELECTRICAL CHARACTERISTICS (Notes: 5, 6, 7, 8, 9, 10, 11, 12) (VCC = +5V ±10%) AC CHARACTERISTICS PARAMETER Read command hold time (referenced to RAS#) RAS# hold time Write command to RAS# lead time Transition time (rise or fall) Write command hold time Write command hold time (referenced to RAS#) WE# command setup time Write command pulse width WE# hold time (CBR REFRESH) WE# setup time (CBR REFRESH) 4, 8 Meg x 36 Parity DRAM SIMMs DM45.pm5 – Rev. 3/97 -6 SYMBOL tRRH tRSH tRWL tT tWCH tWCR tWCS tWP tWRH tWRP 7 MIN 0 15 15 2 10 45 0 10 10 10 MAX 50 UNITS ns ns ns ns ns ns ns ns ns ns NOTES 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. „1997, Micron Technology, Inc. OBSOLETE 4, 8 MEG x 36 PARITY DRAM SIMMs NOTES 14. The tRCD (MAX) limit is no longer specified. tRCD (MAX) was specified as a reference point only. If tRCD was greater than the specified tRCD (MAX) limit, then access time was controlled exclusively by tCAC (tRAC [MIN] no longer applied). With or without the tRCD (MAX) limit, tAA and tCAC must always be met. 15. The tRAD (MAX) limit is no longer specified. tRAD (MAX) was specified as a reference point only. If tRAD was greater than the specified tRAD (MAX) limit, then access time was controlled exclusively by tAA (tRAC and tCAC no longer applied). With or without the tRAD (MAX) limit, tAA, tRAC and tCAC must always be met. 16. Either tRCH or tRRH must be satisfied for a READ cycle. 17. tOFF (MAX) defines the time at which the output achieves the open circuit condition and is not referenced to VOH or VOL. 18. These parameters are referenced to CAS# leading edge in EARLY WRITE cycles. 19. OE# is tied permanently LOW; LATE WRITE or READ-MODIFY-WRITE operations are not permissible and should not be attempted. 20. A HIDDEN REFRESH may also be performed after a WRITE cycle. In this case, WE# = LOW and OE# = HIGH. 21. The 3ns minimum is a parameter guaranteed by design. 22. Column address changed once each cycle. 23. 16MB module values will be half of those shown. 1. All voltages referenced to VSS. 2. This parameter is sampled. Capacitance is measured using MIL-STD-883C, Method 3012.1 (1 MHz AC, VCC = 4.5V, DC bias = 2.4V at 15mV RMS). 3. ICC is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open. 4. Enables on-chip refresh and address counters. 5. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range is ensured. 6. An initial pause of 100µs is required after power-up, followed by eight RAS# refresh cycles (RAS#-ONLY or CBR with WE# HIGH), before proper device operation is ensured. The eight RAS# cycle wake-ups should be repeated any time the tREF refresh requirement is exceeded. 7. AC characteristics assume tT = 5ns. 8. VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL (or between VIL and VIH). 9. In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 10. If CAS# = V IH, data output is High-Z. 11. If CAS# = V IL, data output may contain data from the last valid READ cycle. 12. Measured with a load equivalent to two TTL gates and 100pF, VOL = 0.8V and VOH = 2V. 13. If CAS# is LOW at the falling edge of RAS#, Q will be maintained from the previous cycle. To initiate a new cycle and clear the data-out buffer, CAS# must be pulsed HIGH for tCP. 4, 8 Meg x 36 Parity DRAM SIMMs DM45.pm5 – Rev. 3/97 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. „1997, Micron Technology, Inc. OBSOLETE 4, 8 MEG x 36 PARITY DRAM SIMMs READ CYCLE tRC tRP tRAS RAS# V IH V IL tCSH tRSH tRRH , , , , ,,,,,,, , ,,,,, , ,, , , ,, ,, ,, , tRCD tCRP CAS# tCAS V IH V IL tAR tRAD tASR ADDR V IH V IL tRAH tASC ROW tCAH ROW COLUMN tRCH tRCS WE# V IH V IL tAA tRAC tCAC tOFF tCLZ DQ V IOH V IOL OPEN OPEN VALID DATA , DON’T CARE UNDEFINED TIMING PARAMETERS -6 -6 SYMBOL tAA tAR tASC tASR MIN 45 0 0 tCAC tCAH tCAS tCLZ tCRP 15 10 15 3 tCSH 10 60 tOFF 3 4, 8 Meg x 36 Parity DRAM SIMMs DM45.pm5 – Rev. 3/97 MAX 30 10,000 15 SYMBOL UNITS ns ns ns MIN tRAC tRAD 15 tRAH 10 60 110 ns ns tRAS ns ns ns tRCD ns ns tRP ns tRC UNITS 60 ns ns 10,000 ns ns ns 20 0 ns ns tRRH 0 40 0 ns ns ns tRSH 15 ns tRCH tRCS 9 MAX Micron Technology, Inc., reserves the right to change products or specifications without notice. „1997, Micron Technology, Inc. OBSOLETE 4, 8 MEG x 36 PARITY DRAM SIMMs EARLY WRITE CYCLE tRC tRAS RAS# tRP V IH V IL tCSH tRSH , , , , , , ,, , , , , , , , , , , , ,,,, ,, ,,,,,,,,, ,, ,,, , , , ,, ,, tCRP CAS# tRCD tCAS V IH V IL tAR tRAD tASR ADDR V IH V IL tRAH tASC ROW tCAH ROW COLUMN tCWL tRWL tWCR tWCS tWCH tWP WE# V IH V IL tDH tDS V DQ V IOH IOL VALID DATA DON’T CARE UNDEFINED TIMING PARAMETERS -6 SYMBOL tAR tASC MIN 45 -6 MAX UNITS ns SYMBOL MIN MAX UNITS tRAH 10 60 110 10,000 ns ns ns 0 0 ns ns tRAS 10 15 10 ns ns ns tRCD 60 15 ns ns tRWL 10 0 ns ns tWCR tDS tRAD 15 ns tASR tCAH tCAS tCRP tCSH tCWL tDH 4, 8 Meg x 36 Parity DRAM SIMMs DM45.pm5 – Rev. 3/97 10,000 tRC 20 40 ns ns 15 15 10 ns ns ns tWCS 45 0 ns ns tWP 10 ns tRP tRSH tWCH 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. „1997, Micron Technology, Inc. OBSOLETE 4, 8 MEG x 36 PARITY DRAM SIMMs FAST-PAGE-MODE READ CYCLE tRASP V IH V IL RAS# tCSH tCRP CAS# tRP tRSH tPC tRCD tCAS tCP tCAS tCP tCAS tCP , , , , , , , , , , ,, ,,, ,, ,, , ,,,, , , , , , , , , , ,,,, , , ,,,, , V IH V IL tAR tRAD tASR ADDR V IH V IL tRAH tASC ROW tCAH COLUMN tASC COLUMN tCAH COLUMN tRCH ROW tRCS tRRH tRCH tRCH V IH V IL tAA tAA tRAC tCPA tCAC tOFF tCLZ DQ tCAH tRCS tRCS WE# tASC V IOH V IOL tCAC tAA tCPA tOFF tCLZ tOFF tCLZ VALID DATA OPEN tCAC VALID DATA VALID DATA OPEN DON’T CARE UNDEFINED TIMING PARAMETERS -6 SYMBOL tAA tAR tASC tASR MIN 45 0 0 tCAC 15 tCAH 10 tCAS 15 3 10 tCLZ tCP -6 MAX 30 tCPA 10,000 SYMBOL tOFF tPC tRAD tRAH ns ns ns tRCD tRP tCRP 10 tCSH 60 ns MIN 3 35 tRAC ns ns ns ns 4, 8 Meg x 36 Parity DRAM SIMMs DM45.pm5 – Rev. 3/97 35 UNITS ns ns ns ns tRASP UNITS ns ns 60 ns 125,000 ns ns ns 20 0 ns ns tRRH 0 40 0 ns ns ns tRSH 15 ns tRCH tRCS 11 15 10 60 MAX 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. „1997, Micron Technology, Inc. OBSOLETE 4, 8 MEG x 36 PARITY DRAM SIMMs FAST-PAGE-MODE EARLY-WRITE CYCLE tRP tRASP RAS# V IH V IL tCSH tPC , ,,,,, ,,,, ,,, , , , , , , , , , , , , ,, ,,, ,, ,, tCRP CAS# tRCD tCAS tCP tCAS tRSH tCP tCAS V IH V IL tAR tRAD tASR ADDR V IH V IL tRAH tASC ROW tCAH tASC COLUMN tCAH COLUMN tCWL tWCS tWCH tWCS tWCH tWCS tWP V DQ V IOH IOL tDS VALID DATA tDH VALID DATA tWCH tWP tWCR tDH ROW tCWL V IH V IL tDS , ,,,, , , , ,,,,, , tCAH COLUMN tCWL tWP WE# tASC tCP tDS tRWL tDH VALID DATA DON’T CARE , UNDEFINED TIMING PARAMETERS -6 SYMBOL tAR tASC tASR tCAH tCAS tCP tCRP tCSH tCWL tDH tDS tPC 4, 8 Meg x 36 Parity DRAM SIMMs DM45.pm5 – Rev. 3/97 MIN 45 0 0 -6 MAX UNITS ns ns ns SYMBOL tRAD tRAH tRASP ns ns tRCD 10 10 60 ns ns ns tRSH 15 10 ns ns tWCR 0 35 ns ns 10 15 10,000 MAX 125,000 UNITS ns ns ns 20 40 ns ns 15 15 10 ns ns ns tWCS 45 0 ns ns tWP 10 ns tRP tRWL tWCH 12 MIN 15 10 60 Micron Technology, Inc., reserves the right to change products or specifications without notice. „1997, Micron Technology, Inc. OBSOLETE 4, 8 MEG x 36 PARITY DRAM SIMMs FAST-PAGE-MODE READ-EARLY-WRITE CYCLE (Pseudo READ-MODIFY-WRITE) tRASP RAS# tRP V IH V IL tRSH tCSH tCRP CAS# tPC tRCD tCAS tCP tCAS tCP ,, ,, ,,, ,,,, , , , , , , , , ,, , , ,, , , , ,,, V IH V IL tAR tRAD tASR ADDR V IH V IL tASC tRAH ROW tASC tCAH COLUMN tCAH ROW COLUMN tCWL tRWL tRCS tWP tWCS WE# V IH V IL tCAC t CLZ DQ tWCH V OH V OL NOTE 1 t OFF tDS VALID DATA OPEN tDH VALID DATA tAA t RAC , DON’T CARE UNDEFINED TIMING PARAMETERS -6 SYMBOL MIN UNITS 30 ns ns ns tOFF ns ns tRAD ns ns ns tRASP 10 10 ns ns tRP 60 15 ns ns tRWL 10 0 ns ns tWCS tAA tAR tASC 45 0 tASR 0 tCAC tCAH tCAS tCLZ tCP tCRP tCSH tCWL tDH tDS -6 MAX 15 10 15 3 10,000 SYMBOL tPC MIN MAX UNITS 3 35 15 ns ns 60 ns ns ns 125,000 ns ns tRAC tRAH tRCD tRCS tRSH tWCH tWP 15 10 60 20 0 40 15 ns ns ns 15 10 ns ns 0 10 ns ns NOTE: 1. Do not drive data prior to tristate. 4, 8 Meg x 36 Parity DRAM SIMMs DM45.pm5 – Rev. 3/97 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. „1997, Micron Technology, Inc. OBSOLETE 4, 8 MEG x 36 PARITY DRAM SIMMs RAS#-ONLY REFRESH CYCLE (WE# = DON’T CARE) tRC tRAS V IH V IL ,, RAS# CAS# ADDR tCRP tRP , , , , ,, ,, ,, , tRPC V IH V IL tASR tRAH V IH V IL ROW V DQ V OH OL ROW OPEN CBR REFRESH CYCLE (Addresses = DON’T CARE) tRP RAS# tRAS tRP tRAS V IH V IL tRPC ,,,,,,,,,,,,,,,,,,, , , ,,, tCP CAS# V IH V IL DQ V OH V OL tCSR tCSR tCHR OPEN tWRP WE# tRPC tCHR tWRH tWRP tWRH V IH V IL , DON’T CARE UNDEFINED TIMING PARAMETERS -6 -6 SYMBOL tASR MIN MAX UNITS SYMBOL MIN MAX UNITS 60 110 40 10,000 ns ns ns 0 15 10 ns ns ns tRAS 10 10 ns ns tRPC tCSR tWRH 0 10 ns ns tRAH 10 ns tWRP 10 ns tCHR tCP tCRP 4, 8 Meg x 36 Parity DRAM SIMMs DM45.pm5 – Rev. 3/97 tRC tRP 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. „1997, Micron Technology, Inc. OBSOLETE 4, 8 MEG x 36 PARITY DRAM SIMMs HIDDEN REFRESH CYCLE 20 (WE# = HIGH) tRAS RAS# tRAS V IH V IL , , , , , , ,, , , , , , , ,, , , , , , , , , tCRP CAS# tRP tRSH tRCD tCHR V IH V IL tAR tRAD tASR ADDR V IH V IL tRAH tASC ROW tCAH COLUMN tAA tRAC tCAC tOFF tCLZ DQ V IOH V IOL OPEN VALID DATA OPEN , DON’T CARE UNDEFINED TIMING PARAMETERS -6 SYMBOL tAA tAR tASC tASR tCAC tCAH tCHR tCLZ tCRP 4, 8 Meg x 36 Parity DRAM SIMMs DM45.pm5 – Rev. 3/97 MIN -6 MAX 30 45 0 0 15 UNITS ns ns ns ns ns SYMBOL tOFF MIN MAX UNITS 3 15 60 ns ns ns 10,000 ns ns ns tRAC tRAD 15 tRAH 10 tRAS 10 15 ns ns tRCD tRP 60 20 40 3 10 ns ns tRSH 15 15 ns ns Micron Technology, Inc., reserves the right to change products or specifications without notice. „1997, Micron Technology, Inc. OBSOLETE 4, 8 MEG x 36 PARITY DRAM SIMMs 72-Pin SIMM (16MB) 4.260 (108.20) 4.240 (107.70) .200 (5.08) MAX 1.200 (30.48) 1.180 (29.97) .125 (3.18) TYP .400 (10.16) TYP .250 (6.35) .054 (1.37) .047 (1.19) 1.75 (44.45) TYP .080 (2.03) PIN 1 .250 (6.35) .050 (1.27) TYP .040 (1.02) TYP .133 (3.38) TYP 3.75 (95.25) 72-Pin SIMM (16MB) 4.260 (108.20) 4.240 (107.70) .350 (8.89) MAX 1.200 (30.48) 1.180 (29.97) .125 (3.18) TYP. .400 (10.16) TYP. .250 (6.35) .054 (1.37) .047 (1.19) 1.75 (44.45) TYP. .080 (2.03) PIN 1 .250 (6.35) .050 (1.27) TYP. .040 (1.02) TYP. .133 (3.38) TYP. 3.75 (95.25) NOTE: 1. All dimensions in inches (millimeters) 4, 8 Meg x 36 Parity DRAM SIMMs DM45.pm5 – Rev. 3/97 MAX or typical where noted. MIN 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. „1997, Micron Technology, Inc. OBSOLETE 4, 8 MEG x 36 PARITY DRAM SIMMs 72-Pin SIMM (32MB) FRONT VIEW 4.260 (108.20) 4.240 (107.70) .350 (8.98) MAX .133 (3.38) TYP .125 (3.18) TYP 1.010 (25.65) .990 (25.15) .400 (10.16) TYP .250 (6.35) 1.75 (44.45) TYP .080 (2.03) PIN 1 .250 (6.35) .050 (1.27) TYP .040 (1.02) TYP .235 (5.97) MIN .054 (1.37) .047 (1.19) 3.75 (95.25) BACK VIEW NOTE: 1. All dimensions in inches (millimeters) MAX or typical where noted. MIN 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: [email protected], Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron is a registered trademark of Micron Technology, Inc. 4, 8 Meg x 36 Parity DRAM SIMMs DM45.pm5 – Rev. 3/97 17 Micron Technology, Inc., reserves the right to change products or specifications without notice. „1997, Micron Technology, Inc.