MICRON MT4C16270

MT4C16270
256K x 16 DRAM
TECHNOLOGY, INC.
DRAM
256K x 16 DRAM
5V, EDO PAGE MODE
FEATURES
• Industry-standard x16 pinouts, timing, functions
and packages
• High-performance CMOS silicon-gate process
• Single +5V ±10% power supply*
• Low power, 3mW standby; 300mW active, typical
• All device pins are TTL-compatible
• 512-cycle refresh in 8ms (9 row- and 9 column
addresses)
• Refresh modes: RAS#-ONLY, CAS#-BEFORE-RAS#
(CBR) and HIDDEN
• Extended Data-Out (EDO) PAGE MODE access cycle
• BYTE WRITE and BYTE READ access cycles
OPTIONS
MARKING
• Timing
40ns access
50ns access
60ns access
-4*
-5*
-6
• Packages
Plastic SOJ (400 mil)
DJ
PIN ASSIGNMENT (Top View)
40-Pin SOJ
(DA-6)
Vcc
DQ1
DQ2
DQ3
DQ4
Vcc
DQ5
DQ6
DQ7
DQ8
NC
NC
WE#
RAS#
NC
A0
A1
A2
A3
Vcc
• Part Number Example: MT4C16270DJ-4
*40ns and 50ns access specifications are limited to a VCC range of ±5%.
Contact factory for availability.
KEY TIMING PARAMETERS
SPEED
-4
-5
-6
tRC
tRAC
tPC
tAA
tCAC
tCAS
tCP
75ns
100ns
110ns
40ns
50ns
60ns
15ns
20ns
25ns
20ns
25ns
30ns
12ns
15ns
15ns
6ns
8ns
10ns
6ns
8ns
10ns
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
Vss
DQ16
DQ15
DQ14
DQ13
Vss
DQ12
DQ11
DQ10
DQ9
NC
CASL#
CASH#
OE#
A8
A7
A6
A5
A4
Vss
GENERAL DESCRIPTION
The MT4C16270 is a randomly accessed solid-state
memory containing 4,194,304 bits organized in a x16 configuration. The MT4C16270 has both BYTE WRITE and
WORD WRITE access cycles via two CAS# pins.
The MT4C16270 CAS# function and timing are determined by the first CAS# (CASL# or CASH#) to transition
LOW and by the last to transition back HIGH. CASL# and
CASH# function in a similar manner to CAS# in that either
MT4C16270
W06.pm5 – Rev. 10/96
CASL# or CASH# will generate an internal CAS#. Use of
only one of the two results in a BYTE WRITE cycle. CASL#
transitioning LOW selects a WRITE cycle for the lower
byte (DQ1-DQ8) and CASH# transitioning LOW selects a
WRITE cycle for the upper byte (DQ9-DQ16). BYTE READ
cycles are achieved through CASL# or CASH# in the same
manner.
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1996, Micron Technology, Inc.
MT4C16270
256K x 16 DRAM
TECHNOLOGY, INC.
FUNCTIONAL BLOCK DIAGRAM
WE#
CASL#
CAS#
CASH#
CONTROL
LOGIC
DATA-IN BUFFER
DQ1
16
NO. 2 CLOCK
GENERATOR
9
A0
A1
A2
A3
A4
A5
A6
A7
A8
DATA-OUT
BUFFER
COLUMNADDRESS
BUFFER
9
COLUMN
DECODER
OE#
16
512
REFRESH
CONTROLLER
8
8
SENSE AMPLIFIERS
I/O GATING
REFRESH
COUNTER
512 x 16
ROWADDRESS
BUFFERS (9)
9
ROW
DECODER
9
9
RAS#
DQ16
NO. 1 CLOCK
GENERATOR
512
512 x 512 x 16
MEMORY
ARRAY
Vcc
Vss
FUNCTIONAL DESCRIPTION
Each bit is uniquely addressed through the 18 address
bits during READ or WRITE cycles. These are entered 9 bits
(A0 -A8) at a time. RAS# is used to latch the first 9 bits and
CAS# the latter 9 bits.
The CAS# control also determines whether the cycle will
be a refresh cycle (RAS#-ONLY) or an active cycle (READ,
WRITE or READ WRITE) once RAS# goes LOW. The
MT4C16270 has two CAS# controls, CASL# and CASH#.
The CASL# and CASH# inputs internally generate a
CAS# signal functioning in a similar manner to the single
CAS# input on the other 256K x 16 DRAMs. The key
difference is that each CAS# controls its corresponding DQ
tristate logic (in conjunction with OE# and WE# and RAS#).
CASL# controls DQ1 through DQ8 and CASH# controls
DQ9 through DQ16.
MT4C16270
W06.pm5 – Rev. 10/96
The MT4C16270 CAS# function is determined by the first
CAS# (CASL# or CASH# ) transitioning LOW and the last
transitioning back HIGH. The two CAS# controls give the
MT4C16270 both byte READ and byte WRITE cycle capabilities. (See Figure 2.)
A logic HIGH on WE# dictates READ mode while a logic
LOW on WE# dictates WRITE mode. During a WRITE
cycle, data-in (D) is latched by the falling edge of WE or
CAS# (CASL# or CASH#), whichever occurs last. An EARLY
WRITE occurs when WE is taken LOW prior to either CAS#
falling. A LATE WRITE or READ-MODIFY-WRITE occurs
when WE falls after CAS# (CASL# or CASH#) was taken
LOW. During EARLY WRITE cycles, the data-outputs (Q)
will remain High-Z regardless of the state of OE#. During
LATE WRITE or READ-MODIFY-WRITE cycles, OE# must
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1996, Micron Technology, Inc.
MT4C16270
256K x 16 DRAM
TECHNOLOGY, INC.
WORD WRITE
LOWER BYTE WRITE
RAS#
CASL#
CASH#
WE#
LOWER BYTE
(DQ1-DQ8)
OF WORD
UPPER BYTE
(DQ9-DQ16)
OF WORD
STORED
INPUT
INPUT
DATA
DATA
DATA
1
1
INPUT
INPUT
STORED
DATA
DATA
DATA
DATA
DATA
0
0
0
0
0
0
1
1
1
1
0
1
1
1
1
1
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
1
1
1
1
1
0
1
1
1
1
1
0
1
0
1
0
0
0
0
X
X
X
X
X
X
X
X
1
0
1
0
1
1
1
1
1
0
1
0
1
1
1
1
X
X
X
X
X
X
X
X
1
0
1
0
1
1
1
1
1
0
1
0
1
1
1
1
STORED STORED
ADDRESS 0
ADDRESS 1
X = NOT EFFECTIVE (DON’T CARE)
Figure 1
WORD AND BYTE WRITE EXAMPLE
WORD READ
LOWER BYTE READ
RAS#
CASL#
CASH#
WE#
LOWER BYTE
(DQ1-DQ8)
OF WORD
UPPER BYTE
(DQ9-DQ16)
OF WORD
STORED
DATA
1
1
0
OUTPUT
DATA
1
1
0
OUTPUT
DATA
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
Z
1
0
1
Z
Z
Z
0
0
0
0
Z
Z
Z
Z
1
1
0
STORED STORED
DATA
DATA
1
1
1
1
0
0
1
1
OUTPUT
DATA
1
1
0
OUTPUT
DATA
1
1
0
STORED
DATA
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
Z
Z
0
1
0
1
1
0
1
1
0
1
Z
Z
Z
Z
Z
Z
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
Z
Z
Z
Z
Z
Z
Z
Z
0
0
0
0
ADDRESS 0
ADDRESS 1
Z = High-Z
Figure 2
WORD AND BYTE READ EXAMPLE
MT4C16270
W06.pm5 – Rev. 10/96
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1996, Micron Technology, Inc.
MT4C16270
256K x 16 DRAM
TECHNOLOGY, INC.
FUNCTIONAL DESCRIPTION (continued)
be taken HIGH to disable the data-outputs prior to applying input data. If a LATE WRITE or READ-MODIFYWRITE is attempted while keeping OE# LOW, no write will
occur, and the data-outputs will drive read data from the
accessed location.
Additionally, both bytes must always be of the same
mode of operation if both bytes are active. A CAS# precharge
must be satisfied prior to changing modes of operation
between the upper and lower bytes. For example, an EARLY
WRITE on one byte and a LATE WRITE on the other byte is
not allowed during the same cycle. However, an EARLY
WRITE on one byte and, after a CAS# precharge has been
satisfied, a LATE WRITE on the other byte is permissable.
The 16 data inputs and 16 data outputs are routed through
16 pins using common I/O, and pin direction is controlled
by OE#, WE# and RAS#.
EDO PAGE MODE operations allow faster data operations (READ, WRITE or READ-MODIFY-WRITE) within a
RAS#
CASL#/CASH#
ADDR
row-address-defined (A0 -A8) page boundary. The EDO
PAGE MODE cycle is always initiated with a row address
strobed-in by RAS# followed by a column address
strobed-in by CAS#. CAS# may be toggled by holding
RAS# LOW and strobing-in different column-addresses,
thus executing faster memory cycles. Returning RAS# HIGH
terminates the EDO PAGE MODE operation.
BYTE ACCESS CYCLE
The BYTE WRITE cycle is determined by the use of
CASL# and CASH#. Enabling CASL# will select a lower
BYTE WRITE cycle (DQ1-DQ8) while enabling CASH# will
select an upper BYTE WRITE cycle (DQ9-DQ16). Enabling
both CASL# and CASH# selects a WORD WRITE cycle.
The MT4C16270 can be viewed as two 256K x 8 DRAMs
which have common input controls. Figure 1 illustrates the
MT4C16270 BYTE WRITE and WORD WRITE cycles. The
BYTE READ is accomplished in the same manner.
V IH
V IL
V IH
V IL
V IH
V IL
DQ V IOH
V IOL
ROW
COLUMN (A)
OPEN
COLUMN (B)
VALID DATA (A)
VALID DATA (A)
OE#
VALID DATA (D)
t OD
t OD
t OES
COLUMN (D)
VALID DATA (C)
VALID DATA (B)
t OD
V IH
V IL
COLUMN (C)
t OEHC
t OE
t OEP
The DQs go back to
Low-Z if tOES is met.
The DQs remain High-Z
until the next CAS# cycle
if tOEHC is met.
The DQs remain High-Z
until the next CAS# cycle
if tOEP is met.
DON’T CARE
UNDEFINED
Figure 3
OUTPUT ENABLE AND DISABLE
MT4C16270
W06.pm5 – Rev. 10/96
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1996, Micron Technology, Inc.
MT4C16270
256K x 16 DRAM
TECHNOLOGY, INC.
EDO PAGE MODE
DRAM READ cycles have traditionally turned the output buffers off (High-Z) with the rising edge of CAS#. If
CAS# goes HIGH, and OE# is LOW (active), the output
buffers will be disabled. The MT4C16270 offers an accelerated PAGE MODE cycle by eliminating output disable from
CAS# HIGH. This option is called EDO and it allows CAS#
precharge time (tCP) to occur without the output data going
invalid (see READ and EDO-PAGE-MODE READ waveforms).
EDO operates as any DRAM READ or FAST-PAGEMODE READ, except data will be held valid after CAS#
goes HIGH, as long as RAS# and OE# are held LOW and
WE# is held HIGH. OE# can be brought LOW or HIGH
while CAS# and RAS# are LOW, and the DQs will transition between valid data and High-Z. Using OE#, there are
two methods to disable the outputs and keep them disabled
during the CAS# HIGH time. The first method is to have
OE# HIGH when CAS# transitions HIGH and keep OE#
HIGH for tOEHC. This will tristate the DQs and they will
remain tristate, regardless of OE#, until CAS# falls again.
The second method is to have OE# LOW when CAS#
RAS#
CASL#/CASH#
ADDR
transitions HIGH. Then OE# can pulse HIGH for a minimum of tOEP anytime during the CAS# HIGH period and
the DQs will tristate and remain tristate, regardless of OE#,
until CAS# falls again (please reference Figure 3 for further
detail on the toggling OE# condition). During other cycles,
the outputs are disabled at tOFF time after RAS# and CAS#
are HIGH, or tWHZ after WE# transitions LOW. The tOFF
time is referenced from the rising edge of RAS# or CAS#,
whichever occurs last. WE# can also perform the function
of turning off the output drivers under certain conditions,
as shown in Figure 4.
Returning RAS# and CAS# HIGH terminates a memory
cycle and decreases chip current to a reduced standby level.
The chip is also preconditioned for the next cycle during the
RAS# HIGH time. Memory cell data is retained in its correct
state by maintaining power and executing any RAS# cycle
(READ, WRITE) or RAS# refresh cycle (RAS#-ONLY, CBR,
or HIDDEN) so that all 512 combinations of RAS# addresses (A0-A8) are executed at least every 8ms, regardless
of sequence. The CBR REFRESH cycle will also invoke the
refresh counter and controller for row address control.
V IH
V IL
V IH
V IL
V IH
V IL
DQ V IOH
V IOL
ROW
COLUMN (A)
OPEN
COLUMN (B)
VALID DATA (A)
VALID DATA (B)
t
WE#
V IH
V IL
OE#
V IH
V IL
COLUMN (C)
INPUT DATA (C)
t
WHZ
COLUMN (D)
WHZ
t WPZ
The DQs go to High-Z if WE# falls, and if tWPZ is met,
will remain High-Z until CAS# goes LOW with
WE# HIGH (i.e., until a READ cycle is initiated).
WE# may be used to disable the DQs to prepare
for input data in an EARLY WRITE cycle. The DQs
will remain High-Z until CAS# goes LOW with
WE# HIGH (i.e., until a READ cycle is initiated).
DON’T CARE
UNDEFINED
Figure 4
OUTPUT ENABLE AND DISABLE WITH WE#
MT4C16270
W06.pm5 – Rev. 10/96
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1996, Micron Technology, Inc.
MT4C16270
256K x 16 DRAM
TECHNOLOGY, INC.
TRUTH TABLE
ADDRESSES
RAS#
CASL#
CASH#
WE#
OE#
tR
tC
DQs
Standby
H
H→X
H→X
X
X
X
X
High-Z
READ: WORD
L
L
L
H
L
ROW
COL
Data-Out
READ: LOWER BYTE
L
L
H
H
L
ROW
COL
Lower Byte, Data-Out
Upper Byte, High-Z
READ: UPPER BYTE
L
H
L
H
L
ROW
COL
Lower Byte, High-Z
Upper Byte, Data Out
WRITE: WORD
(EARLY WRITE)
L
L
L
L
X
ROW
COL
Data-In
WRITE: LOWER
BYTE (EARLY)
L
L
H
L
X
ROW
COL
Lower Byte, Data-In
Upper Byte, High-Z
WRITE: UPPER
BYTE (EARLY)
L
H
L
L
X
ROW
COL
Lower Byte, High-Z
Upper Byte, Data-In
READ WRITE
L
L
L
H→L
L→H
ROW
COL
Data-Out, Data-In
1, 2
FUNCTION
NOTES
EDO-PAGE-
1st Cycle
L
H→L
H→L
H
L
ROW
COL
Data-Out
2
MODE READ
2nd Cycle
L
H→L
H→L
H
L
n/a
COL
Data-Out
2
Any Cycle
L
L→H
L→H
H
L
n/a
n/a
Data-Out
2
EDO-PAGE-
1st Cycle
L
H→L
H→L
L
X
ROW
COL
Data-In
1
MODE WRITE 2nd Cycle
L
H→L
H→L
L
X
n/a
COL
Data-In
1
EDO-
L
H→L
H→L
H→L
L→H
ROW
COL
Data-Out, Data-In
1, 2
L
H→L
H→L
H→L
L→H
n/a
COL
Data-Out, Data-In
1, 2
1st Cycle
PAGE-MODE 2nd Cycle
READ-WRITE
HIDDEN
READ
L→H→L
L
L
H
L
ROW
COL
Data-Out
2
REFRESH
WRITE
L→H→L
L
L
L
X
ROW
COL
Data-In
1, 3
L
H
H
X
X
ROW
n/a
High-Z
H→L
L
L
X
X
X
X
High-Z
RAS#-ONLY REFRESH
CBR REFRESH
NOTE:
4
1. These WRITE cycles may also be BYTE WRITE cycles (either CASL# or CASH# active).
2. These READ cycles may also be BYTE READ cycles (either CASL# or CASH# active).
3. EARLY WRITE only.
4. At least one of the two CAS# signals must be active (CASL# or CASH#).
MT4C16270
W06.pm5 – Rev. 10/96
6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1996, Micron Technology, Inc.
MT4C16270
256K x 16 DRAM
TECHNOLOGY, INC.
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
ABSOLUTE MAXIMUM RATINGS*
Voltage on any pin Relative to VSS ..................... -1V to +7V
Operating Temperature, TA (ambient) .......... 0°C to +70°C
Storage Temperature (plastic) .................... -55°C to +150°C
Power Dissipation .......................................................... 1.2W
Short Circuit Output Current ..................................... 50mA
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(Notes: 1, 6, 7) (VCC = +5V ±10%)**
PARAMETER/CONDITION
SYMBOL
MIN
MAX
UNITS
VCC**
4.5
5.5
V
Input High (Logic 1) Voltage, all inputs
VIH
2.4
VCC+1
V
Input Low (Logic 0) Voltage, all inputs
VIL
-1.0
0.8
V
II
-2
2
µA
OUTPUT LEAKAGE CURRENT (Q is disabled; 0V ≤ VOUT ≤ VCC)
IOZ
-10
10
µA
OUTPUT LEVELS
Output High Voltage (IOUT = -2.5mA)
Output Low Voltage (IOUT = 2.1mA)
VOH
2.4
Supply Voltage
INPUT LEAKAGE CURRENT
Any input 0V ≤ VIN ≤ VCC +1.0V
(All other pins not under test = 0V)
NOTES
3
V
VOL
0.4
V
SYMBOL
-4
MAX
-5
STANDBY CURRENT: (TTL)
(RAS# = CAS# = VIH)
ICC1
2
2
2
mA
STANDBY CURRENT: (CMOS)
(RAS# = CAS# = VCC -0.2V)
ICC2
1
1
1
mA
25
ICC3
205
195
185
mA
4, 40
ICC4
125
120
115
mA
4, 40
REFRESH CURRENT: RAS#-ONLY
Average power supply current
(RAS# cycling, CAS#=VIH: tRC = tRC [MIN])
ICC5
205
195
185
mA
4
REFRESH CURRENT: CBR
Average power supply current
(RAS#, CAS#, address cycling: tRC = tRC [MIN])
ICC6
180
170
160
mA
4, 5
PARAMETER/CONDITIONS
OPERATING CURRENT: Random READ/WRITE
Average power supply current
(RAS#, CAS#, address cycling: tRC = tRC [MIN])
OPERATING CURRENT: EDO PAGE MODE
Average power supply current
(RAS# = VIL, CAS#, address cycling:
tPC = tPC [MIN]; tCP, tASC = 10ns)
-6
UNITS
NOTES
**40 and 50ns specifications are limited to a VCC range of ±5%.
MT4C16270
W06.pm5 – Rev. 10/96
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1996, Micron Technology, Inc.
MT4C16270
256K x 16 DRAM
TECHNOLOGY, INC.
CAPACITANCE
PARAMETER
SYMBOL
MAX
UNITS
NOTES
Input Capacitance: A0-A8
CI1
5
pF
2
Input Capacitance: RAS#, CASL#, CASH#, WE#, OE#
CI2
7
pF
2
Input/Output Capacitance: DQ
CIO
7
pF
2
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9, 10, 11, 12, 13) (VCC = +5V ±10%)*
AC CHARACTERISTICS
PARAMETER
Access time from column-address
Column-address setup to CAS#
precharge during WRITE
Column-address hold time (referenced to RAS#)
Column-address setup time
Row-address setup time
Column-address to WE# delay time
Access time from CAS#
Column-address hold time
CAS# pulse width
CAS# hold time (CBR REFRESH)
Last CAS# going LOW to first CAS#
returning HIGH
CAS# to output in Low-Z
Data output hold after CAS# LOW
CAS# precharge time
Access time from CAS# precharge
CAS# to RAS# precharge time
CAS# hold time
CAS# setup time (CBR REFRESH)
CAS# to WE# delay time
Write command to CAS# lead time
Data-in hold time
Data-in setup time
Output disable time
Output Enable time
OE# hold time from WE# during
READ-MODIFY-WRITE cycle
OE# HIGH hold time from CAS# HIGH
OE# HIGH pulse width
OE# LOW to CAS# HIGH setup time
Output buffer turn-off delay from
CAS# or RAS#
-4
-5
MIN
15
15
15
tAR
30
0
0
37
40
0
0
48
40
0
0
55
tASC
tASR
tAWD
tCAC
tCAH
tCAS
tCHR
tCLCH
tCLZ
MAX
20
MIN
-6
SYM
tAA
tACH
12
7
6
10
10
MIN
15
8
8
10
10
10,000
15
10
10
10
10
10,000
ns
ns
ns
ns
ns
ns
ns
ns
ns
6
10
15
tOEHC
10
10
5
3
10
10
5
3
10
10
5
3
ns
ns
ns
ns
tCRP
tCSH
tCSR
tCWD
tCWL
tDH
tDS
tOD
tOE
tOEP
tOES
tOFF
3
3
10
UNITS
ns
ns
tOEH
tCP
tCPA
3
3
8
MAX
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCOH
3
3
6
25
5
37
10
30
7
7
0
3
10,000
MAX
25
28
15
10
15
5
40
10
35
8
8
0
3
15
15
15
35
5
45
10
40
10
10
0
3
15
15
15
NOTES
29
21
15, 31
29
37
5, 30
32
31, 41
16, 34
31
30
30
5, 29
21, 29
26, 30
22, 31
22, 31
28, 39, 41
23, 31
27
20, 28,
31, 41
*40ns and 50ns specifications are limited to a VCC range of ±5%.
MT4C16270
W06.pm5 – Rev. 10/96
8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1996, Micron Technology, Inc.
MT4C16270
256K x 16 DRAM
TECHNOLOGY, INC.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9, 10, 11, 12, 13) (Vcc = +5V ±10%)*
AC CHARACTERISTICS
PARAMETER
OE# setup prior to RAS# during
HIDDEN REFRESH cycle
EDO-PAGE-MODE READ or WRITE cycle time
EDO-PAGE-MODE READ-WRITE cycle time
Access time from RAS#
RAS# to column-address delay time
Row-address hold time
Column-address to RAS# lead time
RAS# pulse width
RAS# pulse width (EDO PAGE MODE)
Random READ or WRITE cycle time
RAS# to CAS# delay time
Read command hold time (referenced to CAS#)
Read command setup time
Refresh period (512 cycles)
RAS# precharge time
RAS# to CAS# precharge time
Read command hold time (referenced to RAS#)
RAS# hold time
READ WRITE cycle time
RAS# to WE# delay time
Write command to RAS# lead time
Transition time (rise or fall)
Write command hold time
Write command hold time (referenced to RAS#)
Write command setup time
Output disable delay from WE#
Write command pulse width
WE# pulse widths to disable outputs
WE# hold time (CBR REFRESH)
WE# setup time (CBR REFRESH)
-4
SYM
tORD
MIN
0
tPC
15
60
tPRWC
tRAC
tRAD
tRAH
tRAL
tRAS
tRASP
tRC
tRCD
tRCH
tRCS
tRPC
tRRH
tRSH
tRWC
tRWD
tRWL
tT
tWCH
tWCR
tWCS
tWHZ
tWP
tWPZ
tWRH
tWRP
MIN
0
10,000
100,000
50
13
MIN
0
10,000
100,000
60
15
10
22
60
60
110
20
0
0
8
30
10
0
8
126
69
8
2
8
40
0
3
8
10
10
10
MAX
25
72
50
13
10
17
50
50
100
18
0
0
8
25
10
0
7
105
60
7
1
7
30
0
3
7
10
10
10
-6
MAX
20
65
40
7
7
15
40
40
70
17
0
0
tREF
tRP
-5
MAX
50
13
10,000
100,000
8
35
10
0
10
140
85
10
2
10
40
0
3
10
10
10
10
50
15
UNITS
ns
NOTES
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
33
33
14
18
17, 29
19, 26, 30
26, 29
19
38
21
26
9, 10
26, 38
26
21, 26, 29
26
*40ns and 50ns specifications are limited to a VCC range of ±5%.
MT4C16270
W06.pm5 – Rev. 10/96
9
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1996, Micron Technology, Inc.
MT4C16270
256K x 16 DRAM
TECHNOLOGY, INC.
NOTES
18. The tRAD (MAX) limit is no longer specified. tRAD
(MAX) was specified as a reference point only. If
tRAD was greater than the specified tRAD (MAX)
limit, then access time was controlled exclusively by
tAA [tRAC (MIN) and tCAC (MIN) no longer
applied]. With or without the tRAD (MAX) limit, tAA
(MIN), tRAC (MIN) and tCAC (MIN) must always be
met.
19. Either tRCH or tRRH must be satisfied for a READ
cycle.
20. tOFF (MAX) defines the time at which the output
achieves the open circuit condition; it is not a
reference to VOH or VOL.
21. tWCS, tRWD, tAWD and tCWD are restrictive
operating parameters in LATE WRITE and READMODIFY-WRITE cycles only. If tWCS ≥ tWCS (MIN),
the cycle is an EARLY WRITE cycle and the data
output will remain an open circuit throughout the
entire cycle. If tRWD ≥ tRWD (MIN), tAWD ≥ tAWD
(MIN) and tCWD ≥ tCWD (MIN), the cycle is a
READ-WRITE and the data output will contain data
read from the selected cell. If neither of the above
conditions is met, the state of Q (at access time and
until CAS# and RAS# or OE# go back to V IH) is
indeterminate. OE# held HIGH and WE# taken LOW
after CAS# goes LOW result in a LATE WRITE (OE#controlled) cycle.
22. These parameters are referenced to CAS# leading
edge in EARLY WRITE cycles and WE# leading edge
in LATE WRITE or READ-MODIFY-WRITE cycles.
23. During a READ cycle, if OE# is LOW then taken
HIGH before CAS# goes HIGH, Q goes open. If OE#
is tied permanently LOW, a LATE WRITE or READMODIFY-WRITE operation is not possible.
24. A HIDDEN REFRESH may also be performed after a
WRITE cycle. In this case, WE# = LOW and OE# =
HIGH.
25. All other inputs at VCC -0.2V.
26. Write command is defined as WE# going LOW.
27. LATE WRITE and READ-MODIFY-WRITE cycles
must have both tOD and tOEH met (OE# HIGH
during WRITE cycle) in order to ensure that the
output buffers will be open during the WRITE cycle.
The DQs will provide the previously written data if
CAS# remains LOW and OE# is taken back LOW
after tOEH is met.
1. All voltages referenced to VSS.
2. This parameter is sampled. VCC = 4.75V; f = 1 MHz.
3. NC pins are assumed to be left floating and are not
tested for leakage.
4. ICC is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle
time and the output open.
5. Enables on-chip refresh and address counters.
6. The minimum specifications are used only to indicate
cycle time at which proper operation over the full
temperature range (0°C ≤ TA ≤ 70°C) is assured.
7. An initial pause of 100µs is required after power-up
followed by eight RAS# refresh cycles (RAS#-ONLY
or CBR) before proper device operation is assured.
The eight RAS# cycle wake-ups should be repeated
any time the tREF refresh requirement is exceeded.
8. AC characteristics assume tT = 2ns.
9. VIH (MIN) and VIL (MAX) are reference levels for
measuring timing of input signals. Transition times
are measured between VIH and VIL (or between VIL
and VIH).
10. In addition to meeting the transition rate specification, all input signals must transit between VIH and
VIL (or between VIL and VIH) in a monotonic manner.
11. If CAS# and RAS# = V IH, data output is High-Z.
12. If CAS# = V IL, data output may contain data from the
last valid READ cycle.
13. Measured with a load equivalent to one TTL gate and
50pF, VOL = 0.8V and VOH = 2.0V.
14. Assumes that tRCD < tRCD (MAX). If tRCD is greater
than the maximum recommended value shown in this
table, tRAC will increase by the amount that tRCD
exceeds the value shown.
15. Assumes that tRCD ≥ tRCD (MAX).
16. If CAS# is LOW at the falling edge of RAS#, Q will be
maintained from the previous cycle. To initiate a new
cycle and clear the Q buffer, CAS# and RAS# must be
pulsed HIGH for tCP.
17. The tRCD (MAX) limit is no longer specified. tRCD
(MAX) was specified as a reference point only. If
tRCD was greater than the specified tRCD (MAX)
limit, then access time was controlled exclusively by
tCAC [tRAC (MIN) no longer applied]. With or
without the tRCD (MAX) limit, tAA (MIN), tRAC
(MIN) and tCAC (MIN) must always be met.
MT4C16270
W06.pm5 – Rev. 10/96
10
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1996, Micron Technology, Inc.
MT4C16270
256K x 16 DRAM
TECHNOLOGY, INC.
NOTES (continued)
28. The DQs open during READ cycles once tOD or tOFF
occur.
29. The first CAS#x edge to transition LOW.
30. The last CAS#x edge to transition HIGH.
31. Output parameter (DQx) is referenced to corresponding CAS# input, DQ1-DQ8 by CASL# and DQ9-DQ16
by CASH#.
32. Last falling CAS#x edge to first rising CAS#x edge.
33. Last rising CAS#x edge to next cycle’s last rising
CAS#x edge.
MT4C16270
W06.pm5 – Rev. 10/96
34. Last rising CAS#x edge to first falling CAS#x edge.
35. First DQs controlled by the first CAS#x to go LOW.
36. Last DQs controlled by the last CAS#x to go HIGH.
37. Each CAS#x must meet minimum pulse width.
38. Last CAS#x to go LOW.
39. All DQs controlled, regardless CASL# and CASH#.
40. Column address changed once each cycle.
41. The 3ns minimum is a parameter guaranteed by
design.
11
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1996, Micron Technology, Inc.
MT4C16270
256K x 16 DRAM
TECHNOLOGY, INC.
READ CYCLE
tRC
tRP
tRAS
RAS#
V IH
V IL
tCSH
tRRH
tRSH
tRCD
tCRP
CASH#/CASL#
tCAS
tCLCH
V IH
V IL
tAR
tRAD
tASR
ADDR
tRAL
tRAH
V IH
V IL
tASC
ROW
tCAH
ROW
COLUMN
tRCH
tRCS
WE# V IH
V IL
tAA
tRAC
NOTE 1
tOFF
tCAC
tCLZ
DQ
V OH
V OL
OPEN
OE#
OPEN
VALID DATA
t OE
t OD
V IH
V IL
t OES
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-4
SYM
tAA
MIN
tAR
tASC
30
0
tASR
0
tCAC
7
tCAS
6
10
tCLZ
tCRP
tCSH
tOD
MIN
-6
MAX
25
40
0
8
10
-4
MAX
30
0
15
8
10,000
MIN
40
0
0
12
tCAH
tCLCH
-5
MAX
20
15
10
10,000
10
10
10,000
SYM
tOFF
ns
ns
tRAC
tRAD
7
13
ns
ns
ns
tRAH
7
15
40
10
17
50
ns
ns
tRC
tRAL
tRAS
tRCD
MIN
3
-5
UNITS
ns
MAX
15
MIN
3
40
10,000
-6
MAX
15
MIN
3
MAX
15
UNITS
ns
60
15
ns
ns
10
22
60
ns
ns
ns
50
10,000
10,000
75
17
100
18
110
20
ns
ns
0
0
0
0
0
0
ns
ns
3
5
3
5
3
5
ns
ns
tRCH
37
3
40
3
40
3
tRP
15
ns
ns
tRRH
25
0
30
0
35
0
ns
ns
15
5
ns
ns
tRSH
8
10
15
ns
tOE
tOES
15
10
5
15
15
5
tRCS
NOTE: 1. tOFF is referenced from the rising edge of RAS# or CAS#, whichever occurs last.
MT4C16270
W06.pm5 – Rev. 10/96
12
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1996, Micron Technology, Inc.
MT4C16270
256K x 16 DRAM
TECHNOLOGY, INC.
EARLY WRITE CYCLE
tRC
tRAS
RAS#
tRP
V IH
V IL
tCSH
tRSH
tCRP
CASL#/CASH#
tRCD
tCAS
tCLCH
V IH
V IL
tAR
tRAD
tASR
tRAL
tRAH
tASC
tCAH
tACH
ADDR
V IH
V IL
ROW
ROW
COLUMN
tCWL
tRWL
tWCR
tWCS
tWCH
tWP
WE#
V IH
V IL
tDH
tDS
V
DQ V IOH
IOL
OE#
VALID DATA
V IH
V IL
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-4
SYM
tACH
tAR
tASC
tASR
tCAH
tCAS
tCLCH
tCRP
tCSH
tCWL
tDH
tDS
tRAD
MIN
15
-5
MAX
MIN
15
-6
MAX
MIN
15
-4
MAX
UNITS
ns
SYM
tRAH
MIN
7
15
40
30
0
0
40
0
0
40
0
0
ns
ns
ns
tRAL
7
6
8
8
10
10
ns
ns
tRCD
10,000
10,000
10,000
tRAS
tRC
tRP
10
5
10
5
10
5
ns
ns
tRSH
37
7
7
40
8
8
40
10
10
ns
ns
ns
tWCH
0
7
0
13
0
15
ns
ns
tWP
MT4C16270
W06.pm5 – Rev. 10/96
tRWL
tWCR
tWCS
13
-5
MAX
10,000
MIN
10
17
50
-6
MAX
10,000
MIN
10
22
60
MAX
10,000
UNITS
ns
ns
ns
75
17
25
100
18
30
110
20
35
ns
ns
ns
7
7
8
8
10
10
ns
ns
7
30
0
8
40
0
10
40
0
ns
ns
ns
7
8
10
ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1996, Micron Technology, Inc.
MT4C16270
256K x 16 DRAM
TECHNOLOGY, INC.
READ WRITE CYCLE
(LATE WRITE and READ-MODIFY-WRITE cycles)
tRWC
tRAS
RAS#
tRP
V IH
V IL
tCSH
tRSH
tCRP
CASL#/CASH#
tRCD
tCLCH
tCAS
V IH
V IL
tAR
tRAD
tASR
tRAL
tASC
tRAH
tCAH
tACH
ADDR
V IH
V IL
ROW
COLUMN
tRCS
WE#
ROW
tRWD
tCWL
tCWD
tRWL
tAWD
tWP
V IH
V IL
tAA
tRAC
tCAC
tDS
t CLZ
V
DQ V IOH
IOL
VALID D OUT
OPEN
tOE
OE#
tDH
VALID D IN
tOD
OPEN
tOEH
V IH
V IL
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-4
-5
SYM
tAA
MIN
tACH
15
30
15
40
0
0
37
0
0
48
tAR
tASC
tASR
tAWD
tCAC
7
tCAS
6
10
3
tCLZ
tCRP
MIN
12
tCAH
tCLCH
MAX
30
-6
MAX
25
8
10
3
-4
UNITS
ns
SYM
tOD
15
40
ns
ns
tOE
0
0
55
ns
ns
ns
tRAC
ns
ns
tRAL
ns
ns
ns
tRCD
15
8
10,000
MIN
MAX
30
15
10
10,000
10
10
3
10,000
tOEH
tRAD
tRAH
tRAS
tRCS
tRP
5
37
5
40
5
40
ns
ns
tRSH
35
8
8
40
10
10
ns
ns
ns
tRWD
tDH
30
7
7
tDS
0
0
0
ns
tCSH
tCWD
tCWL
MT4C16270
W06.pm5 – Rev. 10/96
tRWC
tRWL
tWP
14
MIN
3
-5
MAX
15
MIN
3
10
6
40
50
17
50
MAX
15
UNITS
ns
15
ns
ns
60
ns
ns
ns
15
13
10
10,000
MIN
3
15
10
7
7
15
40
-6
MAX
15
15
10
10,000
22
60
10,000
ns
ns
17
0
25
18
0
30
20
0
35
ns
ns
ns
7
105
8
126
10
140
ns
ns
60
7
7
69
8
8
85
10
10
ns
ns
ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1996, Micron Technology, Inc.
MT4C16270
256K x 16 DRAM
TECHNOLOGY, INC.
EDO-PAGE-MODE READ CYCLE
tRASP
RAS#
V IH
V IL
tCSH
tCRP
CASH#/CASL#
tRP
tPC
tCAS, tCLCH
tRCD
(NOTE 1)
tCAS, tCLCH
tCP
tRSH
tCAS, tCLCH
tCP
tCP
V IH
V IL
tAR
tRAD
tASR
ADDR
V IH
V IL
tRAL
tRAH
tASC
tCAH
ROW
tASC
COLUMN
tCAH
tASC
COLUMN
tCAH
COLUMN
ROW
tRCS
WE#
V IH
V IL
tAA
tAA
tAA
tRAC
tCPA
tCPA
tCAC
tCAC
tCAC
tCOH
tCLZ
DQ
V OH
V OL
VALID
DATA
OPEN
tOFF
tCLZ
VALID
DATA
tOE
OE#
tRRH
tRCH
VALID
DATA
tOEHC
tOD
tOES
V IH
V IL
OPEN
tOE
tOD
tOES
tOEP
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-4
-5
30
40
40
UNITS
ns
ns
tASC
0
0
0
0
0
0
ns
ns
tOES
ns
ns
ns
tPC
tCAC
tCAH
tCAS
tCLCH
tCLZ
tCOH
tCP
12
tCSH
tOD
MAX
25
MIN
tOFF
MIN
10
10
5
3
-5
MAX
15
5
3
-6
MAX
15
5
3
MAX
15
ns
ns
tRAD
7
13
15
tRAH
7
15
10
17
10
22
ns
ns
3
6
3
8
3
10
ns
ns
ns
tRASP
ns
ns
tRCS
ns
ns
tRRH
25
5
37
3
tOE
28
5
40
15
10
3
35
5
40
15
15
3
15
15
tRAL
tRCD
tRCH
tRP
tRSH
40
40
17
0
100,000
25
UNITS
ns
ns
ns
ns
10,000
tRAC
20
MIN
10
10
10
3
10,000
10
10
15
MIN
10
10
10
3
8
8
15
SYM
tOEHC
tOEP
10
3
10,000
15
MAX
30
ns
ns
ns
7
6
tCPA
tCRP
MIN
-4
MIN
tASR
MAX
20
-6
SYM
tAA
tAR
50
50
18
0
100,000
60
60
20
0
100,000
ns
ns
ns
0
25
0
30
0
35
ns
ns
0
7
0
8
0
10
ns
ns
NOTE: 1. tPC can be measured from falling edge of CAS# to falling edge of CAS#, or from rising edge of CAS# to rising edge of CAS#. Both measurements
must meet the tPC specification.
MT4C16270
W06.pm5 – Rev. 10/96
15
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1996, Micron Technology, Inc.
MT4C16270
256K x 16 DRAM
TECHNOLOGY, INC.
EDO-PAGE-MODE EARLY-WRITE CYCLE
tRP
tRASP
RAS#
V IH
V IL
tCSH
tPC
tCRP
CASL#/CASH#
tCAS, tCLCH
tRCD
tCAS, tCLCH
tCP
tRSH
tCAS, tCLCH
tCP
V IH
V IL
tACH
tAR
tACH
tRAD
tASR
ADDR
V IH
V IL
tRAH
tASC
ROW
tACH
tCAH
tASC
COLUMN
tWCS
tCAH
tRAL
tCAH
tASC
COLUMN
tCWL
COLUMN
tCWL
tWCH
tWCS
tWP
WE#
ROW
tCWL
tWCH
tWCS
tWCH
tWP
tWP
V IH
V IL
tWCR
tDS
V
DQ V IOH
IOL
OE#
tCP
tDH
tDS
VALID DATA
tDH
tRWL
tDH
tDS
VALID DATA
VALID DATA
V IH
V IL
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-4
-5
SYM
MIN
tACH
15
30
0
15
40
0
0
7
6
0
8
8
tAR
tASC
tASR
tCAH
tCAS
tCLCH
tCP
tCRP
tCSH
tCWL
tDH
tDS
MAX
10,000
MIN
-6
MAX
10,000
MIN
-4
MAX
UNITS
SYM
MIN
15
40
0
ns
ns
ns
tPC
15
7
7
0
10
10
ns
ns
ns
tRAL
10,000
tRAD
tRAH
tRASP
tRCD
10
6
10
8
10
10
ns
ns
tRP
5
37
7
5
40
8
5
40
10
ns
ns
ns
tRWL
7
0
8
0
10
0
ns
ns
tWCS
MT4C16270
W06.pm5 – Rev. 10/96
tRSH
tWCH
tWCR
tWP
16
15
40
17
-5
MAX
MIN
-6
MAX
20
13
10
100,000
17
50
18
MIN
MAX
25
15
10
100,000
22
60
20
UNITS
ns
ns
ns
100,000
ns
ns
ns
25
7
30
8
35
10
ns
ns
7
7
30
8
8
40
10
10
40
ns
ns
ns
0
7
0
8
0
10
ns
ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1996, Micron Technology, Inc.
MT4C16270
256K x 16 DRAM
TECHNOLOGY, INC.
EDO-PAGE-MODE READ-WRITE CYCLE
(LATE WRITE and READ-MODIFY-WRITE cycles)
tRASP
tRP
V IH
V IL
RAS#
tCSH
tCRP
CAS#L/CASH#
tPRWC NOTE 1
t PC
tRCD
tCP
tCAS, tCLCH
tRSH
tCP
tCAS, tCLCH
tCP
tCAS, tCLCH
V IH
V IL
tAR
tRAD
tASR
V IH
V IL
ADDR
tRAL
tRAH
tASC
ROW
tCAH
tASC
COLUMN
tCAH
tASC
COLUMN
tCAH
COLUMN
ROW
tRWD
tRCS
WE#
tRWL
tCWL
tCWL
tWP
tAWD
tWP
tAWD
tAWD
tCWD
tCWD
tCWD
V IH
V IL
tAA
tAA
tRAC
tDH
tCPA
tDS
DQ
tCWL
tWP
V IOH
V IOL
tAA
tDH
tCAC
tCAC
tCAC
tCLZ
tCLZ
tCLZ
VALID
D OUT
OPEN
VALID
D OUT
VALID
D IN
tDS
VALID
D IN
VALID
D OUT
VALID
D IN
tOD
tOE
tDH
tCPA
tDS
tOD
tOD
tOE
tOE
OPEN
t OEH
V IH
V IL
OE#
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-4
-5
30
40
40
0
0
0
0
ns
ns
tOEH
tASR
0
0
tPC
6
15
tAWD
37
ns
ns
ns
tPRWC
60
tRAD
7
13
15
ns
ns
ns
ns
ns
tRAH
7
15
10
17
10
22
ns
ns
ns
ns
ns
tRASP
7
tCAS
6
10
tCLZ
tCP
tCSH
tCWD
tCWL
tDH
tDS
10,000
8
10
15
10
10,000
3
8
25
MAX
30
55
15
8
3
6
tCPA
tCRP
48
12
MIN
10
10
10,000
3
10
28
35
SYM
tOD
tOE
MIN
3
tRAC
tRAL
tRCD
tRCS
5
37
5
40
5
40
ns
ns
tRP
30
7
35
8
40
10
ns
ns
tRWD
7
0
8
0
10
0
ns
ns
tWP
tRSH
tRWL
MAX
15
10
MIN
3
-6
tASC
tCAH
MAX
25
-5
UNITS
ns
ns
tCLCH
MIN
-4
MIN
tCAC
MAX
20
-6
SYM
tAA
tAR
10
20
100,000
MIN
3
100,000
60
60
20
0
UNITS
ns
ns
ns
ns
72
50
50
18
0
MAX
15
15
15
25
65
40
40
17
0
MAX
15
15
100,000
ns
ns
ns
25
7
30
8
35
10
ns
ns
60
7
69
8
85
10
ns
ns
7
8
10
ns
NOTE: 1. tPC can be measured from falling edge to falling edge of CAS#, or from rising edge to rising edge of CAS#. Both measurements must meet the tPC
specification.
MT4C16270
W06.pm5 – Rev. 10/96
17
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1996, Micron Technology, Inc.
MT4C16270
256K x 16 DRAM
TECHNOLOGY, INC.
EDO-PAGE-MODE READ-EARLY-WRITE CYCLE
(Psuedo READ-MODIFY-WRITE)
t RP
t RASP
V IH
V IL
RAS#
t CSH
t PC
t CRP
t RCD
t CAS
t RSH
t PC
t CP
t CP
t CAS
t CAS
t CP
V IH
V IL
CASL#/CASH#
t ACH
t RAL
t AR
t RAD
tASR
V IH
V IL
ADDR
t RAH
t ASC
ROW
t CAH
t ASC
COLUMN (A)
t CAH
COLUMN (B)
V IH
V IL
t CAH
ROW
COLUMN (N)
t RCH
t RCS
WE#
t ASC
t WCS
t WCH
t AA
t AA
t WHZ
t CPA
t RAC
t CAC
t CAC
t DS
t DH
t COH
DQ V IOH
V IOL
OPEN
VALID
DATA (B)
VALID DATA (A)
VALID DATA
IN
t OE
V IH
V IL
OE#
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-4
-5
SYM
tAA
MIN
tACH
tASC
15
37
0
15
40
0
tASR
0
0
tAR
tCAC
tCAH
tCOH
tCP
6
tCPA
tCRP
tCSH
tDH
tDS
MIN
12
7
6
3
tCAS
MAX
20
10,000
-6
MAX
25
MIN
UNITS
ns
SYM
tOE
MIN
15
40
0
ns
ns
ns
tPC
15
0
ns
ns
tRAH
ns
ns
ns
tRASP
ns
ns
tRCS
15
8
8
3
10,000
8
25
-4
MAX
30
15
10
10
3
10,000
10
28
35
tRAC
tRAD
tRAL
tRCD
tRCH
tRP
5
37
5
40
5
40
ns
ns
tRSH
7
0
8
0
10
0
ns
ns
tWCS
MT4C16270
W06.pm5 – Rev. 10/96
tWCH
tWHZ
18
-5
MAX
10
MIN
20
40
7
7
15
40
17
-6
MAX
15
50
18
MAX
15
UNITS
ns
60
ns
ns
25
50
13
10
17
100,000
MIN
15
10
22
100,000
60
20
ns
ns
ns
100,000
ns
ns
0
0
25
0
0
30
0
0
35
ns
ns
ns
7
7
8
8
10
10
ns
ns
0
3
13
0
3
13
0
3
15
ns
ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1996, Micron Technology, Inc.
MT4C16270
256K x 16 DRAM
TECHNOLOGY, INC.
READ CYCLE
(with WE#-controlled disable)
V IH
V IL
RAS#
tCSH
tRCD
tCRP
tCAS
tCP
V IH
V IL
CASL#/CASH#
tAR
tRAD
tASR
V IH
V IL
ADDR
tRAH
ROW
tWRP
V IH
V IL
WE#
tASC
tCAH
tASC
COLUMN
tWRH
COLUMN
tRCS
tRCH
NOTE 1
tWPZ
tRCS
tAA
tRAC
tCAC
tWHZ
tCLZ
DQ
V OH
V OL
OPEN
VALID DATA
t OE
tCLZ
OPEN
t OD
V IH
V IL
OE#
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-4
-5
SYM
tAA
tAR
MIN
30
40
tASC
0
0
0
0
tASR
tCAC
tCAH
tCAS
tCLZ
tCP
tCRP
tCSH
tOD
MAX
20
MIN
12
7
6
10,000
-6
MAX
25
MIN
SYM
tOE
40
UNITS
ns
ns
0
0
ns
ns
tRAD
ns
ns
ns
tRCH
15
8
8
10,000
-4
MAX
30
15
10
10
10,000
tRAC
tRAH
tRCD
tRCS
3
6
3
8
3
10
ns
ns
tWHZ
5
37
5
40
5
40
ns
ns
tWRH
3
15
3
15
3
15
MIN
tWPZ
tWRP
-5
MAX
10
MIN
40
-6
MAX
15
MIN
UNITS
ns
60
7
7
13
10
15
10
ns
ns
ns
0
17
0
18
0
20
ns
ns
0
3
10
10
10
13
50
MAX
15
0
3
10
10
10
13
0
3
10
10
10
15
ns
ns
ns
ns
ns
ns
NOTE: 1. Although WE# is a “don’t care” at RAS# time during an access cycle (READ or WRITE), the system designer should implement WE# HIGH for tWRP
and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs.
MT4C16270
W06.pm5 – Rev. 10/96
19
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1996, Micron Technology, Inc.
MT4C16270
256K x 16 DRAM
TECHNOLOGY, INC.
RAS#-ONLY REFRESH CYCLE
(OE#, WE# = DON’T CARE)
tRC
tRAS
RAS#
tRP
V IH
V IL
tCRP
CASL#/CASH#
tRPC
V IH
V IL
tASR
ADDR
V IH
V IL
ROW
V
Q V OH
OL
WE#
tRAH
ROW
OPEN
tWRP
V IH
V IL
tWRP
tWRH
tWRH
NOTE 1
CBR REFRESH CYCLE
(Addresses; OE# = DON’T CARE)
tRP
RAS#
tRAS
tRP
tRAS
V IH
V IL
tRPC
tCP
CASH#, CASL#
V IH
V IL
DQ
V OH
V OL
WE#
tRPC
tCHR
tCSR
tCSR
tCHR
OPEN
V IH
V IL
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-4
SYM
tASR
tCHR
tCP
tCRP
tCSR
tRAH
MIN
0
10
-5
MAX
MIN
0
10
-6
MAX
MIN
0
10
-4
MAX
UNITS
ns
ns
SYM
tRAS
tRC
6
5
8
5
10
5
ns
ns
tRP
10
7
10
10
10
10
ns
ns
tWRH
tRPC
tWRP
MIN
40
-5
MAX
10,000
MIN
50
-6
MAX
10,000
MIN
60
MAX
10,000
UNITS
ns
75
25
10
100
30
10
110
35
10
ns
ns
ns
10
10
10
10
10
10
ns
ns
NOTE: 1. Although WE# is a “don’t care” at RAS# time during an access cycle (READ or WRITE), the system designer should implement WE# HIGH for tWRP
and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs.
MT4C16270
W06.pm5 – Rev. 10/96
20
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1996, Micron Technology, Inc.
MT4C16270
256K x 16 DRAM
TECHNOLOGY, INC.
HIDDEN REFRESH CYCLE 24
(WE# = HIGH; OE# = LOW)
tRAS
tRP
tRAS
V IH
V IL
RAS#
tCRP
CASL#/CASH#
tRSH
tRCD
tCHR
V IH
V IL
tAR
tRAD
tASR
V IH
V IL
ADDR
tRAH
tRAL
tCAH
tASC
ROW
COLUMN
tAA
tRAC
NOTE 1
tOFF
tCAC
tCLZ
DQx
V OH
V OL
OPEN
VALID DATA
OPEN
tOE
OE#
tOD
tORD
V IH
V IL
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-4
SYM
tAA
MIN
tAR
30
0
0
tASC
tASR
tCAC
tCAH
tCHR
tCLZ
tCRP
tOD
-5
MAX
20
MIN
-6
MAX
25
40
0
0
12
MIN
-4
MAX
30
UNITS
ns
SYM
tOFF
MIN
3
tORD
0
15
ns
ns
ns
ns
40
0
0
15
tRAC
tRAD
tRAH
7
10
8
10
10
10
ns
ns
tRAL
3
5
3
3
5
3
3
5
3
tRCD
15
ns
ns
ns
15
ns
tOE
15
10
15
15
tRAS
tRP
tRSH
-5
MAX
15
MIN
3
0
40
7
7
15
40
17
25
7
-6
MAX
15
17
50
18
30
8
MAX
15
0
50
13
10
10,000
MIN
3
60
15
10
10,000
22
60
20
35
10
10,000
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTE: 1. tOFF is referenced from the rising edge of RAS# or CAS#, whichever occurs last.
MT4C16270
W06.pm5 – Rev. 10/96
21
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1996, Micron Technology, Inc.
MT4C16270
256K x 16 DRAM
TECHNOLOGY, INC.
40-PIN PLASTIC SOJ (400 mil)
DA-6
1.029 (26.14)
1.023 (25.98)
.405 (10.29)
.399 (10.13)
.445 (11.30)
.435 (11.05)
PIN #1 INDEX
.050 (1.27) TYP
.950 (24.13)
.150 (3.81)
.138 (3.51)
.032 (0.81)
.026 (0.66)
.105 (2.67)
.090 (2.29)
SEATING PLANE
.020 (0.51)
.015 (0.38)
.037 (0.94) MAX
DAMBAR PROTRUSION
NOTE:
.380 (9.65)
.360 (9.14)
.025 (0.64)
MIN
1. All dimensions in inches (millimeters) MAX or typical where noted.
MIN
2. Package width and length do not include mold protrusion; allowable mold protrusion is .01" per side.
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900, Micron DataFax: 208-368-5800
E-mail: [email protected], Internet: http://www.micron.com, Customer Comment Line: 800-932-4992
MT4C16270
W06.pm5 – Rev. 10/96
22
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1996, Micron Technology, Inc.