TI SN74LV4052ADR

SN54LV4052A, SN74LV4052A
DUAL 4-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS
SCLS429H − MAY 1999 − REVISED APRIL 2005
D 2-V to 5.5-V VCC Operation
D Support Mixed-Mode Voltage Operation on
2Y0
2Y2
2-COM
2Y3
2Y1
INH
GND
GND
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VCC
1Y2
1Y1
1-COM
1Y0
1Y3
A
B
description/ordering information
These
dual
4-channel
CMOS
analog
multiplexers/demultiplexers are designed for 2-V
to 5.5-V VCC operation.
2Y2
2-COM
2Y3
2Y1
INH
GND
The ’LV4052A devices handle both analog and
digital signals. Each channel permits signals with
amplitudes up to 5.5 V (peak) to be transmitted in
either direction.
VCC
SN74LV4052A . . . RGY PACKAGE
(TOP VIEW)
1
16
15 1Y2
14 1Y1
2
3
5
13 1-COM
12 1Y0
6
11
7
10 A
4
9
GND
8
Applications include signal gating, chopping,
modulation or demodulation (modem), and signal
multiplexing for analog-to-digital and digital-toanalog conversion systems.
1Y3
B
D
All Ports
Fast Switching
High On-Off Output-Voltage Ratio
Low Crosstalk Between Switches
Extremely Low Input Current
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
2Y0
D
D
D
D
D
SN54LV4052A . . . J OR W PACKAGE
SN74LV4052A . . . D, DB, DGV, N, NS, OR PW PACKAGE
(TOP VIEW)
ORDERING INFORMATION
PDIP − N
QFN − RGY
†
SN74LV4052AN
SN74LV4052AN
SN74LV4052ARGYR
LW052A
SN74LV4052AD
Reel of 2500
SN74LV4052ADR
SOP − NS
Reel of 2000
SN74LV4052ANSR
74LV4052A
SSOP − DB
Reel of 2000
SN74LV4052ADBR
LW052A
Tube of 90
SN74LV4052APW
Reel of 2000
SN74LV4052APWR
Reel of 250
SN74LV4052APWT
TVSOP − DGV
Reel of 2000
SN74LV4052ADGVR
LW052A
CDIP − J
Tube of 25
SNJ54LV4052AJ
SNJ54LV4052AJ
CFP − W
Tube of 150
SNJ54LV4052AW
SNJ54LV4052AW
TSSOP − PW
−55°C
55°C to 125°C
Tube of 25
Reel of 1000
TOP-SIDE
MARKING
Tube of 40
SOIC − D
−40°C
40°C to 85°C
ORDERABLE
PART NUMBER
PACKAGE†
TA
LV4052A
LW052A
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 2005, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN54LV4052A, SN74LV4052A
DUAL 4-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS
SCLS429H − MAY 1999 − REVISED APRIL 2005
FUNCTION TABLE
INPUTS
A
ON
CHANNEL
L
L
1Y0, 2Y0
L
H
1Y1, 2Y1
L
H
L
1Y2, 2Y2
L
H
H
1Y3, 2Y3
H
X
X
None
INH
B
L
L
logic diagram (positive logic)
13
12
A
14
9
11
1
5
2
INH
6
4
3
2
1Y0
10
15
B
1-COM
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1Y1
1Y2
1Y3
2Y0
2Y1
2Y2
2Y3
2-COM
SN54LV4052A, SN74LV4052A
DUAL 4-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS
SCLS429H − MAY 1999 − REVISED APRIL 2005
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7.0 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7.0 V
Switch I/O voltage range, VIO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA
I/O diode current, IIOK (VIO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Switch through current, IT (VIO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
(see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W
(see Note 3): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W
(see Note 3): N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
(see Note 3): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
(see Note 3): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
(see Note 4): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
4. The package thermal impedance is calculated in accordance with JESD 51-5.
recommended operating conditions (see Note 5)
SN54LV4052A
VCC
Supply voltage
VCC = 2 V
VIH
High-level
High
level input voltage,
control inputs
MIN
MAX
MIN
MAX
2‡
5.5
2‡
5.5
1.5
1.5
VCC = 2.3 V to 2.7 V
VCC × 0.7
VCC × 0.7
VCC = 3 V to 3.6 V
VCC × 0.7
VCC × 0.7
VCC = 4.5 V to 5.5 V
VCC × 0.7
VCC × 0.7
VCC = 2 V
VIL
Low-level
Low
level input voltage,
control inputs
VI
Control input voltage
VIO
Input/output voltage
0.5
Input transition rise or fall rate
VCC × 0.3
VCC = 3 V to 3.6 V
VCC × 0.3
VCC × 0.3
VCC × 0.3
V
VCC × 0.3
0
5.5
0
5.5
V
0
VCC
0
VCC
V
VCC = 2.3 V to 2.7 V
200
200
VCC = 3 V to 3.6 V
100
100
20
20
Operating free-air temperature
V
0.5
VCC × 0.3
VCC = 4.5 V to 5.5 V
TA
UNIT
V
VCC = 2.3 V to 2.7 V
VCC = 4.5 V to 5.5 V
Δt/Δv
SN74LV4052A
−55
125
−40
85
ns/V
°C
‡
With supply voltages at or near 2 V, the analog switch on-state resistance becomes very nonlinear. It is recommended that only digital signals
be transmitted at these low supply voltages.
NOTE 5: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SN54LV4052A, SN74LV4052A
DUAL 4-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS
SCLS429H − MAY 1999 − REVISED APRIL 2005
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
TA = 25°C
VCC
MIN
MAX
MIN
MAX
SN74LV4052A
MIN
MAX
UNIT
IT = 2 mA,,
VI = VCC or GND,
VINH = VIL
(see Figure 1)
2.3 V
43
180
225
225
3V
34
150
190
190
4.5 V
25
75
100
100
IT = 2 mA,
VI = VCC to GND,
VINH = VIL
2.3 V
133
500
600
600
3V
63
180
225
225
4.5 V
35
100
125
125
Difference in
on-state
on
state resistance
between switches
IT = 2 mA,
VI = VCC to GND,
VINH = VIL
2.3 V
1.5
30
40
40
3V
1.1
20
30
30
4.5 V
0.7
15
20
20
II
Control input current
VI = 5.5 V or GND
0 to
5.5 V
±0.1
±1
±1
μA
IS(off)
Off-state switch
leakage current
VI = VCC and VO = GND, or
VI = GND and VO = VCC,
VINH = VIH
(see Figure 2)
5.5 V
±0.1
±1
±1
μA
IS(on)
On-state switch
leakage current
VI = VCC or GND,
VINH = VIL
(see Figure 3)
5.5 V
±0.1
±1
±1
μA
ICC
Supply current
VI = VCC or GND
5.5 V
20
20
μA
CIC
Control input
capacitance
f = 10 MHz
3.3 V
2.1
pF
CIS
Common terminal
capacitance
3.3 V
13.1
pF
COS
Switch terminal
capacitance
3.3 V
5.6
pF
CF
Feedthrough
capacitance
3.3 V
0.5
pF
ron
ron(p)
Δron
On-state
switch resistance
P k
Peak
on-state resistance
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
SN54LV4052A
TYP
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
Ω
Ω
Ω
SN54LV4052A, SN74LV4052A
DUAL 4-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS
SCLS429H − MAY 1999 − REVISED APRIL 2005
switching characteristics over recommended operating free-air temperature range,
VCC = 2.5 V ± 0.2 V (unless otherwise noted)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST
CONDITIONS
COM or Y
Y or COM
TA = 25°C
MIN
SN54LV4052A
MIN
MAX
SN74LV4052A
MIN
MAX
UNIT
TYP
MAX
CL = 15 pF,
(see Figure 4)
1.9
10
16
16
ns
tPLH
tPHL
Propagation
delay time
tPZH
tPZL
Enable
delay time
INH
COM or Y
CL = 15 pF,
(see Figure 5)
8
18
23
23
ns
tPHZ
tPLZ
Disable
delay time
INH
COM or Y
CL = 15 pF,
(see Figure 5)
8.3
18
23
23
ns
tPLH
tPHL
Propagation
delay time
COM or Y
Y or COM
CL = 50 pF,
(see Figure 4)
3.8
12
18
18
ns
tPZH
tPZL
Enable
delay time
INH
COM or Y
CL = 50 pF,
(see Figure 5)
9.4
28
35
35
ns
tPHZ
tPLZ
Disable
delay time
INH
COM or Y
CL = 50 pF,
(see Figure 5)
12.4
28
35
35
ns
switching characteristics over recommended operating free-air temperature range,
VCC = 3.3 V ± 0.3 V (unless otherwise noted)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST
CONDITIONS
COM or Y
Y or COM
TA = 25°C
MIN
SN54LV4052A
MIN
MAX
SN74LV4052A
MIN
MAX
UNIT
TYP
MAX
CL = 15 pF,
(see Figure 4)
1.2
6
10
10
ns
tPLH
tPHL
Propagation
delay time
tPZH
tPZL
Enable
delay time
INH
COM or Y
CL = 15 pF,
(see Figure 5)
5.7
12
15
15
ns
tPHZ
tPLZ
Disable
delay time
INH
COM or Y
CL = 15 pF,
(see Figure 5)
6.6
12
15
15
ns
tPLH
tPHL
Propagation
delay time
COM or Y
Y or COM
CL = 50 pF,
(see Figure 4)
2.5
9
12
12
ns
tPZH
tPZL
Enable
delay time
INH
COM or Y
CL = 50 pF,
(see Figure 5)
6.7
20
25
25
ns
tPHZ
tPLZ
Disable
delay time
INH
COM or Y
CL = 50 pF,
(see Figure 5)
9.5
20
25
25
ns
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
SN54LV4052A, SN74LV4052A
DUAL 4-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS
SCLS429H − MAY 1999 − REVISED APRIL 2005
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V (unless otherwise noted)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST
CONDITIONS
COM or Y
Y or COM
TA = 25°C
MIN
SN54LV4052A
MIN
MAX
SN74LV4052A
MIN
MAX
UNIT
TYP
MAX
CL = 15 pF,
(see Figure 4)
0.7
4
7
7
ns
tPLH
tPHL
Propagation
delay time
tPZH
tPZL
Enable
delay time
INH
COM or Y
CL = 15 pF,
(see Figure 5)
4
8
10
10
ns
tPHZ
tPLZ
Disable
delay time
INH
COM or Y
CL = 15 pF,
(see Figure 5)
5
8
10
10
ns
tPLH
tPHL
Propagation
delay time
COM or Y
Y or COM
CL = 50 pF,
(see Figure 4)
1.5
6
8
8
ns
tPZH
tPZL
Enable
delay time
INH
COM or Y
CL = 50 pF,
(see Figure 5)
4.7
14
18
18
ns
tPHZ
tPLZ
Disable
delay time
INH
COM or Y
CL = 50 pF,
(see Figure 5)
6.9
14
18
18
ns
analog switch characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
Frequency response
(switch on)
Crosstalk
(between any switches)
Crosstalk
(control input to signal output)
Feedthrough attenuation
(switch off)
Sine-wave distortion
FROM
(INPUT)
TO
(OUTPUT)
COM or Y
Y or COM
COM or Y
INH
COM or Y
COM or Y
Y or COM
COM or Y
Y or COM
Y or COM
TEST
CONDITIONS
VCC
TA = 25°C
MIN
TYP
CL = 50 pF,
p ,
RL = 600 Ω,
fin
i = 1 MHz (sine wave)
(see Note 6 and Figure 6)
2.3 V
30
3V
35
4.5 V
50
CL = 50 pF,
p ,
RL = 600 Ω,
fin = 1 MHz (sine wave)
(see Note 7 and Figure 7)
2.3 V
−45
3V
−45
4.5 V
−45
CL = 50 pF,
p ,
RL = 600 Ω,
fin = 1 MHz (square wave)
(see Figure 8)
2.3 V
20
3V
35
4.5 V
65
CL = 50 pF,
p ,
RL = 600 Ω,
fin = 1 MHz (sine wave)
(see Note 7 and Figure 9)
2.3 V
−45
3V
−45
4.5 V
−45
CL = 50 pF,
RL = 10 kΩ,
kΩ
fin = 1 kHz
( i wave))
(sine
(see Figure 10)
2.3 V
0.1
3V
0.1
4.5 V
0.1
VI = 2 Vp-p
VI = 2.5 Vp-p
VI = 4 Vp-p
MAX
UNIT
MHz
dB
mV
dB
%
NOTES: 6. Adjust fin voltage to obtain 0 dBm at output. Increase fin frequency until dB meter reads −3 dB.
7. Adjust fin voltage to obtain 0 dBm at input.
operating characteristics, TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance
CL = 50 pF,
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
f = 10 MHz
TYP
UNIT
11.8
pF
SN54LV4052A, SN74LV4052A
DUAL 4-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS
SCLS429H − MAY 1999 − REVISED APRIL 2005
PARAMETER MEASUREMENT INFORMATION
VCC
VINH = VIL
VCC
VI = VCC or GND
VO
(ON)
GND
r on +
VI – VO
2
10 –3
W
2 mA
V
VI − VO
Figure 1. On-State Resistance Test Circuit
VCC
VINH = VIH
VCC
VI
A
(OFF)
VO
GND
Condition 1: VI = 0, VO = VCC
Condition 2: VI = VCC, VO = 0
Figure 2. Off-State Switch Leakage-Current Test Circuit
VCC
VINH = VIL
VCC
VI
A
(ON)
Open
GND
VI = VCC or GND
Figure 3. On-State Switch Leakage-Current Test Circuit
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
SN54LV4052A, SN74LV4052A
DUAL 4-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS
SCLS429H − MAY 1999 − REVISED APRIL 2005
PARAMETER MEASUREMENT INFORMATION
VCC
VINH = VIL
VCC
Input
Output
(ON)
50 Ω
CL
GND
Figure 4. Propagation Delay Time, Signal Input to Signal Output
VCC
50 Ω
VINH
VCC
VO
VI
S1
RL = 1 kΩ
S2
TEST
S1
S2
tPLZ/tPZL
tPHZ/tPZH
GND
VCC
VCC
GND
CL
GND
TEST CIRCUIT
VCC
VCC
VINH
VINH
50%
0V
50%
0V
tPZL
tPZH
≈VCC
VOH
VO
VO
50%
VOL
(tPZL, tPZH)
VCC
VCC
VINH
50%
≈0 V
VINH
50%
0V
50%
0V
tPLZ
tPHZ
≈VCC
VO
VOL
VOH
VO
VOL + 0.3 V
(tPLZ, tPHZ)
VOH − 0.3 V
≈0 V
VOLTAGE WAVEFORMS
Figure 5. Switching Time (tPZL, tPLZ, tPZH, tPHZ), Control to Signal Output
8
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• DALLAS, TEXAS 75265
SN54LV4052A, SN74LV4052A
DUAL 4-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS
SCLS429H − MAY 1999 − REVISED APRIL 2005
PARAMETER MEASUREMENT INFORMATION
VCC
VINH = GND
0.1 μF
VCC
VI
fin
VO
(ON)
GND
50 Ω
RL = 600 Ω
CL = 50 pF
VCC/2
NOTE A: fin is a sine wave.
Figure 6. Frequency Response (Switch On)
VCC
VINH = GND
0.1 μF
VCC
VI
fin
VO1
(ON)
600 Ω
GND
50 Ω
RL = 600 Ω
CL = 50 pF
VCC/2
VCC
VINH = VCC
VCC
(OFF)
VO2
GND
600 Ω
RL = 600 Ω
CL = 50 pF
VCC/2
Figure 7. Crosstalk Between Any Two Switches
VCC
50 Ω
VINH
VCC
fin
VO
600 Ω
VCC/2
GND
RL = 600 Ω
CL = 50 pF
VCC/2
Figure 8. Crosstalk Between Control Input and Switch Output
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
9
SN54LV4052A, SN74LV4052A
DUAL 4-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS
SCLS429H − MAY 1999 − REVISED APRIL 2005
PARAMETER MEASUREMENT INFORMATION
VCC
VINH = VCC
0.1 μF
VI
fin
50 Ω
VCC
GND
600 Ω
VO
(OFF)
RL = 600 Ω
CL = 50 pF
VCC/2
VCC/2
Figure 9. Feedthrough Attenuation (Switch Off)
VCC
VINH = GND
10 μF
fin
600 Ω
VI
VCC
VO
(ON)
GND
RL = 10 kΩ
VCC/2
Figure 10. Sine-Wave Distortion
10
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• DALLAS, TEXAS 75265
CL = 50 pF
PACKAGE OPTION ADDENDUM
www.ti.com
9-Apr-2010
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN74LV4052AD
ACTIVE
SOIC
D
16
SN74LV4052ADBR
ACTIVE
SSOP
DB
SN74LV4052ADBRE4
ACTIVE
SSOP
SN74LV4052ADBRG4
ACTIVE
SN74LV4052ADE4
40
Lead/Ball Finish
MSL Peak Temp (3)
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
DB
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SSOP
DB
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV4052ADG4
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV4052ADGVR
ACTIVE
TVSOP
DGV
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV4052ADGVRE4
ACTIVE
TVSOP
DGV
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV4052ADGVRG4
ACTIVE
TVSOP
DGV
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV4052ADR
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV4052ADRE4
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV4052ADRG3
PREVIEW
SOIC
D
16
2500
SN74LV4052ADRG4
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
SN74LV4052AN
ACTIVE
PDIP
N
16
25
SN74LV4052ANE4
ACTIVE
PDIP
N
16
25
SN74LV4052ANSR
ACTIVE
SO
NS
16
SN74LV4052ANSRE4
ACTIVE
SO
NS
SN74LV4052ANSRG4
ACTIVE
SO
SN74LV4052APW
ACTIVE
SN74LV4052APWE4
TBD
Call TI
Call TI
CU NIPDAU
Level-1-260C-UNLIM
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
NS
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TSSOP
PW
16
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
ACTIVE
TSSOP
PW
16
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV4052APWG4
ACTIVE
TSSOP
PW
16
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV4052APWR
ACTIVE
TSSOP
PW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV4052APWRE4
ACTIVE
TSSOP
PW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV4052APWRG4
ACTIVE
TSSOP
PW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV4052APWT
ACTIVE
TSSOP
PW
16
250
CU NIPDAU
Level-1-260C-UNLIM
Addendum-Page 1
Green (RoHS &
no Sb/Br)
PACKAGE OPTION ADDENDUM
www.ti.com
9-Apr-2010
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN74LV4052APWTE4
ACTIVE
TSSOP
PW
16
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV4052APWTG4
ACTIVE
TSSOP
PW
16
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV4052ARGYR
ACTIVE
VQFN
RGY
16
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
SN74LV4052ARGYRG4
ACTIVE
VQFN
RGY
16
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LV4052A :
SN74LV4052A-Q1
• Automotive:
• Enhanced Product: SN74LV4052A-EP
NOTE: Qualified Version Definitions:
- Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Automotive
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Jul-2010
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
6.6
2.5
12.0
16.0
Q1
SN74LV4052ADBR
SSOP
DB
16
2000
330.0
16.4
8.2
SN74LV4052ADGVR
TVSOP
DGV
16
2000
330.0
12.4
6.8
4.0
1.6
8.0
12.0
Q1
SN74LV4052ADR
SOIC
D
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
SN74LV4052ANSR
SO
NS
16
2000
330.0
16.4
8.2
10.5
2.5
12.0
16.0
Q1
SN74LV4052APWR
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
SN74LV4052ARGYR
VQFN
RGY
16
3000
330.0
12.4
3.8
4.3
1.5
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Jul-2010
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74LV4052ADBR
SSOP
DB
16
2000
346.0
346.0
33.0
SN74LV4052ADGVR
TVSOP
DGV
16
2000
346.0
346.0
29.0
SN74LV4052ADR
SOIC
D
16
2500
333.2
345.9
28.6
SN74LV4052ANSR
SO
NS
16
2000
346.0
346.0
33.0
SN74LV4052APWR
TSSOP
PW
16
2000
346.0
346.0
29.0
SN74LV4052ARGYR
VQFN
RGY
16
3000
346.0
346.0
29.0
Pack Materials-Page 2
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,40
0,23
0,13
24
13
0,07 M
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–8°
1
0,75
0,50
12
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,08
14
16
20
24
38
48
56
A MAX
3,70
3,70
5,10
5,10
7,90
9,80
11,40
A MIN
3,50
3,50
4,90
4,90
7,70
9,60
11,20
DIM
4073251/E 08/00
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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