SCLS428H − MAY 1999 − REVISED APRIL 2005
Y4
Y6
COM
Y7
Y5
INH
GND
GND
15
3
14
4
13
5
12
6
11
7
10
8
9
Y6
COM
Y7
Y5
INH
GND
VCC
Y2
Y1
Y0
Y3
A
B
C
1
16
2
15
3
14
Y2
Y1
13 Y0
12 Y3
11 A
10 B
4
5
6
7
8
GND
The ’LV4051A devices handle both analog and
digital signals. Each channel permits signals with
amplitudes up to 5.5 V (peak) to be transmitted in
either direction.
16
2
SN74LV4051A . . . RGY PACKAGE
(TOP VIEW)
description/ordering information
These 8-channel CMOS analog multiplexers/
demultiplexers are designed for 2-V to 5.5-V VCC
operation.
1
VCC
D
All Ports
High On-Off Output-Voltage Ratio
Low Crosstalk Between Switches
Individual Switch Controls
Extremely Low Input Current
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
Applications include signal gating, chopping,
modulation or demodulation (modem), and signal
multiplexing for analog-to-digital and digital-toanalog conversion systems.
9
C
D
D
D
D
D
SN54LV4051A . . . J OR W PACKAGE
SN74LV4051A . . . D, DB, DGV, N, NS, OR PW PACKAGE
(TOP VIEW)
Y4
D 2-V to 5.5-V VCC Operation
D Support Mixed-Mode Voltage Operation on
ORDERING INFORMATION
PACKAGE†
TA
Tube of 25
SN74LV4051AN
SN74LV4051AN
QFN − RGY
Reel of 1000
SN74LV4051ARGYR
LW051A
Tube of 40
SN74LV4051AD
Reel of 2500
SN74LV4051ADR
SOP − NS
Reel of 2000
SN74LV4051ANSR
74LV4051A
SSOP − DB
Reel of 2000
SN74LV4051ADBR
LW051A
Tube of 90
SN74LV4051APW
Reel of 2000
SN74LV4051APWR
Reel of 250
SN74LV4051APWT
TVSOP − DGV
Reel of 2000
SN74LV4051ADGVR
LW051A
CDIP − J
Tube of 25
SNJ54LV4051AJ
SNJ54LV4051AJ
CFP − W
Tube of 150
SNJ54LV4051AW
TSSOP − PW
−55°C to 125°C
TOP-SIDE
MARKING
PDIP − N
SOIC − D
−40°C to 85°C
ORDERABLE
PART NUMBER
LV4051A
LW051A
SNJ54LV4051AW
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2005, Texas Instruments Incorporated
! "#$%&'( $#()(! (*#+&)#( $%++'( )! #* ,%-.$)#( ")'/ +#"%$! $#(*#+& #
!,'$*$)#(! ,'+ ' '+&! #* '0)! (!+%&'(! !)(")+" 1)++)(2/
+#"%$#( ,+#$'!!(3 "#'! (# ('$'!!)+.2 ($.%"' '!(3 #* )..
,)+)&''+!/
POST OFFICE BOX 655303
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1
SCLS428H − MAY 1999 − REVISED APRIL 2005
FUNCTION TABLE
INPUTS
A
ON
CHANNEL
L
L
Y0
L
H
Y1
H
L
Y2
L
H
H
Y3
H
L
L
Y4
H
L
H
Y5
H
H
L
Y6
L
H
H
H
Y7
H
X
X
X
None
INH
C
L
L
L
L
L
L
L
L
L
L
B
logic diagram (positive logic)
3
13
A
14
11
15
B
12
10
1
C
5
9
2
INH
2
4
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
COM
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
SCLS428H − MAY 1999 − REVISED APRIL 2005
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7.0 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7.0 V
Switch I/O voltage range, VIO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA
I/O diode current, IIOK (VIO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Switch through current, IT (VIO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
(see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W
(see Note 3): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W
(see Note 3): N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
(see Note 3): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
(see Note 3): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
(see Note 4): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
4. The package thermal impedance is calculated in accordance with JESD 51-5.
recommended operating conditions (see Note 5)
SN54LV4051A
VCC
VIH
VIL
VI
VIO
∆t/∆v
MIN
2‡
Supply voltage
High-level input voltage,
control inputs
Low-level input voltage,
control inputs
VCC = 2 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
Input transition rise or fall rate
1.5
VCC 0.7
VCC 0.7
VCC 0.7
VCC 0.7
VCC 0.7
VCC 0.7
0.5
0
0
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC 0.3
5.5
VCC
200
MAX
5.5
UNIT
V
V
0.5
VCC 0.3
VCC 0.3
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
Input/output voltage
5.5
MIN
2‡
1.5
VCC = 2 V
VCC = 2.3 V to 2.7 V
Control input voltage
MAX
SN74LV4051A
VCC 0.3
VCC 0.3
0
0
VCC 0.3
5.5
V
V
VCC
200
V
100
100
ns/V
20
20
TA
Operating free-air temperature
−55
125
−40
85
°C
‡ With supply voltages at or near 2 V, the analog switch on-state resistance becomes very nonlinear. It is recommended that only digital signals
be transmitted at these low supply voltages.
NOTE 5: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to TI application report Implications
of Slow or Floating CMOS Inputs, literature number SCBA004.
(*#+&)#( $#($'+(! ,+#"%$! ( ' *#+&)4' #+
"'!3( ,)!' #* "'4'.#,&'(/ )+)$'+!$ ")) )(" #'+
!,'$*$)#(! )+' "'!3( 3#).!/ '0)! (!+%&'(! +'!'+4'! ' +3 #
$)(3' #+ "!$#((%' '!' ,+#"%$! 1#% (#$'/
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3
SCLS428H − MAY 1999 − REVISED APRIL 2005
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TA = 25°C
TYP
MAX
SN54LV4051A
SN74LV4051A
PARAMETER
TEST
CONDITIONS
IT = 2 mA,
VI = VCC or GND,
VINH = VIL
(see Figure 1)
2.3 V
38
180
225
225
On-state
switch resistance
3V
30
150
190
190
4.5 V
22
75
100
100
IT = 2 mA,
VI = VCC to GND,
VINH = VIL
2.3 V
113
500
600
600
3V
54
180
225
225
4.5 V
31
100
125
125
Difference in
on-state resistance
between switches
IT = 2 mA,
VI = VCC to GND,
VINH = VIL
2.3 V
2.1
30
40
40
3V
1.4
20
30
30
4.5 V
1.3
15
20
20
Control input current
VI = 5.5 V or GND
0 to
5.5 V
±0.1
±1
±1
µA
IS(off)
Off-state switch
leakage current
VI = VCC and
VO = GND, or
VI = GND and
VO = VCC,
VINH = VIH
(see Figure 2)
5.5 V
±0.1
±1
±1
µA
IS(on)
On-state switch
leakage current
VI = VCC or GND,
VINH = VIL
(see Figure 3)
5.5 V
±0.1
±1
±1
µA
20
20
µA
ron
ron(p)
∆ron
II
ICC
CIC
Peak on-state resistance
Supply current
Control input capacitance
VI = VCC or GND
f = 10 MHz
VCC
MIN
MIN
5.5 V
MAX
MIN
MAX
UNIT
Ω
Ω
Ω
3.3 V
2
pF
CIS
Common
terminal capacitance
3.3 V
23.4
pF
COS
Switch terminal capacitance
3.3 V
5.7
pF
CF
Feedthrough capacitance
3.3 V
0.5
pF
switching characteristics over recommended operating free-air temperature range,
VCC = 2.5 V ± 0.2 V (unless otherwise noted)
PARAMETER
TA = 25°C
TYP
MAX
SN74LV4051A
TO
(OUTPUT)
TEST
CONDITIONS
COM or Yn
Yn or COM
CL = 15 pF,
(see Figure 4)
1.9
10
16
16
ns
MIN
MIN
MAX
MIN
MAX
UNIT
tPLH
tPHL
Propagation
delay time
tPZH
tPZL
Enable
delay time
INH
COM or Yn
CL = 15 pF,
(see Figure 5)
6.6
18
23
23
ns
tPHZ
tPLZ
Disable
delay time
INH
COM or Yn
CL = 15 pF,
(see Figure 5)
7.4
18
23
23
ns
tPLH
tPHL
Propagation
delay time
COM or Yn
Yn or COM
CL = 50 pF,
(see Figure 5)
3.8
12
18
18
ns
tPZH
tPZL
Enable
delay time
INH
COM or Yn
CL = 50 pF,
(see Figure 5)
7.8
28
35
35
ns
tPHZ
tPLZ
Disable
delay time
INH
COM or Yn
CL = 50 pF,
(see Figure 5)
11.5
28
35
35
ns
(*#+&)#( $#($'+(! ,+#"%$! ( ' *#+&)4' #+
"'!3( ,)!' #* "'4'.#,&'(/ )+)$'+!$ ")) )(" #'+
!,'$*$)#(! )+' "'!3( 3#).!/ '0)! (!+%&'(! +'!'+4'! ' +3 #
$)(3' #+ "!$#((%' '!' ,+#"%$! 1#% (#$'/
4
SN54LV4051A
FROM
(INPUT)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SCLS428H − MAY 1999 − REVISED APRIL 2005
switching characteristics over recommended operating free-air temperature range,
VCC = 3.3 V ± 0.3 V (unless otherwise noted)
PARAMETER
TA = 25°C
TYP
MAX
SN54LV4051A
SN74LV4051A
FROM
(INPUT)
TO
(OUTPUT)
TEST
CONDITIONS
COM or Yn
Yn or COM
CL = 15 pF,
(see Figure 4)
1.2
6
10
10
ns
MIN
MIN
MAX
MIN
MAX
UNIT
tPLH
tPHL
Propagation
delay time
tPZH
tPZL
Enable
delay time
INH
COM or Yn
CL = 15 pF,
(see Figure 5)
4.7
12
15
15
ns
tPHZ
tPLZ
Disable
delay time
INH
COM or Yn
CL = 15 pF,
(see Figure 5)
5.7
12
15
15
ns
tPLH
tPHL
Propagation
delay time
COM or Yn
Yn or COM
CL = 50 pF,
(see Figure 4)
2.5
9
12
12
ns
tPZH
tPZL
Enable
delay time
INH
COM or Yn
CL = 50 pF,
(see Figure 5)
5.5
20
25
25
ns
tPHZ
tPLZ
Disable
delay time
INH
COM or Yn
CL = 50 pF,
(see Figure 5)
8.8
20
25
25
ns
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V (unless otherwise noted)
PARAMETER
TA = 25°C
TYP
MAX
SN54LV4051A
SN74LV4051A
FROM
(INPUT)
TO
(OUTPUT)
TEST
CONDITIONS
COM or Yn
Yn or COM
CL = 15 pF,
(see Figure 4)
0.6
4
7
7
ns
MIN
MIN
MAX
MIN
MAX
UNIT
tPLH
tPHL
Propagation
delay time
tPZH
tPZL
Enable
delay time
INH
COM or Yn
CL = 15 pF,
(see Figure 5)
3.5
8
10
10
ns
tPHZ
tPLZ
Disable
delay time
INH
COM or Yn
CL = 15 pF,
(see Figure 5)
4.4
8
10
10
ns
tPLH
tPHL
Propagation
delay time
COM or Yn
Yn or COM
CL = 50 pF,
(see Figure 4)
1.5
6
8
8
ns
tPZH
tPZL
Enable
delay time
INH
COM or Yn
CL = 50 pF,
(see Figure 5)
4
14
18
18
ns
tPHZ
tPLZ
Disable
delay time
INH
COM or Yn
CL = 50 pF,
(see Figure 5)
6.2
14
18
18
ns
(*#+&)#( $#($'+(! ,+#"%$! ( ' *#+&)4' #+
"'!3( ,)!' #* "'4'.#,&'(/ )+)$'+!$ ")) )(" #'+
!,'$*$)#(! )+' "'!3( 3#).!/ '0)! (!+%&'(! +'!'+4'! ' +3 #
$)(3' #+ "!$#((%' '!' ,+#"%$! 1#% (#$'/
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• DALLAS, TEXAS 75265
5
SCLS428H − MAY 1999 − REVISED APRIL 2005
analog switch characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
Frequency response
(switch on)
Crosstalk
(control input to signal output)
Feedthrough attenuation
(switch off)
Sine-wave distortion
TA = 25°C
TYP
MAX
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS
VCC
20
Yn or COM
CL = 50 pF,
RL = 600 Ω,,
fin = 1 MHz (sine wave)
(see Note 6 and Figure 6)
2.3 V
COM or Yn
3V
25
4.5 V
35
CL = 50 pF,
RL = 600 Ω,,
fin = 1 MHz (square wave)
(see Figure 7)
2.3 V
20
3V
35
4.5 V
60
CL = 50 pF,
RL = 600 Ω,,
fin = 1 MHz
(see Note 7 and Figure 8)
2.3 V
−45
3V
−45
4.5 V
−45
CL = 50 pF,
RL = 10 kΩ,
fin = 1 kHz
(sine wave)
(see Figure 9)
2.3 V
0.1
3V
0.1
4.5 V
0.1
INH
COM or Yn
COM or Yn
Yn or COM
COM or Yn
Yn or COM
VI = 2 Vp-p
VI = 2.5 Vp-p
VI = 4 Vp-p
MIN
UNIT
MHz
mV
dB
%
NOTES: 6. Adjust fin voltage to obtain 0-dBm output. Increase fin frequency until dB meter reads −3 dB.
7. Adjust fin voltage to obtain 0-dBm input.
operating characteristics, VCC = 3.3 V, TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance
CL = 50 pF,
f = 10 MHz
PARAMETER MEASUREMENT INFORMATION
VCC
VINH = VIL
VCC
VI = VCC or GND
VO
(ON)
GND
r on +
2 mA
V
VI − VO
Figure 1. On-State Resistance Test Circuit
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
VI – VO
2
10 –3
W
TYP
UNIT
5.9
pF
SCLS428H − MAY 1999 − REVISED APRIL 2005
PARAMETER MEASUREMENT INFORMATION
VCC
VINH = VIH
VCC
A
VI
(OFF)
VO
GND
Condition 1: VI = 0, VO = VCC
Condition 2: VI = VCC, VO = 0
Figure 2. Off-State Switch Leakage-Current Test Circuit
VCC
VINH = VIL
VCC
VI
A
(ON)
Open
GND
VI = VCC or GND
Figure 3. On-State Switch Leakage-Current Test Circuit
VCC
VINH = VIL
VCC
Input
Output
(ON)
50 Ω
CL
GND
Figure 4. Propagation Delay Time, Signal Input to Signal Output
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7
SCLS428H − MAY 1999 − REVISED APRIL 2005
PARAMETER MEASUREMENT INFORMATION
VCC
50 Ω
VINH
VCC
VI
S1
VO
TEST
S1
S2
tPLZ/tPZL
tPHZ/tPZH
GND
VCC
VCC
GND
1 kΩ
S2
CL
GND
TEST CIRCUIT
VCC
VCC
VINH
50%
50%
0V
0V
tPZH
tPZL
≈VCC
VOH
VO
50%
50%
VOL
≈0 V
(tPZL, tPZH)
VCC
VCC
VINH
50%
50%
0V
0V
tPHZ
tPLZ
≈VCC
VOH
VO
VOL + 0.3 V
VOL
VOH − 0.3 V
≈0 V
(tPLZ, tPHZ)
VOLTAGE WAVEFORMS
Figure 5. Switching Time (tPZL, tPLZ, tPZH, tPHZ), Control to Signal Output
VCC
VINH = GND
0.1 µF
fin
VI
VCC
(ON)
GND
50 Ω
VO
RL
CL
VCC/2
NOTE A: fin is a sine wave.
Figure 6. Frequency Response (Switch On)
8
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SCLS428H − MAY 1999 − REVISED APRIL 2005
PARAMETER MEASUREMENT INFORMATION
VCC
50 Ω
VINH
VCC
VO
GND
600 Ω
RL
VCC/2
CL
VCC/2
Figure 7. Crosstalk (Control Input, Switch Output)
VCC
VINH = VCC
0.1 µF
VI
fin
50 Ω
VCC
(OFF)
VO
GND
600 Ω
RL
CL
VCC/2
VCC/2
Figure 8. Feedthrough Attenuation (Switch Off)
VCC
VINH = GND
10 µF
fin
600 Ω
10 µF
VCC
(ON)
GND
VO
RL
CL
VCC/2
Figure 9. Sine-Wave Distortion
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9
PACKAGE OPTION ADDENDUM
www.ti.com
4-Jun-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN74LV4051AD
ACTIVE
SOIC
D
16
SN74LV4051ADBR
ACTIVE
SSOP
DB
SN74LV4051ADBRE4
ACTIVE
SSOP
SN74LV4051ADBRG4
ACTIVE
SN74LV4051ADE4
40
Lead/Ball Finish
MSL Peak Temp (3)
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
DB
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SSOP
DB
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV4051ADG4
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV4051ADGVR
ACTIVE
TVSOP
DGV
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV4051ADGVRE4
ACTIVE
TVSOP
DGV
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV4051ADGVRG4
ACTIVE
TVSOP
DGV
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV4051ADR
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV4051ADRE4
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV4051ADRG4
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV4051AN
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
SN74LV4051ANE4
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
SN74LV4051ANSR
ACTIVE
SO
NS
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV4051ANSRE4
ACTIVE
SO
NS
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV4051ANSRG4
ACTIVE
SO
NS
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV4051APW
ACTIVE
TSSOP
PW
16
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV4051APWE4
ACTIVE
TSSOP
PW
16
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV4051APWG4
ACTIVE
TSSOP
PW
16
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV4051APWR
ACTIVE
TSSOP
PW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV4051APWRE4
ACTIVE
TSSOP
PW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV4051APWRG4
ACTIVE
TSSOP
PW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV4051APWT
ACTIVE
TSSOP
PW
16
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV4051APWTE4
ACTIVE
TSSOP
PW
16
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
4-Jun-2007
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN74LV4051APWTG4
ACTIVE
TSSOP
PW
16
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV4051ARGYR
ACTIVE
QFN
RGY
16
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
SN74LV4051ARGYRG4
ACTIVE
QFN
RGY
16
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Jan-2008
TAPE AND REEL BOX INFORMATION
Device
Package Pins
Site
Reel
Diameter
(mm)
Reel
Width
(mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN74LV4051ADBR
DB
16
SITE 41
330
16
8.2
6.6
2.5
12
16
Q1
SN74LV4051ADGVR
DGV
16
SITE 41
330
12
6.8
4.0
1.6
8
16
Q1
SN74LV4051ADR
D
16
SITE 27
330
16
6.5
10.3
2.1
8
16
Q1
SN74LV4051ANSR
NS
16
SITE 41
330
16
8.2
10.5
2.5
12
16
Q1
SN74LV4051APWR
PW
16
SITE 41
330
12
7.0
5.6
1.6
8
12
Q1
SN74LV4051ARGYR
RGY
16
SITE 41
180
12
3.8
4.3
1.5
8
12
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
Device
12-Jan-2008
Package
Pins
Site
Length (mm)
Width (mm)
Height (mm)
SN74LV4051ADBR
DB
16
SITE 41
346.0
346.0
33.0
SN74LV4051ADGVR
DGV
16
SITE 41
346.0
346.0
29.0
SN74LV4051ADR
D
16
SITE 27
342.9
345.9
28.58
SN74LV4051ANSR
NS
16
SITE 41
346.0
346.0
33.0
SN74LV4051APWR
PW
16
SITE 41
346.0
346.0
29.0
SN74LV4051ARGYR
RGY
16
SITE 41
190.5
212.7
31.75
Pack Materials-Page 2
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,40
0,23
0,13
24
13
0,07 M
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–8°
1
0,75
0,50
12
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,08
14
16
20
24
38
48
56
A MAX
3,70
3,70
5,10
5,10
7,90
9,80
11,40
A MIN
3,50
3,50
4,90
4,90
7,70
9,60
11,20
DIM
4073251/E 08/00
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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