ADS8519 www.ti.com SLAS462A – JUNE 2007 – REVISED MARCH 2008 16-Bit, 250kSPS, Serial, CMOS, Sampling ANALOG-TO-DIGITAL CONVERTER FEATURES 1 • • • • • 23 • • • • • • • 0V to 8.192V, ±5V, and ±10V Input Ranges 93dB SNR with 20kHz Input ±1.5LSB Max INL ±1LSB Max DNL; 16 Bits, No Missing Codes SPI™-Compatible Serial Output with Daisy-Chain (TAG) Feature and 3-State Bus 5V Analog Supply, 1.65V to 5.25V I/O Supply Pinout Similar to 16-Bit ADS7809 (Low-Speed) and 12-Bit ADS7808 and ADS8508 No External Precision Resistors Required Uses Internal or External Reference 110mW Typ Power Dissipation at 250kSPS 28-Pin SSOP Package Simple DSP Interface The ADS8519 is a complete 16-bit sampling analog-to-digital (A/D) converter using state-of-the-art CMOS structures. It contains a complete 16-bit, capacitor-based, successive approximation register (SAR) A/D converter with sample-and-hold, reference, clock, and a serial data interface. Data can be output using the internal clock or synchronized to an external data clock. The ADS8519 also provides an output synchronization pulse for ease-of-use with standard DSP processors. The ADS8519 is specified at a 250kSPS sampling rate over the full temperature range. Internal precision resistors provide various input ranges including ±10V, ±5V, and 0V to 8.192V, while the innovative design allows operation from a single 5V supply with power dissipation under 125mW. The ADS8519 is available in a 28-pin SSOP package, and is fully specified for operation over the industrial –40°C to +85°C temperature range. APPLICATIONS • • • • • DESCRIPTION Industrial Process Control Data Acquisition Systems Digital Signal Processing Medical Equipment Instrumentation Successive Approximation Register Clock CDAC 7kΩ R1IN BUSY 7kΩ R2IN 2.87kΩ R3IN EXT/INT 25.67kΩ Comparator CAP Buffer 4kΩ REF Internal +4.096V Ref Serial Data Out and Control DATACLK TAG DATA R/C SB/BTC CS PWRD 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SPI is a trademark of Motorola, Inc. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007–2008, Texas Instruments Incorporated ADS8519 www.ti.com SLAS462A – JUNE 2007 – REVISED MARCH 2008 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. PACKAGE/ORDERING INFORMATION (1) PRODUCT MINIMUM INL (LSB) NO MISSING CODES MINIMUM SINAD (dB) SPECIFIED TEMPERATURE RANGE PACKAGELEAD PACKAGE DESIGNATOR ADS8519IB ±1.5 16-Bit 90 –40°C to +85°C SSOP-28 DB ADS8519I ±3 15-Bit 87 –40°C to +85°C SSOP-28 DB (1) ORDERING NUMBER TRANSPORT MEDIA, QTY ADS8519IBDB Tube, 50 ADS8519IBDBR Tape and Reel, 2000 ADS8519IDB Tube, 50 ADS8519IDBR Tape and Reel, 2000 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) (2) Over operating free-air temperature range (unless otherwise noted). UNIT Analog inputs R1IN ±25V R2IN ±25V R3IN ±25V REF +VANA + 0.3V to AGND2 – 0.3V DGND, AGND2 Ground voltage differences ±0.3V VANA 6V VDIG 6V Digital inputs –0.3V to +VDIG + 0.3V Internal power dissipation 700mW Maximum junction temperature +165°C Lead temperature (soldering, 10s) +300°C (1) (2) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal. ELECTRICAL CHARACTERISTICS At TA = –40°C to +85°C, fs = 250kSPS, and VDIG = VANA = 5V, using internal reference (unless otherwise specified). ADS8519I PARAMETER TEST CONDITIONS MIN TYP Resolution ADS8519IB MAX MIN TYP 16 MAX 16 UNIT Bits ANALOG INPUT Voltage ranges (1) Impedance (1) Capacitance 50 50 pF THROUGHPUT SPEED Conversion cycle time Acquire and convert Throughput rate (1) 2 4 250 4 250 µs kSPS ±10V, ±5V, 0V to 8.192V, etc. (see Table 3) Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): ADS8519 ADS8519 www.ti.com SLAS462A – JUNE 2007 – REVISED MARCH 2008 ELECTRICAL CHARACTERISTICS (continued) At TA = –40°C to +85°C, fs = 250kSPS, and VDIG = VANA = 5V, using internal reference (unless otherwise specified). ADS8519I PARAMETER TEST CONDITIONS MIN TYP ADS8519IB MAX MIN TYP MAX UNIT LSB (2) DC ACCURACY INL Integral linearity error –3 3 –1.5 1.5 DNL Differential linearity error –2 2 –1 1 No missing codes 15 Transition noise (3) Full-scale error (4) (5) 0.67 ±10V range Internal reference –0.5 All other ranges Internal reference –0.5 –0.05 0.003 Full-scale error drift Full-scale error (4) (5) Internal reference External reference –0.05 All other ranges External reference –0.5 External reference Bipolar zero error (4) 0.5 –0.25 0.5 –0.5 –0.05 0.05 –0.05 0.003 0.5 –0.5 4 –2 Bipolar zero error drift –20 Unipolar zero error drift Recovery to rated accuracy after power down 1µF capacitor to CAP Power supply sensitivity (VDIG = VANA = VD) +4.75V < VD < +5.25V –8 95 6 0.25 0.5 0.5 –20 6 ±0.4 ±0.4 1 1 8 –8 %FSR ppm/°C 2 ±2 20 %FSR ppm/°C 0.05 ±2 ±2 8.192V LSB ±7 ±2 –4 LSB Bits 0.67 ±7 ±10V range Full-scale error drift Unipolar zero error (4) 16 mV ppm/°C 20 mV ppm/°C ms 8 LSB AC ACCURACY SFDR Spurious-free dynamic range fI = 20kHz THD Total harmonic distortion fI = 20kHz SINAD Signal-to-(noise+distortion) SNR Signal-to-noise ratio 100 –96 fI = 20kHz 87 –60dB Input 97 –94 91 –98 90 30 fI = 20kHz 88 Full-power bandwidth (7) 92 91 500 dB (6) 100 –96 dB 92 dB 32 dB 93 dB 500 kHz SAMPLING DYNAMICS Aperture delay Transient response 5 FS step 5 2 Overvoltage recovery (8) ns 2 150 150 µs ns REFERENCE Internal reference voltage No load 4.076 4.076 4.096 4.116 V 1 µA Internal reference drift 8 8 ppm/°C External reference current drain (6) (7) (8) 4.116 1 External reference voltage range for specified linearity (2) (3) (4) (5) 4.096 Internal reference source current (must use external buffer) 2.5 4.096 External 4.096V ref. 4.1 100 2.5 4.096 4.1 V 100 µA LSB means Least Significant Bit. For the ±10V input range, one LSB is 305µV. Typical rms noise at worst-case transitions and temperatures. As measured with circuit shown in Figure 29 and Figure 30. For bipolar input ranges, full-scale error is the worst case of –Full-Scale or +Full-Scale uncalibrated deviation from ideal first and last code transitions, divided by the transition voltage (not divided by the full-scale range) and includes the effect of offset error. For unipolar input ranges, full-scale error is the deviation of the last code transition divided by the transition voltage. It also includes the effect of offset error. All specifications in dB are referred to a full-scale ±10V input. Full-power bandwidth is defined as the full-scale input frequency at which signal-to-(noise + distortion) degrades to 60dB. Recovers to specified performance after 2 x FS input overvoltage. Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): ADS8519 3 ADS8519 www.ti.com SLAS462A – JUNE 2007 – REVISED MARCH 2008 ELECTRICAL CHARACTERISTICS (continued) At TA = –40°C to +85°C, fs = 250kSPS, and VDIG = VANA = 5V, using internal reference (unless otherwise specified). ADS8519I PARAMETER TEST CONDITIONS MIN ADS8519IB TYP MAX MIN TYP MAX UNIT DIGITAL INPUTS Logic levels VIL Low-level input voltage (9) VDIG = 1.65V to 5.25V –0.3 0.6 –0.3 0.6 VIH High-level input voltage (9) VDIG = 1.65V to 5.25V 0.5 x VDIG VDIG + 0.3 0.5 x VDIG VDIG + 0.3 V IIL Low-level input current VIL = 0V ±10 ±10 µA IIH High-level input current VIH = 5V ±10 ±10 µA V DIGITAL OUTPUTS Data format Serial, 16-bits Serial, 16-bits Data coding Binary 2's complement or straight binary Binary 2's complement or straight binary Conversion results only available after completed conversion Conversion results only available after completed conversion Selectable for internal or external data clock Selectable for internal or external data clock Pipeline delay Data clock Internal clock (output only when transmitting data) EXT/INT low External clock (can run continually but not recommended for optimum performance) EXT/INT high VOL Low-level output voltage ISINK = 1.6mA, VDIG = 1.65V to 5.25V VOH High-level output voltage ISOURCE = 500µA, VDIG = 1.65V to 5.25V Leakage current Hi-Z state, VOUT = 0V to VDIG ±5 ±5 µA Output capacitance Hi-Z state 15 15 pF 5.25 V 9 0.1 9 26 0.1 26 0.45 VDIG – 0.45 MHz MHz 0.45 V VDIG – 0.45 V POWER SUPPLIES VDIG Digital input voltage Must be ≤ VANA 1.65 VANA Analog input voltage Must be ≤ VANA 4.75 IDIG Digital input current IANA Analog input current 5.25 1.65 5 5.25 4.75 Must be ≤ VANA 0.1 Must be ≤ VANA 5 5.25 1 0.1 1 mA V 22 25 22 25 mA 110 125 110 125 mW POWER DISSIPATION PWRD Low fS = 250kSPS PWRD High 20 µW 20 TEMPERATURE RANGE θJA Specified performance –40 +85 –40 +85 °C Derated performance (10) –55 +125 –55 +125 °C Storage –65 +150 –65 +150 Thermal resistance 67 67 °C °C/W (9) TTL-compatible at 5V supply. (10) The internal reference may not be started correctly beyond the industrial temperature range (–40°C to +85°C); therefore, use of an external reference is recommended. 4 Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): ADS8519 ADS8519 www.ti.com SLAS462A – JUNE 2007 – REVISED MARCH 2008 PIN CONFIGURATION DB PACKAGE (TOP VIEW) R1IN 1 AGND1 2 28 VDIG 27 VANA R2IN 3 26 PWRD R3IN 4 NC 5 25 BUSY CAP 6 23 NC REF 7 22 NC NC 8 AGND2 9 24 CS 21 R/C 20 NC NC 10 19 TAG NC 11 18 NC SB/BTC 12 EXT/INT 13 DGND 14 17 DATA 16 DATACLK 15 SYNC Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): ADS8519 5 ADS8519 www.ti.com SLAS462A – JUNE 2007 – REVISED MARCH 2008 Pin Assignments PIN 6 NAME NO. I/O AGND1 2 – Analog ground. Used internally as ground reference point. Minimal current flow. DESCRIPTION AGND2 9 – Analog ground BUSY 25 O Busy output. Falls when a conversion is started, and remains low until the conversion is completed and the data are latched into the output shift register. CS 24 – Chip select. Internally ORed with R/C. CAP 6 Reference buffer capacitor, 2.2µF tantalum capacitor to ground. DATA 17 O Serial data output. Data are synchronized to DATACLK, with the format determined by the level of SB/BTC. In the external clock mode, after 16 bits of data, the ADS8519 outputs the level input on TAG as long as CS is low and R/C is high (see Figure 8 and Figure 9). If EXT/INT is low, data are valid on both the rising and falling edges of DATACLK, and between conversions DATA stays at the level of the TAG input when the conversion was started. DATACLK 16 I/O Either an input or an output, depending on the EXT/INT level. Output data are synchronized to this clock. If EXT/INT is low, DATACLK transmits 16 pulses after each conversion, and then remains low between conversions. DGND 14 – Digital ground EXT/INT 13 – Selects external or internal clock for transmitting data. If high, data are output synchronized to the clock input on DATACLK. If low, a convert command initiates the transmission of the data from the previous conversion, along with 16 clock pulses output on DATACLK. NC 5, 8, 10, 11, 18, 20, 22, 23 – Not connected PWRD 26 I Power down input. If high, conversions are inhibited and power consumption is significantly reduced. Results from the previous conversion are maintained in the output shift register. R/C 21 I Read/convert input. With CS low, a falling edge on R/C puts the internal sample-and-hold into the hold state and starts a conversion. When EXT/INT is low, this also initiates the transmission of the data results from the previous conversion. If EXT/INT is high, a rising edge on R/C with CS low, or a falling edge on CS with R/C high, initiates the transmission of data from the previous conversion. REF 7 I/O R1IN 1 I Analog input. See Table 3 for input range connections. R2IN 3 I Analog input. See Table 3 for input range connections. R3IN 4 I Analog input. See Table 3 for input range connections. SB/BTC 12 O Select straight binary or binary two's complement data output format. If high, data are output in a straight binary format. If low, data are output in a binary two's complement format. SYNC 15 O Sync output. This pin is used to supply a data synchronization pulse when the EXT level is high and at least one external clock pulse has occurred when not in the read mode. See the External DATACLK section for the external clock mode description. TAG 19 I Tag input for use in the external clock mode. If EXT is high, digital data input from TAG is output on DATA with a delay that depends on the external clock mode. See Figure 8 and Figure 9. VANA 27 I Analog supply input. Nominally +5V. Connect directly to pin 20, and decouple to ground with 0.1µF ceramic and 10µF tantalum capacitors. VDIG 28 I Digital supply input. Connect directly to pin 19. Reference input/output. Outputs internal 4.096V reference. Can also be driven by external system reference. In both cases, bypass to ground with a 2.2µF tantalum capacitor. Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): ADS8519 ADS8519 www.ti.com SLAS462A – JUNE 2007 – REVISED MARCH 2008 TIMING REQUIREMENTS, TA = –40°C to +85°C PARAMETER MIN TYP MAX 6 20 ns 2.2 µs tw1 Pulse duration, convert td1 Delay time, BUSY from R/C low tw2 Pulse duration, BUSY low td2 Delay time, BUSY, after end of conversion 5 td3 Delay time, aperture 5 tconv Conversion time tacq Acquisition time tconv + tacq 40 UNIT ns ns ns 2.2 µs µs 1.8 Cycle time 4 µs td4 Delay time, R/C Low to internal DATACLK output 270 ns tc1 Cycle time, internal DATACLK 110 ns td5 Delay time, data valid to internal DATACLK high 15 35 ns td6 Delay time, data valid after internal DATACLK low 20 35 ns tc2 Cycle time, external DATACLK 35 ns tw3 Pulse duration, external DATACLK high 15 ns tw4 Pulse duration, external DATACLK low 15 ns tsu1 Setup time, R/C rise/fall to external DATACLK high 15 ns tsu2 Setup time, R/C transition to CS transition 10 td7 Delay time, SYNC, after external DATACLK high 3 35 ns td8 Delay time, data valid from external DATACLK high 2 13 ns td9 Delay time, CS rising edge to external DATACLK rising edge td10 tsu3 td11 Delay time, final external DATACLK to BUSY rising edge tsu4 Setup time, TAG valid 0 ns th1 Hold time, TAG valid 2 ns ns 10 ns Delay time, previous data available after CS, R/C low 2 µs Setup time, BUSY transition to first external DATACLK 5 ns 1 µs TIMING DIAGRAMS CS R/C R/C CS tsu1 tsu1 tsu1 External DATACLK tsu1 External DATACLK CS Set Low, Discontinuous Ext DATACLK R/C Set Low, Discontinuous Ext DATACLK BUSY CS tsu2 tsu2 tsu3 External DATACLK R/C Setup Time, R/C to CS 1 2 CS Set Low, Discontinuous Ext DATACLK Figure 1. Critical Timing Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): ADS8519 7 ADS8519 www.ti.com SLAS462A – JUNE 2007 – REVISED MARCH 2008 TIMING DIAGRAMS (continued) tw1 tw1 R/C td1 td1 tw2 tw2 BUSY td2 td3 STATUS Error Correction Nth Conversion td2 td11 td3 td11 Error (N+1)th Conversion Correction (N+1)th Accquisition tconv tconv tacq tc1 td4 (N+2)th Accquisition tacq td4 Internal 1 DATACLK 2 16 16 td6 td5 DATA 2 1 D15 TAG = 0 TAG = 0 D0 D15 D0 TAG = 0 Nth Conversion Data (N−1)th Conversion Data CS, EXT/INT, and TAG are tied low 8 starts READ Figure 2. Basic Conversion Timing: Internal DATACLK (Read Previous Data During Conversion) tw1 tw1 R/C td1 td1 tw2 tw2 BUSY td2 td3 STATUS Error Correction Nth Conversion td2 td3 td11 td11 (N+1)th Accquisition (N+1)th Conversion tacq tconv (N+2)th Accquisition tacq tconv tsu3 tsu1 Error Correction tsu3 tsu1 External 1 DATACLK DATA TAG = 0 16 No more data to shift out 1 TAG = 0 EXT/INT tied high, CS and TAG are tied low 2 1 16 Nth Data TAG = 0 16 1 No more data to shift out TAG = 0 2 16 (N+1)th Data TAG = 0 tw1 + tsu1 starts READ Figure 3. Basic Conversion Timing: External DATACLK 8 Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): ADS8519 ADS8519 www.ti.com SLAS462A – JUNE 2007 – REVISED MARCH 2008 TIMING DIAGRAMS (continued) tw1 R/C td1 tsu1 tw2 td1 BUSY td2 td3 td3 td11 STATUS Nth Conversion Error Correction (N+1) th Accquisition tsu3 tconv tacq tc2 tw3 External tsu1 tw4 DATACLK 0 1 2 3 4 5 10 11 12 13 14 15 16 SYNC = 0 td8 D14 D13 D12 D11 D10 D05 D04 D03 D02 D01 D00 Null T00 Txx T02 T03 T04 T05 T06 T11 T12 T13 T14 T15 T16 Null T17 Tyy th1 tsu4 TAG td8 Nth Conversion Data D15 DATA T00 T01 EXT/INT tied high, CS tied low tw1 + tsu1 starts READ Figure 4. Read After Conversion (Discontinuous External DATACLK) tw1 R/C td1 tw2 BUSY td10 td3 td2 Error Correction Nth Conversion STATUS tsu3 tconv tc2 External tsu1 tw3 1 0 DATACLK td11 tw4 2 3 4 5 10 11 12 13 14 15 16 SYNC = 0 td8 Nth Conversion Data D15 DATA EXT/INT tied high, CS and TAG tied low D14 D13 D12 D11 D10 D05 D04 D03 td8 D02 D01 D00 Rising DATACLK change DATA, tw1 + tsu1 Starts READ TAG is not recommended for this mode. There is not enough time to do so without violating td11. Figure 5. Read During Conversion (Discontinuous External DATACLK) Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): ADS8519 9 ADS8519 www.ti.com SLAS462A – JUNE 2007 – REVISED MARCH 2008 TIMING DIAGRAMS (continued) tw1 R/C td1 tsu1 td1 tsu1 tw2 BUSY td2 td3 td3 td11 Error Nth Conversion Correction STATUS (N+1)th Accquisition tconv tacq tc2 tsu3 tsu1 External 0 DATACLK tsu1 tw4 tw3 1 2 3 4 5 6 7 12 13 14 15 16 17 18 tc2 td7 SYNC =0 td8 Nth Conversion Data D15 DATA td8 D14 D13 D12 D11 D10 D05 D04 D03 D02 D01 D00 Null T02 T03 T04 T05 T06 T11 T12 T13 T14 T15 T16 T17 T00 Txx th1 tsu4 TAG T00 T01 Tyy tw1 + tsu1 starts READ EXT/INT tied high, CS tied low Figure 6. Read After Conversion With SYNC (Discontinuous External DATACLK) tw1 R/C td1 tw2 BUSY td3 td10 td2 Error Correction Nth Conversion STATUS tsu3 tconv tsu1 tsu1 External tw3 tsu1 0 DATACLK tc2 tw4 1 2 3 td11 4 5 6 7 12 13 14 15 16 17 18 td7 tc2 SYNC = 0 td8 DATA EXT/INT tied high, CS and TAG tied low td8 Nth Conversion Data D15 D14 D13 D12 D11 D10 D05 D04 D03 D02 D01 D00 tw1 + tsu1 Starts READ TAG is not recommended for this mode. There is not enough time to do so without violating td11. Figure 7. Read During Conversion With SYNC (Discontinuous External DATACLK) 10 Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): ADS8519 ADS8519 www.ti.com SLAS462A – JUNE 2007 – REVISED MARCH 2008 Tag 18 Tag 17 Tag 16 Tag 15 Tag 2 Tag 0 Tag 1 Bit 15 (MSB) t c2 t su2 t su1 0 TAG DATA SYNC BUSY R/C CS External DATACLK t w1 t su2 t d1 t w3 t d7 1 t c2 t w4 2 t d8 3 Bit 14 4 Bit 1 17 18 Bit 0 (LSB) Tag 0 t d9 Tag 1 Tag 19 TIMING DIAGRAMS (continued) Figure 8. Conversion and Read Timing with Continuous External DATACLK (EXT/INT Tied High) Read After Conversions (Not Recommended) Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): ADS8519 11 ADS8519 www.ti.com SLAS462A – JUNE 2007 – REVISED MARCH 2008 Tag 18 Tag 17 Tag 1 TAG Tag 16 Bit 15 (MSB) DATA SYNC t d1 BUSY R/C CS External DATACLK t su2 t w3 t c2 t w1 t w4 t su1 t su1 Tag 0 t c2 t d8 t d10 Bit 0 (LSB) Tag 0 t d8 Tag 1 Tag 19 TIMING DIAGRAMS (continued) Figure 9. Conversion and Read Timing with Continuous External DATACLK (EXT/INT Tied High) Read Previous Conversion Results During Conversion (Not Recommended) 12 Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): ADS8519 ADS8519 www.ti.com SLAS462A – JUNE 2007 – REVISED MARCH 2008 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs FREE-AIR TEMPERATURE HISTOGRAM 25 8000 6930 4000 3000 2000 712 547 65531 65532 Code 65533 4.096 4.094 4.092 -20 0 20 40 60 TA - Free-Air Temperature - °C 4.09 -40 80 -20 0 20 40 60 TA - Free-Air Temperature - °C 80 Figure 12. BIPOLAR ZERO ERROR vs FREE-AIR TEMPERATURE POSITIVE FULL-SCALE ERROR vs FREE-AIR TEMPERATURE NEGATIVE FULL-SCALE ERROR vs FREE-AIR TEMPERATURE 3 2 1 0 -1 -2 -3 -20 0 20 40 60 TA - Free-Air Temperature - °C 0.25 0.20 Internal Reference ±10V Range 0.15 0.10 0.05 0 -0.05 -0.10 -0.15 -0.20 -0.25 -40 80 NFSE - Negative Full-Scale Error - %FSR PFSE - Positive Full-Scale Error - %FSR BPZ - Bipolar Zero Error - mV 18 4.098 Figure 11. -4 -20 0 20 40 60 TA - Free-Air Temperature - °C 80 0.25 0.20 0.15 Internal Reference ±10V Range 0.10 0.05 0 -0.05 -0.10 -0.15 -0.20 -0.25 -40 -20 0 20 40 60 TA - Free-Air Temperature - °C 80 Figure 13. Figure 14. Figure 15. POSITIVE FULL-SCALE ERROR vs FREE-AIR TEMPERATURE NEGATIVE FULL-SCALE ERROR vs FREE-AIR TEMPERATURE SPURIOUS FREE DYNAMIC RANGE vs FREE-AIR TEMPERATURE 0.1 NFSE - Negative Full-Scale Error - %FSR PFSE - Positive Full-Scale Error - %FSR 19 4.1 Figure 10. Internal Reference ±10V Range 0.08 20 15 -40 65534 5 -5 -40 21 16 2 65530 22 17 1 0 23 External Reference ±10V Range 0.06 0.04 0.02 0 -0.02 -0.04 -0.06 -0.08 -0.1 -40 -20 0 20 40 60 TA - Free-Air Temperature - °C 80 Figure 16. 0.1 0.08 SFDR - Spurious Free Dynamic Range - dB Count 5000 4.102 Internal Reference Voltage - V ICC - Supply Current - mA 6000 1000 4.104 24 7000 4 INTERNAL VOLTAGE REFERENCE vs FREE-AIR TEMPERATURE External Reference ±10V Range 0.06 0.04 0.02 0 -0.02 -0.04 -0.06 -0.08 -0.1 -40 -20 0 20 40 60 TA - Free-Air Temperature - °C Figure 17. 80 105 100 fS = 250kSPS fI = 20kHz 95 90 85 80 75 70 -40 -20 0 20 40 60 TA - Free-Air Temperature - °C Figure 18. Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): ADS8519 80 13 ADS8519 www.ti.com SLAS462A – JUNE 2007 – REVISED MARCH 2008 TYPICAL CHARACTERISTICS (continued) TOTAL HARMONIC DISTORTION vs FREE-AIR TEMPERATURE SIGNAL-TO-NOISE RATIO vs FREE-AIR TEMPERATURE -95 -90 -85 -80 -75 fS = 250kSPS fI = 20kHz fS = 250kSPS fI = 20kHz 95 90 85 80 75 70 -40 -20 0 20 40 60 80 TA - Free-Air Temperature - °C 0 40 -20 20 60 TA - Free-Air Temperature - °C 80 100 95 fS = 250kSPS fI = 20kHz 90 85 80 75 70 -40 -20 0 20 40 60 TA - Free-Air Temperature - °C 80 Figure 20. Figure 21. SIGNAL-TO-NOISE AND DISTORTION vs INPUT FREQUENCY SIGNAL-TO-NOISE RATIO vs INPUT FREQUENCY SPURIOUS FREE DYNAMIC RANGE vs INPUT FREQUENCY 100 100 95 90 85 80 75 95 90 85 80 75 70 70 1 10 100 fi - Input Frequency - kHz 1 1000 Figure 22. 10 100 fi - Input Frequency - kHz 1000 Figure 23. SFDR - Spurious Free Dynamic Range - dB Figure 19. SNR - Signal-to-Noise Ratio - dB SINAD - Signal-to-Noise and Distortion - dB -70 -40 SNR - Signal-to-Noise and Distortion - dB 100 SNR - Signal-to-Noise Ratio - dB THD - Total Harmonic Distortion - dB -100 SIGNAL-TO-NOISE AND DISTORTION vs FREE-AIR TEMPERATURE 105 100 95 90 85 80 75 70 1 10 100 fi - Input Frequency - kHz 1000 Figure 24. TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY THD - Total Harmonic Distortion - dB 105 100 95 90 85 80 75 70 1 10 100 fi - Input Frequency - kHz 1000 Figure 25. 14 Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): ADS8519 ADS8519 www.ti.com SLAS462A – JUNE 2007 – REVISED MARCH 2008 TYPICAL CHARACTERISTICS (continued) INL 2 1.5 INL - LSBs 1 0.5 0 -0.5 -1 -1.5 -2 0 10000 20000 30000 40000 50000 60000 70000 50000 60000 70000 Code Figure 26. DNL 2 1.5 DNL - LSBs 1 0.5 0 -0.5 -1 -1.5 -2 0 10000 20000 30000 40000 Code Figure 27. BASIC OPERATION Two signals control conversion in the ADS8519: CS and R/C. These two signals are internally ORed together. To start a conversion, the chip must be selected (CS low) and the conversion signal must be active (R/C low). Either signal can be brought low first. Conversion starts on the falling edge of the second signal. BUSY goes low when conversion starts and returns high after the data from that conversion are shifted into the internal storage register. Sampling begins when BUSY goes high. To reduce the number of control pins, CS can be tied low permanently. The R/C pin then controls conversion and data reading exclusively. In the external clock mode, this configuration means that the ADS8519 clocks out data whenever R/C is brought high and the external clock is active. In the internal clock mode, data are clocked out every convert cycle, regardless of the states of CS and R/C. The ADS8519 provides a TAG input for cascading multiple converters together. READING DATA The conversion result is available as soon as BUSY returns to high; therefore, data always represent the conversion previously completed, even when it is read during a conversion. The ADS8519 outputs serial data in either straight binary or binary two’s complement format. The SB/BTC pin controls the format. data are shifted out MSB first. The first conversion immediately following a power-up does not produce a valid conversion result. Data can be clocked out with either the internally-generated clock or with an external clock. The EXT/INT pin controls this function. If an external clock is used, the TAG input can be used to daisy-chain multiple ADS8519 data pins together. Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): ADS8519 15 ADS8519 www.ti.com SLAS462A – JUNE 2007 – REVISED MARCH 2008 INTERNAL DATACLK In the internal clock mode, data for the previous conversion are clocked out during each conversion period. The internal data clock is synchronized to the internal conversion clock so that it does not interfere with the conversion process. The DATACLK pin becomes an output when EXT/INT is low. 16 clock pulses are generated at the beginning of each conversion after timing td4 is satisfied (that is, previous conversion results can only be read during the current conversion). DATACLK returns to low when it is inactive. The 16 bits of serial data are shifted out of the DATA pin synchronous to this clock, with each bit available on a rising and then a falling edge. The DATA pin then returns to the state of the TAG pin input sensed at the start of transmission. EXTERNAL DATACLK The external clock mode offers several ways to retrieve conversion results. However, care must be taken to avoid corrupting the data because the external clock cannot be synchronized to the internal conversion clock. When EXT/INT is set high, the R/C and CS signals control the read state. When the read state is initiated, the result from the previously completed conversion is shifted out of the DATA pin synchronous to the external clock that is connected to the DATACLK pin. Each bit is available on a falling and then a rising edge. The maximum external clock speed of 28.5MHz allows data to be shifted out quickly either at the beginning of conversion or the beginning of sampling. There are several modes of operation available when using an external clock. It is recommended that the external clock run only while reading data. This mode is the discontinuous clock mode. Because the external clock is not synchronized to the internal clock that controls conversion, slight changes in the external clock can cause conflicts that can corrupt the conversion process. Specifications with a continuously running external clock cannot be ensured. It is especially important that the external clock does not run during the second half of the conversion cycle (approximately the time period specified by td11; see the Timing Requirements table). In the discontinuous clock mode, data can be read during conversion or during sampling, with or without a SYNC pulse. Data read during a conversion must meet the td11 timing specification. Data read during sampling must be complete before starting a conversion. Whether reading during sampling or during conversion, a SYNC pulse is generated whenever at least one rising edge of the external clock occurs while the device is not in the read state. In the Discontinuous External Clock with SYNC mode, a SYNC pulse follows the first rising edge after the read command. Data are shifted out after the SYNC pulse. The first rising clock edge after the read command generates a SYNC pulse. The SYNC pulse can be detected on the next falling edge and then the next rising edge. Successively, each bit can be read first on the falling edge and then on the next rising edge. Thus, 17 clock pulses after the read command are required to read on the falling edge; 18 clock pulses are necessary to read on the rising edge. If the clock is entirely inactive when not in the read state, no SYNC pulse is generated. In this case, the first rising clock edge shifts out the MSB. The MSB can be read on the first falling edge or on the next rising edge. In this Discontinuous External Clock with No SYNC mode, 16 clocks are necessary to read the data on the falling edge and 17 clocks for reading on the rising edge. Data always represent the conversion already completed. Table 2 summarizes the required DATACLK pulses. Table 2. DATACLK Pulses DATACLK PULSES REQUIRED 16 DESCRIPTION WITH SYNC WITHOUT SYNC Read on falling edge of DATACLK 17 16 Read on rising edge of DATACLK 18 17 Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): ADS8519 ADS8519 www.ti.com SLAS462A – JUNE 2007 – REVISED MARCH 2008 TAG FEATURE The TAG feature allows the data from multiple ADS8519 converters to be read on a single serial line. The converters are cascaded together using the DATA pins as outputs and the TAG pins as inputs, as illustrated in Figure 28. The DATA pin of the last converter drives the processor serial data input. Data are then shifted through each converter, synchronous to the externally supplied data clock, onto the serial data line. The internal clock cannot be used for this configuration. The preferred timing uses the discontinuous, external data clock during the sampling period. Data must be read during the sampling period because there is not sufficient time to read data from multiple converters during a conversion period without violating the td11 constraint (see External DATACLK section). The sampling period must be sufficiently long to allow all data words to be read before starting a new conversion. In Figure 28, note that a null bit separates the data word from each converter. The state of the DATA pin at the end of a read cycle reflects the state of the TAG pin at the start of the cycle. This condition is true in all read modes, including the internal clock mode. For example, when a single converter is used in the internal clock mode, the state of the TAG pin determines the state of the DATA pin after all 16 bits have shifted out. When multiple converters are cascaded together, this state forms the null bit that separates the words. Thus, with the TAG pin of the first converter grounded as shown in Figure 28, the null bit becomes a zero between each data word. Processor ADS8519A DATA CS R/C DATACLK TAG SCLK ADS 8519B TAG(A) DATA CS R/C DATACLK TAG TAG(B) GPIO GPIO SDI Null D A00 Q D Q D Null D A15 Q D Q D B00 DATA (A) A16 Q D Q D B15 Q B16 DATA (B) Q DATACLK R/C (both A & B) BUSY (both A & B) SYNC (both A & B) External DATACLK 1 2 3 4 16 17 DATA ( A ) A15 A14 A13 A01 A00 DATA ( B ) B15 B14 B13 B01 B00 18 19 20 21 Null TAG(A) = 0 A Nth Conversion Data Null A15 A14 A13 B EXT/INT tied high, CS of both converter A and B, TAG input of converter A are tied low. 34 A01 35 36 A00 Null A TAG(A) = 0 . Figure 28. Timing of TAG Feature With Single Conversion (Using External DATACLK) Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): ADS8519 17 ADS8519 www.ti.com SLAS462A – JUNE 2007 – REVISED MARCH 2008 ANALOG INPUTS The ADS8519 has three analog input ranges, as shown in Table 3. The offset specification is factory-calibrated with internal resistors. The gain specification is factory-calibrated with 0.1%, 0.25W, external resistors, as shown in Figure 29 and Figure 30. The external resistors can be omitted if a larger gain error is acceptable or if using software calibration. The hardware trim circuitry shown in Figure 29 and Figure 30 can reduce the error to zero. Table 3. Input Range Connections (see Figure 29 and Figure 30 for complete information) ANALOG INPUT RANGE CONNECT R1IN TO CONNECT R2IN TO CONNECT R3IN TO IMPEDANCE ±10V VIN AGND CAP 8.88kΩ ±10V AGND VIN CAP 8.88kΩ ±5V VIN VIN CAP 6.08kΩ 0V to 8.192V AGND AGND VIN 5.95kΩ Input Range With Trim (Adjust Gain) Without Trim 0V − 8.192V R1IN AGND1 AGND1 R2IN R2IN R3IN VIN 2.2µF R1IN CAP + 2.2µF + R3IN VIN 2.2µF + REF CAP + 5V 576kΩ 50 kΩ 2.2µF AGND2 + REF AGND2 Figure 29. Offset/Gain Circuits for Unipolar Input Ranges 18 Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): ADS8519 ADS8519 www.ti.com SLAS462A – JUNE 2007 – REVISED MARCH 2008 Input Range With Trim (Adjust Gain) Without Trim VIN R1IN ±10V AGND1 AGND1 R2IN R2IN R3IN R3IN +5V CAP + 2.2µF 2.2µF + R1IN VIN 50kΩ REF 2.2µF 576kΩ + CAP REF 2.2µF + AGND2 VIN R1IN R1IN AGND1 AGND1 R2IN ±5V AGND2 VIN R2IN R3IN 2.2µF +5V CAP + 2.2µF 2.2µF + REF 50kΩ R3IN + CAP 576kΩ REF + AGND2 2.2µF AGND2 Figure 30. Offset/Gain Circuits for Bipolar Input Ranges Analog input pins R1IN, R2IN, and R3IN have ±25V overvoltage protection. The input signal must be referenced to AGND1. This referencing minimizes the ground-loop problem typical to analog designs. The analog input should be driven by a low-impedance source. A typical driving circuit using the OPA627 or OPA132 is shown in Figure 30. The ADS8519 can operate with its internal 4.096V reference or an external reference. An external reference connected to pin 6 (REF) bypasses the internal reference. The external reference must drive the 4kΩ resistor that separates pin 6 from the internal reference (see the illustration on page 1). The load varies with the difference between the internal and external reference voltages. The external reference voltage can vary from 3.9V to 4.2V. The internal reference is approximately 4.096V. The reference, whether internal or external, is buffered internally with the output on pin 5 (CAP). The ADS8519 is factory-tested with 2.2µF capacitors connected to pin 5 (CAP) and pin 6 (REF). Each capacitor should be placed as close as possible to its pin. The capacitor on pin 6 band-limits the internal reference noise. A smaller capacitor can be used, but it may degrade SNR and SINAD The capacitor on pin 5 stabilizes the reference buffer and provides switching charge to the CDAC during conversion. Capacitors smaller than 1µF may cause the buffer to become unstable and not hold sufficient charge for the CDAC. The parts are tested to specifications with 2.2µF, so larger capacitors are not necessary. The equivalent series resistance (ESR) of these compensation capacitors is also critical. Keep the total ESR under 3Ω. See the Typical Characteristics section concerning how ESR affects performance. Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): ADS8519 19 ADS8519 www.ti.com SLAS462A – JUNE 2007 – REVISED MARCH 2008 Neither the internal reference nor the buffer should be used to drive an external load. Such loading can degrade performance. Any load on the internal reference causes a voltage drop across the 4kΩ resistor and affects gain. The internal buffer is capable of driving ±2mA loads, but any load can cause perturbations of the reference at the CDAC, degrading performance. It should be pointed out that, unlike other devices with a similar input structure, the ADS8519 does not require a second high-speed amplifier used as a buffer to isolate the CAP pin from the signal-dependent current in the R3IN pin, but can tolerate it if one does exist. The external reference voltage can vary from 3.9V to 4.2V. The reference voltage determines the size of the least significant bit (LSB). The larger reference voltages produce a larger LSB, which can improve SNR. Smaller reference voltages can degrade SNR. +15V 2.2mF 22pF ADS8519 100nF R1IN GND 2kW AGND Pin 7 2kW Pin 2 Vin 22pF Pin 1 − OPA627 or OPA132 + Pin3 R2IN Pin6 R3IN Pin4 CAP 2.2mF GND 2.2mF AGND2 GND 100nF 2.2mF −15V GND Figure 31. Typical Driving Circuitry (±10V, No Trim) Table 4. Control Truth Table SPECIFIC FUNCTION Initiate conversion and output data using internal clock Initiate conversion and output data using external clock No actions CS R/C BUSY EXT/INT DATACLK PWRD SB/BTC OPERATION 1>0 0 1 0 Output 0 x 0 1>0 1 0 Output 0 x Initiates conversion n. Data from conversion n - 1 clocked out on DATA synchronized to 16 clock pulses output on DATACLK. 1>0 0 1 1 Input 0 x Initiates conversion n. 0 1>0 1 1 Input 0 x Initiates conversion n. 1>0 1 1 1 Input x x Outputs data with or without SYNC pulse. See the Reading Data section. 1>0 1 0 1 Input 0 x 0 0>1 0 1 Input 0 x Outputs data with or without SYNC pulse. See Reading Data section. 0 0 0>1 x x 0 x This is an acceptable condition. x x x x x 0 x Analog circuitry powered. Conversion can proceed.. x x x x x 1 x Analog circuitry disabled. Data from previous conversion maintained in output registers. x x x x x x 0 Serial data are output in binary two's complement format. x x x x x x 1 Serial data are output in straight binary format. Power down Selecting output format 20 Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): ADS8519 ADS8519 www.ti.com SLAS462A – JUNE 2007 – REVISED MARCH 2008 Table 5. Output Codes and Ideal Input Voltages DESCRIPTION ANALOG INPUT RANGE DIGITAL OUTPUT Full-scale range ±10V ±5V 0V to 8.192V BINARY TWO'S COMPLEMENT (SB/BTC LOW) STRAIGHT BINARY (SB/BTC HIGH) Least significant bit (LSB) 305µV 153µV 125µV BINARY CODE HEX CODE BINARY CODE HEX CODE +Full-scale (FS – 1LSB) 9.999695V 4.999847V 8.191875V 0111 1111 1111 1111 7FFF 1111 1111 1111 1111 FFFF Midscale 0V 0V 4.096V 0000 0000 0000 0000 0000 1000 0000 0000 0000 8000 One LSB below midscale –305µV 153µV 4.095975V 1111 1111 1111 1111 FFFF 0111 1111 1111 1111 7FFF –Full scale –10V –5V 0V 1000 0000 0000 0000 8000 0000 0000 0000 0000 0000 1 ± 10V 2 +5V 2.2mF + 175kW 20kW Gain 30kW 3 4 + VIN 1 ± 10V 2 AGND1 2.2mF 5 AGND2 (a) ± 10V With Hardware Trim 3 4 CAP 2.2mF 2.2mF + REF VIN AGND1 REF CAP + 5 AGND2 (b) ± 10V Without Hardware Trim Note: Use 1% metal film resistors. Figure 32. Gain Adjust Trim Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): ADS8519 21 PACKAGE OPTION ADDENDUM www.ti.com 20-Mar-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty ADS8519IBDB ACTIVE SSOP DB 28 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS8519IBDBG4 ACTIVE SSOP DB 28 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS8519IBDBR ACTIVE SSOP DB 28 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS8519IBDBRG4 ACTIVE SSOP DB 28 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS8519IDB ACTIVE SSOP DB 28 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS8519IDBG4 ACTIVE SSOP DB 28 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS8519IDBR ACTIVE SSOP DB 28 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS8519IDBRG4 ACTIVE SSOP DB 28 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 25-Jul-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADS8519IBDBR SSOP DB 28 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 ADS8519IDBR SSOP DB 28 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 25-Jul-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS8519IBDBR SSOP DB 28 2000 346.0 346.0 33.0 ADS8519IDBR SSOP DB 28 2000 346.0 346.0 33.0 Pack Materials-Page 2 MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. 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