MICROSEMI NX2141

NX2141
SINGLE CHANNEL MOBILE PWM CONTROLLER WITH
FEEDFORWARD AND ENABLE
ADVANCE DATA SHEET
Pb Free Product
DESCRIPTION
FEATURES
The NX2141 controller IC is a compact synchronous Buck
controller IC designed for step down DC to DC converter applications with voltage feedforward functionality.
Voltage feedforward provides fast response, good line
regulation and nearly constant power stage gain under
wide voltage input range. The NX2141 controller is optimized to convert single supply up to 24V bus voltage to
as low as 0.8V output voltage. Internal UVLO keeps the
regulator off until the supply voltage exceeds 7V where
internal digital soft starts get initiated to ramp up output.
The NX2141 employs fixed current limiting and FB UVLO
followed by hiccup feature. Other features includes: 5V
gate drive capability , Adaptive dead band control, available in 16 lead MLPQ and 10 lead MSOP package.
n Bus voltage operation from 7V to 24V
n Less than 1uA shutdown current with Enable low
n Excellent dynamic response with input voltage feedforward and voltage mode control
n Internal Digital Soft Start Function
n Fixed internal hiccup current limit
n FB UVLO followed by hiccup feature
n Power Good indicator available
n Start into precharged output
n Pb-free and RoHS compliant
APPLICATIONS
n
n
n
Notebook PC
Graphic Card on board converters
On board DC to DC such as
12V to 3.3V, 2.5V or 1.8V
Set Top Box and LCD Display
n
TYPICAL APPLICATION
1uH
Vin1
+8 to 20V
100uF
1uF
25TQC33M
25V,33uF
MBR0530T1
13
1uF
10
Vin2
+5V
14
1uF
ON
OFF
5
9
12
PGOOD
EN
COMP
2.3k
NX2141
10k
16
8
PVCC VIN
VCC
0.1uF
BST
Hdrv
1
M1
1uH
SW
Vout
+1.05V 10A
15
Co
2*2R5TPE220MC
(220uF,12mohm)
Ldrv
3
M2
1.5k
10k
1nF
15nF
2.2nF
11
FB
Pgnd
2
Gnd
17
32k
Figure1 - Typical application of NX2141(MLPQ)
ORDERING INFORMATION
Device
NX2141CMTR
NX2141CUTR
Rev. 1.6
05/15/07
Temperature
-40o C to 85o C
-40o C to 85o C
Package
MLPQ-16L
MSOP-10L
Frequency
200kHz
200kHz
Pb-Free
Yes
Yes
1
NX2141
ABSOLUTE MAXIMUM RATINGS
VCC to GND & BST to SW voltage ...................... -0.3V to 6.5V
VIN to GND ........................................................ -0.3V to 30V
BST to GND Voltage .......................................... -0.3V to 35V
SW to GND ....................................................... -2V to 35V
All other pins ..................................................... -0.3V to 6.5V
Storage Temperature Range ................................ -65oC to 150oC
Operating Junction Temperature Range ................ -40oC to 125oC
ESD Susceptibility ............................................ 2kV
CAUTION: Stresses above those listed in "ABSOLUTE MAXIMUM RATINGS", may cause permanent damage to
the device. This is a stress only rating and operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
PACKAGE INFORMATION
BST
SW
VCC
PVCC
16-LEAD PLASTIC MLPQ
16
15
14
13
HDRV 1
10-LEAD PLASTIC MSOP
θJA ≈ 200o C/W
12 COMP
PGND 2
11 FB
17
AGND
BST 1
θJA ≈ 46o C/W
HDRV 2
9 EN
LDRV 4
6
7
8
VIN
NC 4
NC
GND 3
NC
10 NC
PGOOD
LDRV 3
5
10 SW
9 COMP
8 FB
7 VCC
6 EN
VIN 5
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over Vcc =5V, VIN=12V and TA = -40oC to 85oC. Typical
values refer to TA = 25oC.
PARAMETER
Reference Voltage
Ref Voltage
Ref Voltage line regulation
Supply Voltage(Vcc)
VCC Voltage Range
Operating quiescent current
Shut down current
Vcc UVLO
VCC-Threshold
VCC-Hysteresis
Supply Voltage(Vin)
Vin Voltage Range
Input Voltage Current
Shut Down Current
Rev. 1.6
05/15/07
SYM
Test Condition
Min
VREF
VCC
IQ
ISD
TYP
MAX
0.8
0.2
4.75
EN=HIGH
EN=LOW
1.5
VCC_UVLO VCC Rising
VCC_Hyst VCC Falling
Vin
Vin=24V
EN=LOW
V
%
5.25
5
1
4.4
0.2
7
24
Units
V
mA
uA
V
V
25
40
1
V
uA
uA
2
NX2141
PARAMETER
Vin UVLO
Vin-Threshold
Vin-Hysteresis
Oscillator (Rt)
Frequency
Frequency Over Vin
Ramp-Amplitude Voltage
Ramp Offset
Ramp/Vin Gain
Max Duty Cycle
Min on time
Error Amplifiers
Transconductance
Input Bias Current
Comp SD threshold
Vref and Soft Start
Soft Start time
High Side Driver
(CL=3300pF)
Output Impedance , Sourcing
Current
Output Impedance , Sinking
Current
Rise Time
Fall Time
Deadband Time
SYM
Vin_UVLO
Vin_Hyst
Test Condition
Min
VCC Rising
VCC Falling
FS
TYP
Vin=20V
V
V
200
KHz
%
V
V
V/V
%
nS
5
2
0.8
0.1
88
150
2500
0.3
umho
nA
V
10
mS
Ib
Tss
100
FS=200kHz
Units
6
0.5
-5
VRAMP
MAX
Rsource(Hdrv)
I=200mA
1
ohm
Rsink(Hdrv)
I=200mA
0.8
ohm
THdrv(Rise)
10% to 90%
THdrv(Fall)
90% to 10%
Tdead(L to Ldrv going Low to Hdrv going
H)
High, 10% to 10%
50
50
30
ns
ns
ns
Rsource(Ldrv)
I=200mA
1
ohm
Rsink(Ldrv)
I=200mA
0.5
ohm
50
50
30
ns
ns
ns
320
mV
Low NSide Driver
(CL=3300pF)
Output Impedance, Sourcing
Current
Output Impedance, Sinking
Current
Rise Time
Fall Time
Deadband Time
Fixed OCP
OCP voltage Threshold
Enable
Enable HI Threshold
Enable LOW Threshold
Rev. 1.6
05/15/07
TLdrv(Rise)
10% to 90%
TLdrv(Fall)
90% to 10%
Tdead(H to SW going Low to Ldrv going
L)
High, 10% to 10%
1.4
0.4
V
V
3
NX2141
PARAMETER
Power Good(MLPQ only)
Threshold Voltage as % of
Vref
Hysteresis
FBUVLO
Feedback UVLO threshold
Over temperature
Threshold
Hysteresis
SYM
Test Condition
Min
FB ramping up
percent of nominal
65
TYP
MAX
Units
90
%
5
%
70
%
75
150
20
°C
°C
PIN DESCRIPTIONS
PIN SYMBOL
VCC
This pin supplies the internal 5V bias circuit. A 1uF ceramic capacitor is placed as
close as possible to this pin and ground pin.
BST
This pin supplies voltage to high side FET driver. A high freq minimum 0.1uF ceramic
capacitor is placed as close as possible to and connected to this pin and SW pin.
GND
Power ground.
FB
This pin is the error amplifiers inverting input. This pin is connected via resistor divider to
the output of the switching regulator to set the output DC voltage.
COMP
This pin is the output of the error amplifier and together with FB pin is used to compensate
the voltage control feedback loop.
SW
This pin is connected to source of high side FETs and provide return path for the high
side driver.
HDRV
High side gate driver output.
LDRV
Low side gate driver output.
EN
VIN
PGOOD
(MLPQ only)
PVCC
Rev. 1.6
05/15/07
PIN DESCRIPTION
Pull up this pin to Vcc for normal operation. Pulling this pin down below 0.4V shuts
down the controller and resets the soft start.
Bus voltage input provides power supply to oscillator and VIN UVLO signal.
An open drain output that requires a pull up resistor to Vcc or a voltage lower than Vcc.
When FB pin reaches 90% of the reference voltage, PGOOD changes from LO to HI
state.
Supply voltage for the low side fet drivers. A high frequency 1uF ceramic cap must be
connected from this pin to the PGND pin as close as possible.
4
NX2141
BLOCK DIAGRAM
PGOOD
FB
0.85Vref
/0.90Vref
Bias
Generator
VCC
1.25V
0.8V
BST
POR
UVLO
VIN
START
6V/
5.5V
HDRV
COMP
0.3V
SW
OC
VIN
Control
Logic
START 0.8V
OSC
Digital
start Up
PWM
PVCC
ramp
S
R
Q
LDRV
DISABLE
OC
PGND
FB
0.6V
CLAMP
COMP
START
POR
1.3V
CLAMP
320mV
Hiccup Logic
OCP
comparator
EN
DISABLE
SS_half_done
70%*Vp
FB
AGND
Figure 2 - Simplified block diagram of the NX2141(MLPQ)
Rev. 1.6
05/15/07
5
NX2141
1uH
Vin1
+8 to 20V
10
100uF
MBR0530T1
0.1uF
13
10
Vin2
+5V
14
1uF
10k
5
9
12
16
8
PVCC VIN BST
VCC
Hdrv
EN
COMP
2.3k
0.1uF
1
M1
1uH
PGOOD
NX2141
1uF
25TQC33M
25V,33uF
1uF
SW
Vout
+1.05V 10A
15
Co
2*2R5TPE220MC
(220uF,12mohm)
Ldrv
3
M2
1.5k
10k
1nF
15nF
2.2nF
11
FB
Pgnd
2
Gnd
17
32k
Figure 3 - Simplified Demo board schematic(MLPQ)
Rev. 1.6
05/15/07
6
NX2141
Figure 4 - Demo board schematic based on ORCAD
Rev. 1.6
05/15/07
7
NX2141
Bill of Materials
Item number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Rev. 1.6
05/15/07
Quantity
4
4
1
2
1
1
1
1
2
1
1
1
1
4
3
1
1
1
1
1
1
1
1
Reference
C1,C5,C6,C18
C2,C4,C7,C9
C3
C19,C8
C10
C13
C14
C15
C17,C16
D1
L2
M1
M2
R1,R2,R3,R11
R4,R6,R14
R5
R8
R10
R12
R13
R15
U1
U2
Part
0.1u
1u
25TQC33M
47u
15nF
1000pF
2.2n
470p
2R5TPE220MC
MBR0530T1
MLC1550-102ML
FDS6294
FDS6676AS
0
10
100k
2.3k
32k
10k
1.5k
1k
NX2141CMTR
L78L05AB/sot89
Manufacturer
SANYO
SANYO
Coilcraft
Fairchildsemi
Fairchildsemi
NEXSEM INC.
8
NX2141
Demoboard waveforms
Figure 5 - Output ripple(CH1 Vout ripple(50mV/
div),CH2 output current(5A/div), CH3 SW(5V/div))
Figure 7 - Enlarged transient response(CH1 Vout
AC(50mV/div), CH2 output current(5A/div))
Figure 6 - Transient response(CH1 Vout
AC(50mV/div), CH2 output current(5A/div))
Figure 8 - Enlarged transient response(CH1 Vout
AC(50mV/div), CH2 output current(5A/div))
Figure 9 - Over Current Protection(CH2 output current(10A/ Figure 10 - Power Good(CH4 Vout(500mV/div), CH3
PGOOD(5V/div))
div), CH4 VOUT(500mV/div))
Rev. 1.6
05/15/07
9
NX2141
Demoboard waveforms(cont'd)
Figure 11 - Step VIN response(CH1 Vout AC(50mV/
div), CH3 VIN(5V/div), CH4 SW(5V/div))
Figure 12 - Enlarged Figure 11 (CH1 Vout AC(50mV/
div), CH3 VIN(5V/div), CH4 SW(5V/div))
Figure 13 - Step into precharged output (CH1 EN (2V/
div), CH3 OUTPUT CURRENT(10A/div), CH4
VOUT(500mV/div))
Figure 14 - Soft start(CH1 EN(2V/div),CH2 output
current(10A/div), CH3 VOUT(500mV/div))
efficinecy vs Iout(VIn=19V)
efficinecy vs Iout(VIn=12V)
86.00%
89.00%
88.00%
84.00%
Efficiency(%)
Efficiency(%)
87.00%
86.00%
85.00%
84.00%
83.00%
82.00%
80.00%
78.00%
82.00%
81.00%
76.00%
80.00%
74.00%
79.00%
0
2
4
6
8
10
Iout(A)
Figure 15 - Efficiency(VIN=12V, VOUT=1V)
Rev. 1.6
05/15/07
12
0
2
4
6
8
10
12
Iout(A)
Figure 16 - Efficiency(VIN=19V, VOUT=1V)
10
NX2141
Current Ripple @ maximum input voltage is
APPLICATION INFORMATION
Symbol Used In Application Information:
VIN
- Input voltage
VOUT
- Output voltage
IOUT
- Output current
- Switching frequency
DIRIPPLE
- Inductor current ripple
IRIPPLE =
=
DVRIPPLE - Output voltage ripple
FS
calculated as
VIN -VOUT VOUT 1
×
×
LOUT
VIN FS
...(2)
20V-1.05V 1.05V
1
×
×
= 4.97A
1uH
20V 200kHz
Output Capacitor Selection
Output capacitor is basically decided by the
amount of the output voltage ripple allowed during steady
state(DC) load condition as well as specification for the
Design Example
load transient. The optimum design may require a couple
Power stage design requirements:
VINMAX=20V
of iterations to satisfy both condition.
Based on DC Load Condition
The amount of voltage ripple during the DC load
VOUT=1.05V
condition is determined by equation(3).
VINMIN=8V
IOUT_max =10A
∆VRIPPLE = ESR × ∆IRIPPLE +
DVRIPPLE <=30mV
DVTRAN<=50mV @ 5A step
∆IRIPPLE
8 × FS × COUT ...(3)
Where ESR is the output capacitors' equivalent
FS=200kHz
series resistance,COUT is the value of output capacitors.
Typically when large value capacitors are selected
Output Inductor Selection
such as Aluminum Electrolytic,POSCAP and OSCON
The selection of inductor value is based on induc-
types are used, the amount of the output voltage ripple
tor ripple current, power rating, working frequency and
is dominated by the first term in equation(3) and the
efficiency. Larger inductor value normally means smaller
second term can be neglected.
ripple current. However if the inductance is chosen too
For this example, POSCAP are chosen as output
large, it brings slow response and lower efficiency. Usu-
capacitors, the ESR and inductor current typically de-
ally the ripple current ranges from 20% to 40% of the
termines the output voltage ripple.
output current. This is a design freedom which can be
decided by design engineer according to various appli-
ESR desire =
cation requirements. The inductor value can be calcu-
IRIPPLE =k × IOUTPUT
...(4)
If low ESR is required, for most applications, mul-
lated by using the following equations:
V
-V
V
1
LOUT = INMAX OUT × OUT ×
IRIPPLE
VINMAX FS
∆VRIPPLE 30mV
=
= 6m Ω
∆IRIPPLE
4.97A
tiple capacitors in parallel are better than a big capacitor. For example, for 30mV output ripple, POSCAP
...(1)
where k is between 0.2 to 0.4.
Select k=0.4, then
2R5TPE220MC with 12mΩ are chosen.
N =
E S R E × ∆ IR I P P L E
∆ VR IPPLE
...(5)
Number of Capacitor is calculated as
20V-1.05V 1.05V
1
LOUT =
×
×
0.4 ×10A
20V 200kHz
LOUT =1.2uH
In this application we choose L OUT=1uH, then
coilcraft inductor MLC1550-102MLC is a good choice.
N=
12mΩ× 4.97A
30mV
N =2
The number of capacitor has to be round up to a
integer. Choose N =2.
Rev. 1.6
05/15/07
11
NX2141
If ceramic capacitors are chosen as output ca-
The above equation shows that if the selected out-
pacitors, both terms in equation (3) need to be evalu-
put inductor is smaller than the critical inductance, the
ated to determine the overall ripple. Usually when this
voltage droop or overshoot is only dependent on the ESR
type of capacitors are selected, the amount of capaci-
of output capacitor. For low frequency capacitor such
tance per single unit is not sufficient to meet the tran-
as electrolytic capacitor, the product of ESR and ca-
sient specification, which results in parallel configura-
pacitance is high and L ≤ L crit is true. In that case, the
tion of multiple capacitors.
transient spec is mostly like to dependent on the ESR
For example, two 100uF, X5R ceramic capacitor
with 2mΩ ESR is used. The amount of output ripple is
of capacitor.
Most case, the output capacitor is multiple capacitor in parallel. The number of capacitor can be calcu-
4.97A
8 × 200kHz × 200uF
= 5mV + 15mV = 20mV
∆VRIPPLE = 1mΩ× 4.97A +
lated by the following
Two ceramic capacitors are needed. Although this
can meet DC ripple spec, however it needs to be studied for transient requirement.
Based On Transient Requirement
Typically, the output voltage droop during transient
is specified as
∆V droop < ∆V tran @step load DISTEP
During the transient, the voltage droop during the
N=
ESR E × ∆Istep
∆Vtran
+
VOUT
× τ2
2 × L × C E × ∆Vtran
...(9)
where
0 if L ≤ L crit

τ =  L × ∆Istep
− ESR E × CE
 V
 OUT
if
L ≥ L crit
...(10)
For example, assume voltage droop during tran-
transient is composed of two sections. One section is
sient is 50mV for 5A load step.
dependent on the ESR of capacitor, the other section is
If the POSCAP 2R5TPE220MC(220uF, 12mohm
ESR) is used, the crticial inductance is given as
a function of the inductor, output capacitance as well
as input, output voltage. For example, for the over-
Lcrit =
shoot when load from high load to light load with a
DISTEP transient load, if assuming the bandwidth of
12mΩ× 220µF ×1.05V
= 0.55µH
5A
system is high enough, the overshoot can be estimated as the following equation.
∆Vovershoot
VOUT
= ESR × ∆Istep +
× τ2
2 × L × COUT
...(6)
where τ is the a function of capacitor,etc.
0 if L ≤ L crit

τ =  L × ∆Istep
− ESR × COUT
 V
 OUT
if
L ≥ L crit
...(7)
where
L crit =
ESR × COUT × VOUT ESR E × C E × VOUT
=
...(8)
∆Istep
∆Istep
where ESRE and CE represents ESR and capacitance of each capacitor if multiple capacitors are used
in parallel.
Rev. 1.6
05/15/07
ESR E × CE × VOUT
=
∆Istep
The selected inductor is 1uH which is bigger than
critical inductance. In that case, the output voltage transient not only dependent on the ESR, but also capacitance.
number of capacitor is
τ=
=
N=
L × ∆ I step
VOUT
− ESR E × C E
1µH × 5A
− 12m Ω × 220µF = 2.12us
1.05V
ESR E × ∆ I step
∆ Vtran
+
VOUT
× τ2
2 × L × C E × ∆ Vtran
12m Ω × 5A
1.05V
=
+
× (2.12us) 2
53mV
2 × 1µH × 220µ F × 53mV
= 1.35
12
NX2141
The number of capacitors has to satisfy both ripple
and transient requirement. Overall, we choose N=2.
It should be considered that the proposed equa-
sate the system with type III compensator. The following figures and equations show how to realize the type III
compensator by transconductance amplifier.
tion is based on ideal case, in reality, the droop or overshoot is typically more than the calculation. The equation gives a good start. For more margin, more capacitors have to be chosen after the test. Typically, for high
frequency capacitor such as high quality POSCAP especially ceramic capacitor, 20% to 100% (for ceramic)
more capacitors have to be chosen since the ESR of
capacitors is so low that the PCB parasitic can affect
the results tremendously. More capacitors have to be
FZ1 =
1
2 × π × R 4 × C2
...(11)
FZ2 =
1
2 × π × (R 2 + R3 ) × C3
...(12)
FP1 =
1
2 × π × R3 × C3
...(13)
FP2 =
1
2 × π × R4 ×
selected to compensate these parasitic parameters.
Compensator Design
Due to the double pole generated by LC filter of the
power stage, the power system has 180o phase shift ,
and therefore, is unstable by itself. In order to achieve
accurate output voltage and fast transient response,
compensator is employed to provide highest possible
bandwidth and enough phase margin. Ideally, the Bode
plot of the closed loop system has crossover frequency
between 1/10 and 1/5 of the switching frequency, phase
...(14)
C1 × C2
C1 + C2
where FZ1,FZ2,FP1 and FP2 are poles and zeros in
the compensator.
The transfer function of type III compensator for
transconductance amplifier is given by:
Ve
1 − gm × Z f
=
VOUT
1 + gm × Zin + Z in / R1
For the voltage amplifier, the transfer function of
compensator is
20dB/decade. Power stage output capacitors usually
Ve
−Z f
=
VOUT
Zin
decide the compensator type. If electrolytic capacitors
To achieve the same effect as voltage amplifier,
are chosen as output capacitors, type II compensator
the compensator of transconductance amplifier must
can be used to compensate the system, because the
satisfy this condition: R4>>2/gm. And it would be desir-
zero caused by output capacitor ESR is lower than cross-
able if R1||R2||R3>>1/gm can be met at the same time.
margin greater than 50o and the gain crossing 0dB with -
over frequency. Otherwise type III compensator should
be chosen.
Voltage feedforward compensation is used in
Zin
Zf
C1
Vout
NX2141 to compensate the output voltage variation
caused by input voltage changing. The feedforward funtion
R3
R2
is realized by using VIN pin voltage to program the oscillator ramp voltage VOSC=0.1VIN, which provides nearly
C3
C2
R4
Fb
constant power stage gain under wide voltage input range.
gm
Ve
R1
A. Type III compensator design
Vref
For low ESR output capacitors, typically such as
Sanyo oscap and poscap, the frequency of ESR zero
caused by output capacitors is higher than the crossover frequency. In this case, it is necessary to compen-
Rev. 1.6
05/15/07
Figure 17 - Type III compensator using
transconductance amplifier
13
NX2141
Case 1:
FLC<FO<FESR(for most ceramic or low
ESR POSCAP, OSCON)
2. Set R4 equal to 2.5kΩ.
3. Calculate C2 with zero Fz1 at 75% of the LC
Gain(db)
double pole by equation (11).
1
2 × π × FZ1 × R 4
C2 =
power stage
FLC
1
2 × π × 0.75 × 7.59kHz × 2.5k Ω
= 11nF
=
40dB/decade
Choose C2=15nF.
4. Calculate C 1 by equation (14) with pole F p2 at
loop gain
FESR
20dB/decade
one third of the switching frequency.
1
2 × π × R 4 × FP2
C1 ≈
1
2 × π × 2.5k Ω × 66.7kHz
≈ 959pF
≈
compensator
Choose C1=1nF.
FZ1 FZ2
FO FP1
FP2
Figure 18 - Bode plot of Type III compensator
(FLC<FO<FESR)
Typical design example of type III compensator in
which the crossover frequency is selected as
FLC<FO<FESR and FO<1/10 is shown as the following
steps.
1. Calculate the location of LC double pole F LC
and ESR zero FESR.
FLC =
=
1
2 × π × L OUT × C OUT
1
2 × π × 1uH × 440uF
= 7.59kHz
FESR =
1
2 × π × ESR × C OUT
1
2 × π × 6m Ω × 440uF
= 60.3kHz
=
5. Calculate C 3 with the crossover frequency F O at
15kHz.
C3 =
VOSC 2 × π × FO × L × C OUT
×
VIN
R4
1 2 × π × 15kHz × 1uH × 440uF
×
10
2.5k Ω
=1.7nF
=
Choose C3=2.2nF.
6. Calculate R3 by equation (13) with Fp1 =FESR.
R3 =
1
2 × π × FP1 × C3
1
2 × π × 60.3kHz × 2.2nF
= 1.2kΩ
=
Choose R3 =1.5kΩ.
7. Calculate R2 by setting compensator zero FZ2
at the LC double pole.
R2 =
1
1
1
)
×(
−
2 × π × C3 FZ2 FP1
1
1
1
×(
−
)
2 × π × 2.2nF 7.59kHz 60.3kHz
= 8.35k Ω
=
Choose R2 =10kΩ.
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14
NX2141
8. Calculate R1 .
R1=
FESR =
R 2 × VREF
10k Ω × 0.8V
=
= 32k Ω
VOUT -VREF
1.05V-0.8V
1
2 × π × ESR × COUT
1
2 × π × 9m Ω × 2000uF
= 8.8kHz
=
Choose R1=32kΩ.
2. Set R4 equal to 2.5kΩ.
Case 2:
FLC<FESR<FO(for electrolytic capacitors)
3. Calculate C2 with zero Fz1 at 75% of the LC
Gain(db)
double pole by equation (11).
power stage
FLC
C2 =
40dB/decade
1
2 × π × FZ1 × R 4
1
2 × π × 0.75 × 2.4kHz × 2.5k Ω
= 35nF
=
FESR
Choose C2=33nF.
loop gain
4. Calculate C 1 by equation (14) with pole F p2 at
one third of the switching frequency.
20dB/decade
C1 ≈
compensator
1
2 × π × R 4 × FP2
1
2 × π × 2.5k Ω × 66.7kHz
≈ 959pF
≈
FZ1 FZ2 FP1 FO
FP2
Figure 19- Bode plot of Type III compensator
(FLC<FESR<FO)
If electrolytic capacitors are used as output
capacitors, typical design example of type III
compensator in which the crossover frequency is
selected as FLC<FESR<FO and FO<1/10Fs is shown as
the following steps. Here two SANYO MV-WF1000 with
18 mΩ is chosen as output capacitor, output inductor is
2.2uH, output voltage is 1.05V, switching frequency is
200kHz.
1. Calculate the location of LC double pole F LC
and ESR zero FESR.
FLC =
=
5. Calculate R 3 with the crossover frequency F O at
15kHz.
R3 =
VIN
ESR × R 4
×
VOSC 2 × π × FO × L
9mohm × 2.5kΩ
2 × π × 15kHz × 1uH
=1.08kΩ
=10 ×
Choose R3=1.2kΩ.
6. Calculate C3 by equation (13) with Fp1 =FESR.
C3 =
1
2 × π × FP1 × R3
1
2 × π × 8.8kHz × 1.2k Ω
= 14nF
=
1
2 × π × LOUT × COUT
1
2 × π × 2.2uH × 2000uF
= 2.4kHz
Rev. 1.6
05/15/07
Choose C1=1nF.
Choose C3 =15nF.
7. Calculate R2 by setting compensator zero FZ2
at the LC double pole.
15
NX2141
R2 =
1
1
1
×(
−
)
2 × π × C3
FZ2 FP1
1
1
1
×(
−
)
2 × π × 15nF
2.4kHz 8.8kHz
= 3.2k Ω
=
The following equations show the compensator pole zero
location and constant gain.
Gain=gm ×
Fz =
Choose R2 =4kΩ.
8. Calculate R1 .
R × VREF
4k Ω × 0.8V
R1 = 2
=
= 12.8k Ω
VOUT -VREF 1.05V-0.8V
Choose R1=12.7kΩ.
R1
× R3
R1 +R 2
1
2 × π × R3 × C1
1
2 × π × R 3 × C2
Fp ≈
...(15)
... (16)
... (17)
Vout
B. Type II compensator design
R2
Fb
If the electrolytic capacitors are chosen as power
stage output capacitors, usually the Type II compensator can be used to compensate the system.
gm
R1
R3
Vref
For this type of compensator, FO has to satisfy
Ve
C2
FLC<FESR<<FO<1/10Fs.
C1
power stage
Gain(db)
Figure 21 - Type II compensator with
transconductance amplifier
40dB/decade
The following is parameters for type II compensa-
loop gain
tor design. Input voltage is 12V, output voltage is 2.5V,
20dB/decade
output inductor is 2.2uH, output capacitors are two 680uF
with 41mΩ electrolytic capacitors.
1.Calculate the location of LC double pole F LC
and ESR zero FESR.
compensator
Gain
FLC =
1
2 × π × L OUT × COUT
1
=
FZ FLC FESR
FO FP
Figure 20 - Bode plot of Type II compensator
Type II compensator can also be realized by simple
RC circuit without feedback as shown in figure 15. R3
2 × π × 2.2uH × 1360uF
= 2.9kHz
FESR =
1
2 × π × ESR × COUT
1
2 × π × 20.5m Ω × 1360uF
= 5.7kHz
=
and C1 introduce a zero to cancel the double pole effect.
C2 introduces a pole to suppress the switching noise.
Rev. 1.6
05/15/07
16
NX2141
1.Set R2 equal to10kΩ. Using equation 18, the final selection of R1 is 4.7kΩ.
2. Set crossover frequency at 1/20 of the
Vout
R2
swithing frequency, here FO=10kHz.
Fb
3.Calculate R3 value by the following equation.
V
2 × π × FO × L 1 VOUT
R3 = OSC ×
×
×
Vin
RESR
gm VREF
1 2 × π × 10kHz × 2.2uH
1
×
×
10
20.5mΩ
2.5mA/V
2.5V
×
0.8V
=0.8kΩ
R1
Vref
Figure 22 - Voltage divider
=
R 2 × VR E F
V O U T -V R E F
...(18)
where R2 is part of the compensator, and the value
Choose R3 =1kΩ.
4. Calculate C1 by setting compensator zero FZ
at 75% of the LC double pole.
1
2 × π × R 3 × Fz
C1 =
R 1=
1
2 × π × 1k Ω × 0.75 × 2.9kHz
=70nF
=
of R1 value can be set by voltage divider.
Input Capacitor Selection
Input capacitors are usually a mix of high frequency
ceramic capacitors and bulk capacitors. Ceramic capacitors bypass the high frequency noise, and bulk capacitors supply switching current to the MOSFETs. Usually 1uF ceramic capacitor is chosen to decouple the
Choose C1=68nF.
high frequency noise.The bulk input capacitors are de-
5. Calculate C2 by setting compensator pole Fp
cided by voltage rating and RMS current rating. The RMS
at half the swithing frequency.
C
2
=
1
π × R
3
× Fs
1
π × 1k Ω × 3 0 0 k H z
=530pF
=
Choose C2=560pF.
Output Voltage Calculation
Output voltage is set by reference voltage and external voltage divider. The reference voltage is fixed at
0.8V. The divider consists of two ratioed resistors so
current in the input capacitors can be calculated
as:
IRMS = IOUT × D × 1- D
D=
VOUT
VINMIN
...(19)
VINMIN = 8V, VOUT=1.05V, IOUT=10A, the result of
input RMS current is 3.4A.
For higher efficiency, low ESR capacitors are
recommended. One Sanyo OSCON CAP 25SVP56M
25V 56uF 28mΩ with 3.8A RMS rating are chosen as
input bulk capacitors.
that the output voltage applied at the Fb pin is 0.8V when
the output voltage is at the desired value. The following
equation applies to figure 22, which shows the relationship between
Rev. 1.6
05/15/07
VOUT , VREF and voltage divider..
17
NX2141
Power MOSFETs Selection
The NX2141 requires two N-Channel power
This power dissipation should not exceed maximum power dissipation of the driver device.
MOSFETs. The selection of MOSFETs is based on
maximum drain source voltage, gate source voltage,
Over Current Limit Protection
maximum current rating, MOSFET on resistance and
Over current Limit for step down converter is
power dissipation. The main consideration is the power
achieved by sensing current through the low side
loss contribution of MOSFETs to the overall converter
efficiency. For example, two IRF7822 are used in application. They have the following parameters: VDS=30V, ID
MOSFET. For NX2141, the current limit is decided by
=18A,RDSON =6.5mΩ,QGATE =44nC.
the over current occurs. The over current limit can be
There are two factors causing the MOSFET power
Conduction loss is simply defined as:
PHCON =IOUT × D × RDS(ON) × K
...(20)
where the RDS(ON) will increases as MOSFET junction temperature increases, K is RDS(ON) temperature
dependency. As a result, RDS(ON) should be selected for
the worst case, in which K approximately equals to 1.4
at 125oC according to datasheet. Conduction loss should
not exceed package rating or overall system thermal
budget.
ISET =
320mV
320mV
=
= 35A
RDSON 1.4 × 6.5mΩ
Layout Considerations
The layout is very important when designing high
frequency switching converters. Layout will affect noise
pickup and can cause a good design to perform with
less than expected results.
There are two sets of components considered in
the layout which are power components and small sig-
Switching loss is mainly caused by crossover
conduction at the switching transition. The total
nal components. Power components usually consist of
input capacitors, high-side MOSFET, low-side MOSFET,
switching loss can be approximated.
inductor and output capacitors. A noisy environment is
1
PSW = × VIN × IOUT × TSW × FS
...(21)
2
where IOUT is output current, TSW is the sum of TR
and TF which can be found in mosfet datasheet, and FS
is switching frequency. Swithing loss PSW is frequency
dependent.
Also MOSFET gate driver loss should be considered when choosing the proper power MOSFET.
MOSFET gate driver loss is the loss generated by discharging the gate capacitor and is dissipated in driver
circuits.It is proportional to frequency and is defined as:
Pgate = (QHGATE × VHGS + QLGATE × VLGS ) × FS
calculated by the following equation.
The MOSFET RDSON is calculated in the worst case
situation, then the current limit for MOSFET IRF7822 is
2
PTOTAL =PHCON + PLCON
FET is on, and the voltage on SW pin is below 320mV,
ISET = 320mV/R DSON
loss:conduction loss, switching loss.
PLCON =IOUT 2 × (1 − D) × RDS(ON) × K
the RDSON of the low side mosfet. When synchronous
...(22)
generated by the power components due to the switching power. Small signal components are connected to
sensitive pins or nodes. A multilayer layout which includes power plane, ground plane and signal plane is
recommended .
Layout guidelines:
1. First put all the power components in the top
layer connected by wide, copper filled areas. The input
capacitor, inductor, output capacitor and the MOSFETs
should be close to each other as possible. This helps to
reduce the EMI radiated by the power loop due to the
high switching currents through them.
where QHGATE is the high side MOSFETs gate
2. Low ESR capacitor which can handle input RMS
charge,QLGATE is the low side MOSFETs gate charge,VHGS
ripple current and a high frequency decoupling ceramic
is the high side gate source voltage, and VLGS is the low
cap which usually is 1uF need to be practically touch-
side gate source voltage.
Rev. 1.6
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NX2141
ing the drain pin of the upper MOSFET, a plane connection is a must.
3. The output capacitors should be placed as close
as to the load as possible and plane connection is required.
4. Drain of the low-side MOSFET and source of
the high-side MOSFET need to be connected thru a plane
ans as close as possible. A snubber nedds to be placed
as close to this junction as possible.
5. Source of the lower MOSFET needs to be connected to the GND plane with multiple vias. One is not
enough. This is very important. The same applies to the
output capacitors and input capacitors.
6. Hdrv and Ldrv pins should be as close to
MOSFET gate as possible. The gate traces should be
wide and short. A place for gate drv resistors is needed
to fine tune noise if needed.
7. Vcc capacitor, BST capacitor or any other bypassing capacitor needs to be placed first around the IC
and as close as possible. The capacitor on comp to
GND or comp back to FB needs to be place as close to
the pin as well as resistor divider.
8. The output sense line which is sensing output
back to the resistor divider should not go through high
frequency signals.
9. All GNDs need to go directly thru via to GND
plane.
10. The feedback part of the system should be
kept away from the inductor and other noise sources,
and be placed close to the IC.
11. In multilayer PCB, separate power ground and
analog ground. These two grounds must be connected
together on the PC board layout at a single point. The
goal is to localize the high current path to a separate
loop that does not interfere with the more sensitive analog control function.
Rev. 1.6
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NX2141
MLPQ 16 PIN 3 x 3 PACKAGE OUTLINE DIMENSIONS
NOTE: ALL DIMENSIONS ARE DISPLAYED IN MILLIMETERS.
Rev. 1.6
05/15/07
20
NX2141
MLPQ 16 PIN 3 x 3 TAPE AND REEL INFORMATION
NOTE:
1. R7 = 7 INCH LOCK REEL, R13 = 13 INCH LOCK REEL.
2. ALL DIMENSIONS ARE DISPLAYED IN MILLIMETERS.
Rev. 1.6
05/15/07
21