MMDF3N06VL Power MOSFET 3 Amps, 60 Volts N−Channel SO−8, Dual Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. VDSS RDS(ON) TYP ID MAX Features 60 V 130 mΩ 3.0 A http://onsemi.com • On−resistance Area Product about One−half that of Standard • • • • • • MOSFETs with New Low Voltage, Low RDS(on) Technology Faster Switching than E−FET Predecessors Avalanche Energy Specified IDSS and VDS(on) Specified at Elevated Temperature Static Parameters are the Same for both TMOS V and TMOS E−FET Miniature SO−8 Surface Mount Package − Saves Board Space Mounting Information for SO−8 Package Provided N−Channel D G S MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Symbol Value Unit Drain−to−Source Voltage VDSS 60 Vdc Drain−to−Gate Voltage, (RGS = 1 MΩ) VDGR 60 Vdc Gate−to−Source Voltage − Continuous VGS ± 15 Vdc ID ID Adc IDM 3.3 0.7 10 PD 2.0 W TJ, Tstg −55 to 150 °C EAS 54 mJ Rating Drain Current − Continuous @ TA = 25°C Drain Current − Continuous @ TA = 100°C Drain Current − Single Pulse (tp ≤ 10 s) Total Power Dissipation @ TA = 25°C (Note 1) Operating and Storage Temperature Range Single Pulse Drain−to−Source Avalanche Energy − Starting TJ = 25°C (VDD = 25 Vdc, VGS = 5.0 Vdc, Peak IL = 3.3 Apk, L = 10 mH, RG = 25 Ω) Thermal Resistance, Junction to Ambient (Note 1) Maximum Lead Temperature for Soldering Purposes, 0.0625″ from case for 10 seconds MARKING DIAGRAM 8 8 1 3N06V ALYW SO−8 CASE 751 STYLE 11 1 Apk A L Y W = Assembly Location = Wafer Lot = Year = Work Week PIN ASSIGNMENT RθJA 62.5 °C/W TL 260 °C Source−1 1 8 Drain−1 Gate−1 2 7 Drain−1 Source−2 3 6 Drain−2 Gate−2 4 5 Drain−2 Top View 1 Mounted on G10/FR4 glass epoxy board using minimum recommended footprint. ORDERING INFORMATION Device Package Shipping† MMDF3N06VLR2 SO−8 2500 Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2004 April, 2004 − Rev. 2 1 Publication Order Number: MMDF3N06VL/D MMDF3N06VL ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) Symbol Characteristic Min Typ Max Unit 60 − − 66 − − − − − − 10 100 − − 100 1.0 − 1.5 3.0 2.0 − − 0.12 0.13 − − − − 0.5 0.4 gFS 1.0 3.0 − Mhos Ciss − 340 480 pF Coss − 110 150 Crss − 27 50 td(on) − 10 20 tr − 30 60 td(off) − 32 60 tf − 28 60 QT − 9.0 20 Q1 − 1.5 − Q2 − 4.3 − Q3 − 3.5 − VSD − − 0.84 0.67 1.2 − Vdc trr − 58 − ns ta − 38 − tb − 20 − QRR − 0.11 − OFF CHARACTERISTICS V(BR)DSS Drain−to−Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150°C) IDSS Gate−Body Leakage Current (VGS = ± 15 Vdc, VDS = 0 Vdc) IGSS Vdc mV/°C Adc nAdc ON CHARACTERISTICS (Note 1) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) VGS(th) Static Drain−to−Source On−Resistance (VGS = 5.0 Vdc, ID = 3.3 Adc) RDS(on) Drain−to−Source On−Voltage (VGS = 5.0 Vdc, ID = 3.3 Adc) (VGS = 5.0 Vdc, ID = 1.65 Adc, TJ = 150°C) VDS(on) Forward Transconductance (VDS = 15 Vdc, ID = 1.65 Adc) Vdc mV/°C Vdc DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 25 Vdc, Vd VGS = 0 Vdc, Vd f = 1.0 MHz) Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2) Turn−On Delay Time Rise Time Turn−Off Delay Time (VDD = 30 Vdc, ID = 3.3 Adc, VGS = 5.0 5 0 Vdc, Vdc RG = 9.1 Ω) Fall Time Gate Charge (VDS = 48 Vdc, ID = 3.3 Adc, VGS = 5.0 Vdc) ns nC SOURCE−DRAIN DIODE CHARACTERISTICS Forward On−Voltage (Note 1) (IS = 3.3 Adc, VGS = 0 Vdc) (IS = 3.3 Adc, VGS = 0 Vdc, TJ = 150°C) Reverse Recovery Time (IS = 3.3 3 3 Adc, Adc VGS = 0 Vdc, Vdc dIS/dt = 100 A/µs) Reverse Recovery Storage Charge 1. Pulse Test: Pulse Width ≤ 300 s, Duty Cycle ≤ 2%. 2. Switching characteristics are independent of operating junction temperature. http://onsemi.com 2 C MMDF3N06VL PACKAGE DIMENSIONS SO−8 CASE 751−07 ISSUE AB NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. −X− A 8 5 0.25 (0.010) S B 1 Y M M 4 K −Y− G C N DIM A B C D G H J K M N S X 45 SEATING PLANE −Z− 0.10 (0.004) H D 0.25 (0.010) M Z Y S X M J S STYLE 11: PIN 1. 2. 3. 4. 5. 6. 7. 8. SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 3 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0 8 0.25 0.50 5.80 6.20 SOURCE 1 GATE 1 SOURCE 2 GATE 2 DRAIN 2 DRAIN 2 DRAIN 1 DRAIN 1 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 8 0.010 0.020 0.228 0.244 MMDF3N06VL E−FET is a trademark of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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