ONSEMI NTP65N02R

NTB65N02R, NTP65N02R
Power MOSFET
65 A, 24 V N−Channel
TO−220, D2PAK
Features
•
•
•
•
•
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Planar HD3e Process for Fast Switching Performance
Low RDSon to Minimize Conduction Loss
Low Ciss to Minimize Driver Loss
Low Gate Charge
Pb−Free Packages are Available*
V(BR)DSS
RDS(on) TYP
ID MAX
24 V
8.4 m @ 10 V
65 A
D
MAXIMUM RATINGS (TJ = 25°C Unless otherwise specified)
Parameter
G
Symbol
Value
Unit
Drain−to−Source Voltage
VDSS
25
Vdc
Gate−to−Source Voltage − Continuous
VGS
±20
Vdc
Thermal Resistance − Junction−to−Case
Total Power Dissipation @ TC = 25°C
Drain Current −
Continuous @ TC = 25°C, Chip
Continuous @ TC =25°C, Limited by Package
Single Pulse (tp = 10 s)
RJC
PD
2.0
62.5
°C/W
W
ID
ID
IDM
65
58
160
A
A
A
Thermal Resistance −
Junction−to−Ambient (Note 1)
Total Power Dissipation @ TA = 25°C
Drain Current − Continuous @ TA = 25°C
RJA
PD
ID
67
1.86
10
°C/W
W
A
Thermal Resistance −
Junction−to−Ambient (Note 2)
Total Power Dissipation @ TA = 25°C
Drain Current − Continuous @ TA = 25°C
RJA
PD
ID
120
1.04
7.6
°C/W
W
A
TJ and
Tstg
−55 to
150
°C
Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ = 25°C
(VDD = 50 Vdc, VGS = 10 Vdc, IL = 11 Apk,
L = 1 mH, RG = 25 )
EAS
60
mJ
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from Case for 10 Seconds
TL
Operating and Storage Temperature Range
4
1
2
TO−220AB
CASE 221A
STYLE 5
P65N02RG
AYWW
3
4
2
1 3
D2PAK
CASE 418AA
STYLE 2
65N02RG
AYWW
65N02R = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
°C
260
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
May, 2005 − Rev. 6
MARKING
DIAGRAMS
1
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. When surface mounted to an FR4 board using 1 in. pad size, (Cu Area 1.127 in2).
2. When surface mounted to an FR4 board using minimum recommended pad
size, (Cu Area 0.412 in2).
 Semiconductor Components Industries, LLC, 2005
S
PIN ASSIGNMENT
PIN
FUNCTION
1
Gate
2
Drain
3
Source
4
Drain
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
Publication Order Number:
NTB65N02R/D
NTB65N02R, NTP65N02R
ELECTRICAL CHARACTERISTICS (TJ = 25°C Unless otherwise specified)
Characteristics
Symbol
Drain−to−Source Breakdown Voltage (Note 3)
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)
V(BR)DSS
Min
Typ
Max
Unit
24
−
27.5
25.5
−
−
−
−
−
−
1.5
10
−
−
±100
1.0
−
1.5
4.1
2.0
−
−
−
−
11.2
8.4
8.2
12.5
10.5
−
−
27
−
Ciss
−
948
1330
Coss
−
456
640
Crss
−
160
225
td(on)
−
7.0
−
tr
−
53
−
td(off)
−
14
−
tf
−
10
−
QT
−
9.5
−
Q1
−
3.0
−
Q2
−
4.4
−
VSD
−
−
−
0.88
1.10
0 80
0.80
1.2
−
−
Vdc
trr
−
29.1
−
ns
ta
−
13.6
−
tb
−
15.5
−
QRR
−
0.02
−
OFF CHARACTERISTICS
Zero Gate Voltage Drain Current
(VDS = 20 Vdc, VGS = 0 Vdc)
(VDS = 20 Vdc, VGS = 0 Vdc, TJ = 150°C)
IDSS
Gate−Body Leakage Current
(VGS = ±20 Vdc, VDS = 0 Vdc)
IGSS
Vdc
mV/°C
Adc
nAdc
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage (Note 3)
(VDS = VGS, ID = 250 Adc)
Threshold Temperature Coefficient (Negative)
VGS(th)
Static Drain−to−Source On−Resistance (Note 3)
(VGS = 4.5 Vdc, ID = 15 Adc)
(VGS = 10 Vdc, ID = 20 Adc)
(VGS = 10 Vdc, ID = 30 Adc)
RDS(on)
Forward Transconductance (Note 3)
(VDS = 10 Vdc, ID = 15 Adc)
Vdc
mV/°C
m
gFS
Mhos
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
((VDS = 20 Vdc, VGS = 0 V,, f = 1 MHz))
Transfer Capacitance
pF
SWITCHING CHARACTERISTICS (Note 4)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
(VGS = 10 Vdc, VDD = 10 Vdc,
ID = 30 Adc, RG = 3)
Fall Time
Gate Charge
(VGS = 4.5 Vdc, ID = 30 Adc,
VDS = 10 Vdc) (Note 3)
ns
nC
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage
(IS = 20 Adc, VGS = 0 Vdc) (Note 3)
((IS = 30 Adc, VGS = 0 Vdc)
(IS = 15 Adc, VGS = 0 Vdc, TJ = 125°C)
Reverse Recovery Time
(IS = 30 Adc
d , VGS = 0 Vdc
d ,
dIS/dt = 100 A/s)
) (Note
(
3))
Reverse Recovery Stored
Charge
3. Pulse Test: Pulse Width 300 s, Duty Cycle 2%.
4. Switching characteristics are independent of operating junction temperatures.
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2
C
NTB65N02R, NTP65N02R
120
VGS = 10 V
80
VDS 10 V
VGS = 4.5 V
VGS = 8.0 V
VGS = 6.0 V
100
100
ID, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
120
VGS = 4.0 V
VGS = 5.5 V
VGS = 5.0 V
60
VGS = 3.5 V
40
VGS = 3.0 V
20
80
60
40
TJ = 25°C
20
VGS = 2.5 V
0
0
2
4
6
8
TJ = 150°C
10
0
1
0.02
TJ = 150°C
0.012
TJ = 25°C
TJ = −55°C
0.004
10
20
30
40
50
60
70
80
90
100 110 120
6
5
0.028
VGS = 4.5 V
0.024
0.02
TJ = 150°C
TJ = 125°C
0.016
TJ = 25°C
0.012
TJ = −55°C
0.008
0.004
10
20
30
40
50
60
70
80
90 100 110 120
ID, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
Figure 3. On−Resistance versus Drain Current
and Temperature
Figure 4. On−Resistance versus Drain Current
and Temperature
10000
1.8
ID = 30 A
VGS = 4.5 V and 10 V
TJ = 150°C
IDSS, LEAKAGE (nA)
1.6
RDS(on), DRAIN−TO−SOURCE RESISTANCE ()
0.024
RDS(on), DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
RDS(on), DRAIN−TO−SOURCE RESISTANCE ()
VGS = 10 V
TJ = 125°C
3
Figure 2. Transfer Characteristics
0.028
0.008
2
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 1. On−Region Characteristics
0.016
TJ = −55°C
0
1.4
1.2
1.0
1000
TJ = 125°C
100
TJ = 100°C
0.8
0.6
−50
10
−25
0
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (°C)
0
5
10
15
20
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
versus Voltage
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3
25
NTB65N02R, NTP65N02R
VDS = 0 V
VGS = 0 V
VGS, GATE−TO−SOURCE VOLTAGE (V)
Ciss
TJ = 25°C
C, CAPACITANCE (pF)
1600
1200
Ciss
Crss
800
Coss
400
Crss
0
10
5
VGS
0
5
VDS
10
15
20
5
QT
QGS
QGD
8
VGS
3
6
2
4
1
0
2
ID = 30 A
TJ = 25°C
2
0
4
8
6
10
12
Figure 8. Gate−to−Source and Drain−to−Source
Voltage versus Total Charge
Figure 7. Capacitance Variation
1000
60
IS, SOURCE CURRENT (A)
VDS = 10 V
ID = 30 A
VGS = 10 V
100
tr
td(off)
tf
10
td(on)
50
40
30
20
TJ = 150°C
10
TJ = 25°C
0
1
1
10
100
0
RG, GATE RESISTANCE ()
0.2
0.4
ID, DRAIN CURRENT (A)
0.8
1
Figure 10. Diode Forward Voltage versus
Current
1000
VGS = 20 V
SINGLE PULSE
TC = 25°C
100
10 s
100 s
10
1 ms
10 ms
dc
RDS(ON) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1
0.6
VSD, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 9. Resistive Switching Time Variation
versus Gate Resistance
1
1
10
100
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 11. Maximum Rated Forward Biased Safe Operating Area
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4
0
Qg, TOTAL GATE CHARGE (nC)
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE
(V)
t, TIME (ns)
10
VDS
4
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
2000
r(t), EFFECTIVE TRANSIENT THERMAL
RESISTANCE (NORMALIZED)
NTB65N02R, NTP65N02R
1
D = 0.5
0.2
0.1
0.05
0.01
SINGLE PULSE
0.1
0.0001
0.001
0.01
0.1
1
10
t, TIME (s)
Figure 12. Thermal Response
ORDERING INFORMATION
Package
Shipping†
NTB65N02R
D2PAK
50 Units / Rail
NTB65N02RG
D2PAK
50 Units / Rail
Device
(Pb−Free)
NTB65N02RT4
D2PAK
800 / Tape & Reel
NTB65N02RT4G
D2PAK
800 / Tape & Reel
(Pb−Free)
NTP65N02R
TO−220AB
50 Units / Rail
NTP65N02RG
TO−220AB
(Pb−Free)
50 Units / Rail
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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5
NTB65N02R, NTP65N02R
PACKAGE DIMENSIONS
TO−220AB
CASE 221A−09
ISSUE AA
−T−
B
SEATING
PLANE
C
F
T
S
4
DIM
A
B
C
D
F
G
H
J
K
L
N
Q
R
S
T
U
V
Z
A
Q
1 2 3
U
H
K
Z
L
R
V
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
J
G
D
N
INCHES
MIN
MAX
0.570
0.620
0.380
0.405
0.160
0.190
0.025
0.035
0.142
0.147
0.095
0.105
0.110
0.155
0.018
0.025
0.500
0.562
0.045
0.060
0.190
0.210
0.100
0.120
0.080
0.110
0.045
0.055
0.235
0.255
0.000
0.050
0.045
−−−
−−−
0.080
STYLE 5:
PIN 1.
2.
3.
4.
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6
GATE
DRAIN
SOURCE
DRAIN
MILLIMETERS
MIN
MAX
14.48
15.75
9.66
10.28
4.07
4.82
0.64
0.88
3.61
3.73
2.42
2.66
2.80
3.93
0.46
0.64
12.70
14.27
1.15
1.52
4.83
5.33
2.54
3.04
2.04
2.79
1.15
1.39
5.97
6.47
0.00
1.27
1.15
−−−
−−−
2.04
NTB65N02R, NTP65N02R
PACKAGE DIMENSIONS
D2PAK
CASE 418AA−01
ISSUE O
C
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
E
V
W
−B−
4
DIM
A
B
C
D
E
F
G
J
K
M
S
V
A
1
2
S
3
−T−
SEATING
PLANE
K
W
J
G
D 3 PL
0.13 (0.005)
T B
M
STYLE 2:
PIN 1.
2.
3.
4.
M
VARIABLE
CONFIGURATION
ZONE
U
M
INCHES
MIN
MAX
0.340 0.380
0.380 0.405
0.160 0.190
0.020 0.036
0.045 0.055
0.310
−−−
0.100 BSC
0.018 0.025
0.090
0.110
0.280
−−−
0.575 0.625
0.045 0.055
M
M
F
F
F
VIEW W−W
1
VIEW W−W
2
VIEW W−W
3
SOLDERING FOOTPRINT*
8.38
0.33
1.016
0.04
10.66
0.42
5.08
0.20
3.05
0.12
17.02
0.67
SCALE 3:1
mm inches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
7
GATE
DRAIN
SOURCE
DRAIN
MILLIMETERS
MIN
MAX
8.64
9.65
9.65 10.29
4.06
4.83
0.51
0.92
1.14
1.40
7.87
−−−
2.54 BSC
0.46
0.64
2.29
2.79
7.11
−−−
14.60 15.88
1.14
1.40
NTB65N02R, NTP65N02R
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
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8
For additional information, please contact your
local Sales Representative.
NTB65N02R/D